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authorStephen Warren <swarren@nvidia.com>2011-12-15 16:23:34 -0500
committerStephen Warren <swarren@nvidia.com>2012-04-18 12:26:39 -0400
commitb7449d95b0cbfb06b9ca9de8c322c470fbc2a873 (patch)
tree9b504551205137e869e035a6ddf8681c741ca6ad /arch/arm/mach-tegra
parentf30d12b3ffb321c9d29bd1588940704d9bed2643 (diff)
ARM: tegra: Remove pre-pinctrl pinmux driver
The pinctrl driver is now active and used by all boards. Remove the old pinmux driver. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra20.h184
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra30.h320
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h302
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra20-tables.c244
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra30-tables.c376
-rw-r--r--arch/arm/mach-tegra/pinmux.c987
7 files changed, 0 insertions, 2416 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968115ec..2eb4445ddb14 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y += io.o
5obj-y += irq.o 5obj-y += irq.o
6obj-y += clock.o 6obj-y += clock.o
7obj-y += timer.o 7obj-y += timer.o
8obj-y += pinmux.o
9obj-y += fuse.o 8obj-y += fuse.o
10obj-y += pmc.o 9obj-y += pmc.o
11obj-y += flowctrl.o 10obj-y += flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
18obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
19obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 16obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 18obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1dbab17..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
18#define __MACH_TEGRA_PINMUX_TEGRA20_H
19
20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0,
22 TEGRA_PINGROUP_ATB,
23 TEGRA_PINGROUP_ATC,
24 TEGRA_PINGROUP_ATD,
25 TEGRA_PINGROUP_ATE,
26 TEGRA_PINGROUP_CDEV1,
27 TEGRA_PINGROUP_CDEV2,
28 TEGRA_PINGROUP_CRTP,
29 TEGRA_PINGROUP_CSUS,
30 TEGRA_PINGROUP_DAP1,
31 TEGRA_PINGROUP_DAP2,
32 TEGRA_PINGROUP_DAP3,
33 TEGRA_PINGROUP_DAP4,
34 TEGRA_PINGROUP_DDC,
35 TEGRA_PINGROUP_DTA,
36 TEGRA_PINGROUP_DTB,
37 TEGRA_PINGROUP_DTC,
38 TEGRA_PINGROUP_DTD,
39 TEGRA_PINGROUP_DTE,
40 TEGRA_PINGROUP_DTF,
41 TEGRA_PINGROUP_GMA,
42 TEGRA_PINGROUP_GMB,
43 TEGRA_PINGROUP_GMC,
44 TEGRA_PINGROUP_GMD,
45 TEGRA_PINGROUP_GME,
46 TEGRA_PINGROUP_GPU,
47 TEGRA_PINGROUP_GPU7,
48 TEGRA_PINGROUP_GPV,
49 TEGRA_PINGROUP_HDINT,
50 TEGRA_PINGROUP_I2CP,
51 TEGRA_PINGROUP_IRRX,
52 TEGRA_PINGROUP_IRTX,
53 TEGRA_PINGROUP_KBCA,
54 TEGRA_PINGROUP_KBCB,
55 TEGRA_PINGROUP_KBCC,
56 TEGRA_PINGROUP_KBCD,
57 TEGRA_PINGROUP_KBCE,
58 TEGRA_PINGROUP_KBCF,
59 TEGRA_PINGROUP_LCSN,
60 TEGRA_PINGROUP_LD0,
61 TEGRA_PINGROUP_LD1,
62 TEGRA_PINGROUP_LD10,
63 TEGRA_PINGROUP_LD11,
64 TEGRA_PINGROUP_LD12,
65 TEGRA_PINGROUP_LD13,
66 TEGRA_PINGROUP_LD14,
67 TEGRA_PINGROUP_LD15,
68 TEGRA_PINGROUP_LD16,
69 TEGRA_PINGROUP_LD17,
70 TEGRA_PINGROUP_LD2,
71 TEGRA_PINGROUP_LD3,
72 TEGRA_PINGROUP_LD4,
73 TEGRA_PINGROUP_LD5,
74 TEGRA_PINGROUP_LD6,
75 TEGRA_PINGROUP_LD7,
76 TEGRA_PINGROUP_LD8,
77 TEGRA_PINGROUP_LD9,
78 TEGRA_PINGROUP_LDC,
79 TEGRA_PINGROUP_LDI,
80 TEGRA_PINGROUP_LHP0,
81 TEGRA_PINGROUP_LHP1,
82 TEGRA_PINGROUP_LHP2,
83 TEGRA_PINGROUP_LHS,
84 TEGRA_PINGROUP_LM0,
85 TEGRA_PINGROUP_LM1,
86 TEGRA_PINGROUP_LPP,
87 TEGRA_PINGROUP_LPW0,
88 TEGRA_PINGROUP_LPW1,
89 TEGRA_PINGROUP_LPW2,
90 TEGRA_PINGROUP_LSC0,
91 TEGRA_PINGROUP_LSC1,
92 TEGRA_PINGROUP_LSCK,
93 TEGRA_PINGROUP_LSDA,
94 TEGRA_PINGROUP_LSDI,
95 TEGRA_PINGROUP_LSPI,
96 TEGRA_PINGROUP_LVP0,
97 TEGRA_PINGROUP_LVP1,
98 TEGRA_PINGROUP_LVS,
99 TEGRA_PINGROUP_OWC,
100 TEGRA_PINGROUP_PMC,
101 TEGRA_PINGROUP_PTA,
102 TEGRA_PINGROUP_RM,
103 TEGRA_PINGROUP_SDB,
104 TEGRA_PINGROUP_SDC,
105 TEGRA_PINGROUP_SDD,
106 TEGRA_PINGROUP_SDIO1,
107 TEGRA_PINGROUP_SLXA,
108 TEGRA_PINGROUP_SLXC,
109 TEGRA_PINGROUP_SLXD,
110 TEGRA_PINGROUP_SLXK,
111 TEGRA_PINGROUP_SPDI,
112 TEGRA_PINGROUP_SPDO,
113 TEGRA_PINGROUP_SPIA,
114 TEGRA_PINGROUP_SPIB,
115 TEGRA_PINGROUP_SPIC,
116 TEGRA_PINGROUP_SPID,
117 TEGRA_PINGROUP_SPIE,
118 TEGRA_PINGROUP_SPIF,
119 TEGRA_PINGROUP_SPIG,
120 TEGRA_PINGROUP_SPIH,
121 TEGRA_PINGROUP_UAA,
122 TEGRA_PINGROUP_UAB,
123 TEGRA_PINGROUP_UAC,
124 TEGRA_PINGROUP_UAD,
125 TEGRA_PINGROUP_UCA,
126 TEGRA_PINGROUP_UCB,
127 TEGRA_PINGROUP_UDA,
128 /* these pin groups only have pullup and pull down control */
129 TEGRA_PINGROUP_CK32,
130 TEGRA_PINGROUP_DDRC,
131 TEGRA_PINGROUP_PMCA,
132 TEGRA_PINGROUP_PMCB,
133 TEGRA_PINGROUP_PMCC,
134 TEGRA_PINGROUP_PMCD,
135 TEGRA_PINGROUP_PMCE,
136 TEGRA_PINGROUP_XM2C,
137 TEGRA_PINGROUP_XM2D,
138 TEGRA_MAX_PINGROUP,
139};
140
141enum tegra_drive_pingroup {
142 TEGRA_DRIVE_PINGROUP_AO1 = 0,
143 TEGRA_DRIVE_PINGROUP_AO2,
144 TEGRA_DRIVE_PINGROUP_AT1,
145 TEGRA_DRIVE_PINGROUP_AT2,
146 TEGRA_DRIVE_PINGROUP_CDEV1,
147 TEGRA_DRIVE_PINGROUP_CDEV2,
148 TEGRA_DRIVE_PINGROUP_CSUS,
149 TEGRA_DRIVE_PINGROUP_DAP1,
150 TEGRA_DRIVE_PINGROUP_DAP2,
151 TEGRA_DRIVE_PINGROUP_DAP3,
152 TEGRA_DRIVE_PINGROUP_DAP4,
153 TEGRA_DRIVE_PINGROUP_DBG,
154 TEGRA_DRIVE_PINGROUP_LCD1,
155 TEGRA_DRIVE_PINGROUP_LCD2,
156 TEGRA_DRIVE_PINGROUP_SDMMC2,
157 TEGRA_DRIVE_PINGROUP_SDMMC3,
158 TEGRA_DRIVE_PINGROUP_SPI,
159 TEGRA_DRIVE_PINGROUP_UAA,
160 TEGRA_DRIVE_PINGROUP_UAB,
161 TEGRA_DRIVE_PINGROUP_UART2,
162 TEGRA_DRIVE_PINGROUP_UART3,
163 TEGRA_DRIVE_PINGROUP_VI1,
164 TEGRA_DRIVE_PINGROUP_VI2,
165 TEGRA_DRIVE_PINGROUP_XM2A,
166 TEGRA_DRIVE_PINGROUP_XM2C,
167 TEGRA_DRIVE_PINGROUP_XM2D,
168 TEGRA_DRIVE_PINGROUP_XM2CLK,
169 TEGRA_DRIVE_PINGROUP_MEMCOMP,
170 TEGRA_DRIVE_PINGROUP_SDIO1,
171 TEGRA_DRIVE_PINGROUP_CRT,
172 TEGRA_DRIVE_PINGROUP_DDC,
173 TEGRA_DRIVE_PINGROUP_GMA,
174 TEGRA_DRIVE_PINGROUP_GMB,
175 TEGRA_DRIVE_PINGROUP_GMC,
176 TEGRA_DRIVE_PINGROUP_GMD,
177 TEGRA_DRIVE_PINGROUP_GME,
178 TEGRA_DRIVE_PINGROUP_OWR,
179 TEGRA_DRIVE_PINGROUP_UAD,
180 TEGRA_MAX_DRIVE_PINGROUP,
181};
182
183#endif
184
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3eb2df1..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
19#define __MACH_TEGRA_PINMUX_TEGRA30_H
20
21enum tegra_pingroup {
22 TEGRA_PINGROUP_ULPI_DATA0 = 0,
23 TEGRA_PINGROUP_ULPI_DATA1,
24 TEGRA_PINGROUP_ULPI_DATA2,
25 TEGRA_PINGROUP_ULPI_DATA3,
26 TEGRA_PINGROUP_ULPI_DATA4,
27 TEGRA_PINGROUP_ULPI_DATA5,
28 TEGRA_PINGROUP_ULPI_DATA6,
29 TEGRA_PINGROUP_ULPI_DATA7,
30 TEGRA_PINGROUP_ULPI_CLK,
31 TEGRA_PINGROUP_ULPI_DIR,
32 TEGRA_PINGROUP_ULPI_NXT,
33 TEGRA_PINGROUP_ULPI_STP,
34 TEGRA_PINGROUP_DAP3_FS,
35 TEGRA_PINGROUP_DAP3_DIN,
36 TEGRA_PINGROUP_DAP3_DOUT,
37 TEGRA_PINGROUP_DAP3_SCLK,
38 TEGRA_PINGROUP_GPIO_PV0,
39 TEGRA_PINGROUP_GPIO_PV1,
40 TEGRA_PINGROUP_SDMMC1_CLK,
41 TEGRA_PINGROUP_SDMMC1_CMD,
42 TEGRA_PINGROUP_SDMMC1_DAT3,
43 TEGRA_PINGROUP_SDMMC1_DAT2,
44 TEGRA_PINGROUP_SDMMC1_DAT1,
45 TEGRA_PINGROUP_SDMMC1_DAT0,
46 TEGRA_PINGROUP_GPIO_PV2,
47 TEGRA_PINGROUP_GPIO_PV3,
48 TEGRA_PINGROUP_CLK2_OUT,
49 TEGRA_PINGROUP_CLK2_REQ,
50 TEGRA_PINGROUP_LCD_PWR1,
51 TEGRA_PINGROUP_LCD_PWR2,
52 TEGRA_PINGROUP_LCD_SDIN,
53 TEGRA_PINGROUP_LCD_SDOUT,
54 TEGRA_PINGROUP_LCD_WR_N,
55 TEGRA_PINGROUP_LCD_CS0_N,
56 TEGRA_PINGROUP_LCD_DC0,
57 TEGRA_PINGROUP_LCD_SCK,
58 TEGRA_PINGROUP_LCD_PWR0,
59 TEGRA_PINGROUP_LCD_PCLK,
60 TEGRA_PINGROUP_LCD_DE,
61 TEGRA_PINGROUP_LCD_HSYNC,
62 TEGRA_PINGROUP_LCD_VSYNC,
63 TEGRA_PINGROUP_LCD_D0,
64 TEGRA_PINGROUP_LCD_D1,
65 TEGRA_PINGROUP_LCD_D2,
66 TEGRA_PINGROUP_LCD_D3,
67 TEGRA_PINGROUP_LCD_D4,
68 TEGRA_PINGROUP_LCD_D5,
69 TEGRA_PINGROUP_LCD_D6,
70 TEGRA_PINGROUP_LCD_D7,
71 TEGRA_PINGROUP_LCD_D8,
72 TEGRA_PINGROUP_LCD_D9,
73 TEGRA_PINGROUP_LCD_D10,
74 TEGRA_PINGROUP_LCD_D11,
75 TEGRA_PINGROUP_LCD_D12,
76 TEGRA_PINGROUP_LCD_D13,
77 TEGRA_PINGROUP_LCD_D14,
78 TEGRA_PINGROUP_LCD_D15,
79 TEGRA_PINGROUP_LCD_D16,
80 TEGRA_PINGROUP_LCD_D17,
81 TEGRA_PINGROUP_LCD_D18,
82 TEGRA_PINGROUP_LCD_D19,
83 TEGRA_PINGROUP_LCD_D20,
84 TEGRA_PINGROUP_LCD_D21,
85 TEGRA_PINGROUP_LCD_D22,
86 TEGRA_PINGROUP_LCD_D23,
87 TEGRA_PINGROUP_LCD_CS1_N,
88 TEGRA_PINGROUP_LCD_M1,
89 TEGRA_PINGROUP_LCD_DC1,
90 TEGRA_PINGROUP_HDMI_INT,
91 TEGRA_PINGROUP_DDC_SCL,
92 TEGRA_PINGROUP_DDC_SDA,
93 TEGRA_PINGROUP_CRT_HSYNC,
94 TEGRA_PINGROUP_CRT_VSYNC,
95 TEGRA_PINGROUP_VI_D0,
96 TEGRA_PINGROUP_VI_D1,
97 TEGRA_PINGROUP_VI_D2,
98 TEGRA_PINGROUP_VI_D3,
99 TEGRA_PINGROUP_VI_D4,
100 TEGRA_PINGROUP_VI_D5,
101 TEGRA_PINGROUP_VI_D6,
102 TEGRA_PINGROUP_VI_D7,
103 TEGRA_PINGROUP_VI_D8,
104 TEGRA_PINGROUP_VI_D9,
105 TEGRA_PINGROUP_VI_D10,
106 TEGRA_PINGROUP_VI_D11,
107 TEGRA_PINGROUP_VI_PCLK,
108 TEGRA_PINGROUP_VI_MCLK,
109 TEGRA_PINGROUP_VI_VSYNC,
110 TEGRA_PINGROUP_VI_HSYNC,
111 TEGRA_PINGROUP_UART2_RXD,
112 TEGRA_PINGROUP_UART2_TXD,
113 TEGRA_PINGROUP_UART2_RTS_N,
114 TEGRA_PINGROUP_UART2_CTS_N,
115 TEGRA_PINGROUP_UART3_TXD,
116 TEGRA_PINGROUP_UART3_RXD,
117 TEGRA_PINGROUP_UART3_CTS_N,
118 TEGRA_PINGROUP_UART3_RTS_N,
119 TEGRA_PINGROUP_GPIO_PU0,
120 TEGRA_PINGROUP_GPIO_PU1,
121 TEGRA_PINGROUP_GPIO_PU2,
122 TEGRA_PINGROUP_GPIO_PU3,
123 TEGRA_PINGROUP_GPIO_PU4,
124 TEGRA_PINGROUP_GPIO_PU5,
125 TEGRA_PINGROUP_GPIO_PU6,
126 TEGRA_PINGROUP_GEN1_I2C_SDA,
127 TEGRA_PINGROUP_GEN1_I2C_SCL,
128 TEGRA_PINGROUP_DAP4_FS,
129 TEGRA_PINGROUP_DAP4_DIN,
130 TEGRA_PINGROUP_DAP4_DOUT,
131 TEGRA_PINGROUP_DAP4_SCLK,
132 TEGRA_PINGROUP_CLK3_OUT,
133 TEGRA_PINGROUP_CLK3_REQ,
134 TEGRA_PINGROUP_GMI_WP_N,
135 TEGRA_PINGROUP_GMI_IORDY,
136 TEGRA_PINGROUP_GMI_WAIT,
137 TEGRA_PINGROUP_GMI_ADV_N,
138 TEGRA_PINGROUP_GMI_CLK,
139 TEGRA_PINGROUP_GMI_CS0_N,
140 TEGRA_PINGROUP_GMI_CS1_N,
141 TEGRA_PINGROUP_GMI_CS2_N,
142 TEGRA_PINGROUP_GMI_CS3_N,
143 TEGRA_PINGROUP_GMI_CS4_N,
144 TEGRA_PINGROUP_GMI_CS6_N,
145 TEGRA_PINGROUP_GMI_CS7_N,
146 TEGRA_PINGROUP_GMI_AD0,
147 TEGRA_PINGROUP_GMI_AD1,
148 TEGRA_PINGROUP_GMI_AD2,
149 TEGRA_PINGROUP_GMI_AD3,
150 TEGRA_PINGROUP_GMI_AD4,
151 TEGRA_PINGROUP_GMI_AD5,
152 TEGRA_PINGROUP_GMI_AD6,
153 TEGRA_PINGROUP_GMI_AD7,
154 TEGRA_PINGROUP_GMI_AD8,
155 TEGRA_PINGROUP_GMI_AD9,
156 TEGRA_PINGROUP_GMI_AD10,
157 TEGRA_PINGROUP_GMI_AD11,
158 TEGRA_PINGROUP_GMI_AD12,
159 TEGRA_PINGROUP_GMI_AD13,
160 TEGRA_PINGROUP_GMI_AD14,
161 TEGRA_PINGROUP_GMI_AD15,
162 TEGRA_PINGROUP_GMI_A16,
163 TEGRA_PINGROUP_GMI_A17,
164 TEGRA_PINGROUP_GMI_A18,
165 TEGRA_PINGROUP_GMI_A19,
166 TEGRA_PINGROUP_GMI_WR_N,
167 TEGRA_PINGROUP_GMI_OE_N,
168 TEGRA_PINGROUP_GMI_DQS,
169 TEGRA_PINGROUP_GMI_RST_N,
170 TEGRA_PINGROUP_GEN2_I2C_SCL,
171 TEGRA_PINGROUP_GEN2_I2C_SDA,
172 TEGRA_PINGROUP_SDMMC4_CLK,
173 TEGRA_PINGROUP_SDMMC4_CMD,
174 TEGRA_PINGROUP_SDMMC4_DAT0,
175 TEGRA_PINGROUP_SDMMC4_DAT1,
176 TEGRA_PINGROUP_SDMMC4_DAT2,
177 TEGRA_PINGROUP_SDMMC4_DAT3,
178 TEGRA_PINGROUP_SDMMC4_DAT4,
179 TEGRA_PINGROUP_SDMMC4_DAT5,
180 TEGRA_PINGROUP_SDMMC4_DAT6,
181 TEGRA_PINGROUP_SDMMC4_DAT7,
182 TEGRA_PINGROUP_SDMMC4_RST_N,
183 TEGRA_PINGROUP_CAM_MCLK,
184 TEGRA_PINGROUP_GPIO_PCC1,
185 TEGRA_PINGROUP_GPIO_PBB0,
186 TEGRA_PINGROUP_CAM_I2C_SCL,
187 TEGRA_PINGROUP_CAM_I2C_SDA,
188 TEGRA_PINGROUP_GPIO_PBB3,
189 TEGRA_PINGROUP_GPIO_PBB4,
190 TEGRA_PINGROUP_GPIO_PBB5,
191 TEGRA_PINGROUP_GPIO_PBB6,
192 TEGRA_PINGROUP_GPIO_PBB7,
193 TEGRA_PINGROUP_GPIO_PCC2,
194 TEGRA_PINGROUP_JTAG_RTCK,
195 TEGRA_PINGROUP_PWR_I2C_SCL,
196 TEGRA_PINGROUP_PWR_I2C_SDA,
197 TEGRA_PINGROUP_KB_ROW0,
198 TEGRA_PINGROUP_KB_ROW1,
199 TEGRA_PINGROUP_KB_ROW2,
200 TEGRA_PINGROUP_KB_ROW3,
201 TEGRA_PINGROUP_KB_ROW4,
202 TEGRA_PINGROUP_KB_ROW5,
203 TEGRA_PINGROUP_KB_ROW6,
204 TEGRA_PINGROUP_KB_ROW7,
205 TEGRA_PINGROUP_KB_ROW8,
206 TEGRA_PINGROUP_KB_ROW9,
207 TEGRA_PINGROUP_KB_ROW10,
208 TEGRA_PINGROUP_KB_ROW11,
209 TEGRA_PINGROUP_KB_ROW12,
210 TEGRA_PINGROUP_KB_ROW13,
211 TEGRA_PINGROUP_KB_ROW14,
212 TEGRA_PINGROUP_KB_ROW15,
213 TEGRA_PINGROUP_KB_COL0,
214 TEGRA_PINGROUP_KB_COL1,
215 TEGRA_PINGROUP_KB_COL2,
216 TEGRA_PINGROUP_KB_COL3,
217 TEGRA_PINGROUP_KB_COL4,
218 TEGRA_PINGROUP_KB_COL5,
219 TEGRA_PINGROUP_KB_COL6,
220 TEGRA_PINGROUP_KB_COL7,
221 TEGRA_PINGROUP_CLK_32K_OUT,
222 TEGRA_PINGROUP_SYS_CLK_REQ,
223 TEGRA_PINGROUP_CORE_PWR_REQ,
224 TEGRA_PINGROUP_CPU_PWR_REQ,
225 TEGRA_PINGROUP_PWR_INT_N,
226 TEGRA_PINGROUP_CLK_32K_IN,
227 TEGRA_PINGROUP_OWR,
228 TEGRA_PINGROUP_DAP1_FS,
229 TEGRA_PINGROUP_DAP1_DIN,
230 TEGRA_PINGROUP_DAP1_DOUT,
231 TEGRA_PINGROUP_DAP1_SCLK,
232 TEGRA_PINGROUP_CLK1_REQ,
233 TEGRA_PINGROUP_CLK1_OUT,
234 TEGRA_PINGROUP_SPDIF_IN,
235 TEGRA_PINGROUP_SPDIF_OUT,
236 TEGRA_PINGROUP_DAP2_FS,
237 TEGRA_PINGROUP_DAP2_DIN,
238 TEGRA_PINGROUP_DAP2_DOUT,
239 TEGRA_PINGROUP_DAP2_SCLK,
240 TEGRA_PINGROUP_SPI2_MOSI,
241 TEGRA_PINGROUP_SPI2_MISO,
242 TEGRA_PINGROUP_SPI2_CS0_N,
243 TEGRA_PINGROUP_SPI2_SCK,
244 TEGRA_PINGROUP_SPI1_MOSI,
245 TEGRA_PINGROUP_SPI1_SCK,
246 TEGRA_PINGROUP_SPI1_CS0_N,
247 TEGRA_PINGROUP_SPI1_MISO,
248 TEGRA_PINGROUP_SPI2_CS1_N,
249 TEGRA_PINGROUP_SPI2_CS2_N,
250 TEGRA_PINGROUP_SDMMC3_CLK,
251 TEGRA_PINGROUP_SDMMC3_CMD,
252 TEGRA_PINGROUP_SDMMC3_DAT0,
253 TEGRA_PINGROUP_SDMMC3_DAT1,
254 TEGRA_PINGROUP_SDMMC3_DAT2,
255 TEGRA_PINGROUP_SDMMC3_DAT3,
256 TEGRA_PINGROUP_SDMMC3_DAT4,
257 TEGRA_PINGROUP_SDMMC3_DAT5,
258 TEGRA_PINGROUP_SDMMC3_DAT6,
259 TEGRA_PINGROUP_SDMMC3_DAT7,
260 TEGRA_PINGROUP_PEX_L0_PRSNT_N,
261 TEGRA_PINGROUP_PEX_L0_RST_N,
262 TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
263 TEGRA_PINGROUP_PEX_WAKE_N,
264 TEGRA_PINGROUP_PEX_L1_PRSNT_N,
265 TEGRA_PINGROUP_PEX_L1_RST_N,
266 TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
267 TEGRA_PINGROUP_PEX_L2_PRSNT_N,
268 TEGRA_PINGROUP_PEX_L2_RST_N,
269 TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
270 TEGRA_PINGROUP_HDMI_CEC,
271 TEGRA_MAX_PINGROUP,
272};
273
274enum tegra_drive_pingroup {
275 TEGRA_DRIVE_PINGROUP_AO1 = 0,
276 TEGRA_DRIVE_PINGROUP_AO2,
277 TEGRA_DRIVE_PINGROUP_AT1,
278 TEGRA_DRIVE_PINGROUP_AT2,
279 TEGRA_DRIVE_PINGROUP_AT3,
280 TEGRA_DRIVE_PINGROUP_AT4,
281 TEGRA_DRIVE_PINGROUP_AT5,
282 TEGRA_DRIVE_PINGROUP_CDEV1,
283 TEGRA_DRIVE_PINGROUP_CDEV2,
284 TEGRA_DRIVE_PINGROUP_CSUS,
285 TEGRA_DRIVE_PINGROUP_DAP1,
286 TEGRA_DRIVE_PINGROUP_DAP2,
287 TEGRA_DRIVE_PINGROUP_DAP3,
288 TEGRA_DRIVE_PINGROUP_DAP4,
289 TEGRA_DRIVE_PINGROUP_DBG,
290 TEGRA_DRIVE_PINGROUP_LCD1,
291 TEGRA_DRIVE_PINGROUP_LCD2,
292 TEGRA_DRIVE_PINGROUP_SDIO2,
293 TEGRA_DRIVE_PINGROUP_SDIO3,
294 TEGRA_DRIVE_PINGROUP_SPI,
295 TEGRA_DRIVE_PINGROUP_UAA,
296 TEGRA_DRIVE_PINGROUP_UAB,
297 TEGRA_DRIVE_PINGROUP_UART2,
298 TEGRA_DRIVE_PINGROUP_UART3,
299 TEGRA_DRIVE_PINGROUP_VI1,
300 TEGRA_DRIVE_PINGROUP_SDIO1,
301 TEGRA_DRIVE_PINGROUP_CRT,
302 TEGRA_DRIVE_PINGROUP_DDC,
303 TEGRA_DRIVE_PINGROUP_GMA,
304 TEGRA_DRIVE_PINGROUP_GMB,
305 TEGRA_DRIVE_PINGROUP_GMC,
306 TEGRA_DRIVE_PINGROUP_GMD,
307 TEGRA_DRIVE_PINGROUP_GME,
308 TEGRA_DRIVE_PINGROUP_GMF,
309 TEGRA_DRIVE_PINGROUP_GMG,
310 TEGRA_DRIVE_PINGROUP_GMH,
311 TEGRA_DRIVE_PINGROUP_OWR,
312 TEGRA_DRIVE_PINGROUP_UAD,
313 TEGRA_DRIVE_PINGROUP_GPV,
314 TEGRA_DRIVE_PINGROUP_DEV3,
315 TEGRA_DRIVE_PINGROUP_CEC,
316 TEGRA_MAX_DRIVE_PINGROUP,
317};
318
319#endif
320
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f1792c8ff..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_H
19#define __MACH_TEGRA_PINMUX_H
20
21enum tegra_mux_func {
22 TEGRA_MUX_RSVD = 0x8000,
23 TEGRA_MUX_RSVD1 = 0x8000,
24 TEGRA_MUX_RSVD2 = 0x8001,
25 TEGRA_MUX_RSVD3 = 0x8002,
26 TEGRA_MUX_RSVD4 = 0x8003,
27 TEGRA_MUX_INVALID = 0x4000,
28 TEGRA_MUX_NONE = -1,
29 TEGRA_MUX_AHB_CLK,
30 TEGRA_MUX_APB_CLK,
31 TEGRA_MUX_AUDIO_SYNC,
32 TEGRA_MUX_CRT,
33 TEGRA_MUX_DAP1,
34 TEGRA_MUX_DAP2,
35 TEGRA_MUX_DAP3,
36 TEGRA_MUX_DAP4,
37 TEGRA_MUX_DAP5,
38 TEGRA_MUX_DISPLAYA,
39 TEGRA_MUX_DISPLAYB,
40 TEGRA_MUX_EMC_TEST0_DLL,
41 TEGRA_MUX_EMC_TEST1_DLL,
42 TEGRA_MUX_GMI,
43 TEGRA_MUX_GMI_INT,
44 TEGRA_MUX_HDMI,
45 TEGRA_MUX_I2C,
46 TEGRA_MUX_I2C2,
47 TEGRA_MUX_I2C3,
48 TEGRA_MUX_IDE,
49 TEGRA_MUX_IRDA,
50 TEGRA_MUX_KBC,
51 TEGRA_MUX_MIO,
52 TEGRA_MUX_MIPI_HS,
53 TEGRA_MUX_NAND,
54 TEGRA_MUX_OSC,
55 TEGRA_MUX_OWR,
56 TEGRA_MUX_PCIE,
57 TEGRA_MUX_PLLA_OUT,
58 TEGRA_MUX_PLLC_OUT1,
59 TEGRA_MUX_PLLM_OUT1,
60 TEGRA_MUX_PLLP_OUT2,
61 TEGRA_MUX_PLLP_OUT3,
62 TEGRA_MUX_PLLP_OUT4,
63 TEGRA_MUX_PWM,
64 TEGRA_MUX_PWR_INTR,
65 TEGRA_MUX_PWR_ON,
66 TEGRA_MUX_RTCK,
67 TEGRA_MUX_SDIO1,
68 TEGRA_MUX_SDIO2,
69 TEGRA_MUX_SDIO3,
70 TEGRA_MUX_SDIO4,
71 TEGRA_MUX_SFLASH,
72 TEGRA_MUX_SPDIF,
73 TEGRA_MUX_SPI1,
74 TEGRA_MUX_SPI2,
75 TEGRA_MUX_SPI2_ALT,
76 TEGRA_MUX_SPI3,
77 TEGRA_MUX_SPI4,
78 TEGRA_MUX_TRACE,
79 TEGRA_MUX_TWC,
80 TEGRA_MUX_UARTA,
81 TEGRA_MUX_UARTB,
82 TEGRA_MUX_UARTC,
83 TEGRA_MUX_UARTD,
84 TEGRA_MUX_UARTE,
85 TEGRA_MUX_ULPI,
86 TEGRA_MUX_VI,
87 TEGRA_MUX_VI_SENSOR_CLK,
88 TEGRA_MUX_XIO,
89 TEGRA_MUX_BLINK,
90 TEGRA_MUX_CEC,
91 TEGRA_MUX_CLK12,
92 TEGRA_MUX_DAP,
93 TEGRA_MUX_DAPSDMMC2,
94 TEGRA_MUX_DDR,
95 TEGRA_MUX_DEV3,
96 TEGRA_MUX_DTV,
97 TEGRA_MUX_VI_ALT1,
98 TEGRA_MUX_VI_ALT2,
99 TEGRA_MUX_VI_ALT3,
100 TEGRA_MUX_EMC_DLL,
101 TEGRA_MUX_EXTPERIPH1,
102 TEGRA_MUX_EXTPERIPH2,
103 TEGRA_MUX_EXTPERIPH3,
104 TEGRA_MUX_GMI_ALT,
105 TEGRA_MUX_HDA,
106 TEGRA_MUX_HSI,
107 TEGRA_MUX_I2C4,
108 TEGRA_MUX_I2C5,
109 TEGRA_MUX_I2CPWR,
110 TEGRA_MUX_I2S0,
111 TEGRA_MUX_I2S1,
112 TEGRA_MUX_I2S2,
113 TEGRA_MUX_I2S3,
114 TEGRA_MUX_I2S4,
115 TEGRA_MUX_NAND_ALT,
116 TEGRA_MUX_POPSDIO4,
117 TEGRA_MUX_POPSDMMC4,
118 TEGRA_MUX_PWM0,
119 TEGRA_MUX_PWM1,
120 TEGRA_MUX_PWM2,
121 TEGRA_MUX_PWM3,
122 TEGRA_MUX_SATA,
123 TEGRA_MUX_SPI5,
124 TEGRA_MUX_SPI6,
125 TEGRA_MUX_SYSCLK,
126 TEGRA_MUX_VGP1,
127 TEGRA_MUX_VGP2,
128 TEGRA_MUX_VGP3,
129 TEGRA_MUX_VGP4,
130 TEGRA_MUX_VGP5,
131 TEGRA_MUX_VGP6,
132 TEGRA_MUX_SAFE,
133 TEGRA_MAX_MUX,
134};
135
136enum tegra_pullupdown {
137 TEGRA_PUPD_NORMAL = 0,
138 TEGRA_PUPD_PULL_DOWN,
139 TEGRA_PUPD_PULL_UP,
140};
141
142enum tegra_tristate {
143 TEGRA_TRI_NORMAL = 0,
144 TEGRA_TRI_TRISTATE = 1,
145};
146
147enum tegra_pin_io {
148 TEGRA_PIN_OUTPUT = 0,
149 TEGRA_PIN_INPUT = 1,
150};
151
152enum tegra_vddio {
153 TEGRA_VDDIO_BB = 0,
154 TEGRA_VDDIO_LCD,
155 TEGRA_VDDIO_VI,
156 TEGRA_VDDIO_UART,
157 TEGRA_VDDIO_DDR,
158 TEGRA_VDDIO_NAND,
159 TEGRA_VDDIO_SYS,
160 TEGRA_VDDIO_AUDIO,
161 TEGRA_VDDIO_SD,
162 TEGRA_VDDIO_CAM,
163 TEGRA_VDDIO_GMI,
164 TEGRA_VDDIO_PEXCTL,
165 TEGRA_VDDIO_SDMMC1,
166 TEGRA_VDDIO_SDMMC3,
167 TEGRA_VDDIO_SDMMC4,
168};
169
170struct tegra_pingroup_config {
171 int pingroup;
172 enum tegra_mux_func func;
173 enum tegra_pullupdown pupd;
174 enum tegra_tristate tristate;
175};
176
177enum tegra_slew {
178 TEGRA_SLEW_FASTEST = 0,
179 TEGRA_SLEW_FAST,
180 TEGRA_SLEW_SLOW,
181 TEGRA_SLEW_SLOWEST,
182 TEGRA_MAX_SLEW,
183};
184
185enum tegra_pull_strength {
186 TEGRA_PULL_0 = 0,
187 TEGRA_PULL_1,
188 TEGRA_PULL_2,
189 TEGRA_PULL_3,
190 TEGRA_PULL_4,
191 TEGRA_PULL_5,
192 TEGRA_PULL_6,
193 TEGRA_PULL_7,
194 TEGRA_PULL_8,
195 TEGRA_PULL_9,
196 TEGRA_PULL_10,
197 TEGRA_PULL_11,
198 TEGRA_PULL_12,
199 TEGRA_PULL_13,
200 TEGRA_PULL_14,
201 TEGRA_PULL_15,
202 TEGRA_PULL_16,
203 TEGRA_PULL_17,
204 TEGRA_PULL_18,
205 TEGRA_PULL_19,
206 TEGRA_PULL_20,
207 TEGRA_PULL_21,
208 TEGRA_PULL_22,
209 TEGRA_PULL_23,
210 TEGRA_PULL_24,
211 TEGRA_PULL_25,
212 TEGRA_PULL_26,
213 TEGRA_PULL_27,
214 TEGRA_PULL_28,
215 TEGRA_PULL_29,
216 TEGRA_PULL_30,
217 TEGRA_PULL_31,
218 TEGRA_MAX_PULL,
219};
220
221enum tegra_drive {
222 TEGRA_DRIVE_DIV_8 = 0,
223 TEGRA_DRIVE_DIV_4,
224 TEGRA_DRIVE_DIV_2,
225 TEGRA_DRIVE_DIV_1,
226 TEGRA_MAX_DRIVE,
227};
228
229enum tegra_hsm {
230 TEGRA_HSM_DISABLE = 0,
231 TEGRA_HSM_ENABLE,
232};
233
234enum tegra_schmitt {
235 TEGRA_SCHMITT_DISABLE = 0,
236 TEGRA_SCHMITT_ENABLE,
237};
238
239struct tegra_drive_pingroup_config {
240 int pingroup;
241 enum tegra_hsm hsm;
242 enum tegra_schmitt schmitt;
243 enum tegra_drive drive;
244 enum tegra_pull_strength pull_down;
245 enum tegra_pull_strength pull_up;
246 enum tegra_slew slew_rising;
247 enum tegra_slew slew_falling;
248};
249
250struct tegra_drive_pingroup_desc {
251 const char *name;
252 s16 reg_bank;
253 s16 reg;
254};
255
256struct tegra_pingroup_desc {
257 const char *name;
258 int funcs[4];
259 int func_safe;
260 int vddio;
261 enum tegra_pin_io io_default;
262 s16 tri_bank; /* Register bank the tri_reg exists within */
263 s16 mux_bank; /* Register bank the mux_reg exists within */
264 s16 pupd_bank; /* Register bank the pupd_reg exists within */
265 s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
266 s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
267 s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
268 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
269 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
270 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
271 s8 lock_bit; /* offset of the LOCK bit into mux register bit */
272 s8 od_bit; /* offset of the OD bit into mux register bit */
273 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
274};
275
276typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
277 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
278 int *pgdrive_max);
279
280void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
281 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
282
283void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
284 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
285
286int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
287int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
288
289void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
290 int len);
291
292void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
293 int len);
294void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
295 int len);
296void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
297 int len);
298void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
299 int len, enum tegra_tristate tristate);
300void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
301 int len, enum tegra_pullupdown pupd);
302#endif
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1280b7..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
3 *
4 * Common pinmux configurations for Tegra20 SoCs
5 *
6 * Copyright (C) 2010 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/spinlock.h>
26#include <linux/io.h>
27#include <linux/init.h>
28#include <linux/string.h>
29
30#include <mach/iomap.h>
31#include <mach/pinmux.h>
32#include <mach/pinmux-tegra20.h>
33#include <mach/suspend.h>
34
35#define TRISTATE_REG_A 0x14
36#define PIN_MUX_CTL_REG_A 0x80
37#define PULLUPDOWN_REG_A 0xa0
38#define PINGROUP_REG_A 0x868
39
40#define DRIVE_PINGROUP(pg_name, r) \
41 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
42 .name = #pg_name, \
43 .reg_bank = 3, \
44 .reg = ((r) - PINGROUP_REG_A) \
45 }
46
47static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
48 DRIVE_PINGROUP(AO1, 0x868),
49 DRIVE_PINGROUP(AO2, 0x86c),
50 DRIVE_PINGROUP(AT1, 0x870),
51 DRIVE_PINGROUP(AT2, 0x874),
52 DRIVE_PINGROUP(CDEV1, 0x878),
53 DRIVE_PINGROUP(CDEV2, 0x87c),
54 DRIVE_PINGROUP(CSUS, 0x880),
55 DRIVE_PINGROUP(DAP1, 0x884),
56 DRIVE_PINGROUP(DAP2, 0x888),
57 DRIVE_PINGROUP(DAP3, 0x88c),
58 DRIVE_PINGROUP(DAP4, 0x890),
59 DRIVE_PINGROUP(DBG, 0x894),
60 DRIVE_PINGROUP(LCD1, 0x898),
61 DRIVE_PINGROUP(LCD2, 0x89c),
62 DRIVE_PINGROUP(SDMMC2, 0x8a0),
63 DRIVE_PINGROUP(SDMMC3, 0x8a4),
64 DRIVE_PINGROUP(SPI, 0x8a8),
65 DRIVE_PINGROUP(UAA, 0x8ac),
66 DRIVE_PINGROUP(UAB, 0x8b0),
67 DRIVE_PINGROUP(UART2, 0x8b4),
68 DRIVE_PINGROUP(UART3, 0x8b8),
69 DRIVE_PINGROUP(VI1, 0x8bc),
70 DRIVE_PINGROUP(VI2, 0x8c0),
71 DRIVE_PINGROUP(XM2A, 0x8c4),
72 DRIVE_PINGROUP(XM2C, 0x8c8),
73 DRIVE_PINGROUP(XM2D, 0x8cc),
74 DRIVE_PINGROUP(XM2CLK, 0x8d0),
75 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
76 DRIVE_PINGROUP(SDIO1, 0x8e0),
77 DRIVE_PINGROUP(CRT, 0x8ec),
78 DRIVE_PINGROUP(DDC, 0x8f0),
79 DRIVE_PINGROUP(GMA, 0x8f4),
80 DRIVE_PINGROUP(GMB, 0x8f8),
81 DRIVE_PINGROUP(GMC, 0x8fc),
82 DRIVE_PINGROUP(GMD, 0x900),
83 DRIVE_PINGROUP(GME, 0x904),
84 DRIVE_PINGROUP(OWR, 0x908),
85 DRIVE_PINGROUP(UAD, 0x90c),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe, \
89 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
90 [TEGRA_PINGROUP_ ## pg_name] = { \
91 .name = #pg_name, \
92 .vddio = TEGRA_VDDIO_ ## vdd, \
93 .funcs = { \
94 TEGRA_MUX_ ## f0, \
95 TEGRA_MUX_ ## f1, \
96 TEGRA_MUX_ ## f2, \
97 TEGRA_MUX_ ## f3, \
98 }, \
99 .func_safe = TEGRA_MUX_ ## f_safe, \
100 .tri_bank = 0, \
101 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
102 .tri_bit = tri_b, \
103 .mux_bank = 1, \
104 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
105 .mux_bit = mux_b, \
106 .pupd_bank = 2, \
107 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
108 .pupd_bit = pupd_b, \
109 .lock_bit = -1, \
110 .od_bit = -1, \
111 .ioreset_bit = -1, \
112 .io_default = -1, \
113 }
114
115static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
116 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
117 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
118 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
119 PINGROUP(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 3, 0x80, 20, 0xA0, 6),
120 PINGROUP(ATE, NAND, IDE, NAND, GMI, RSVD, IDE, 0x18, 25, 0x80, 12, 0xA0, 8),
121 PINGROUP(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC, 0x14, 4, 0x88, 2, 0xA8, 0),
122 PINGROUP(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC, 0x14, 5, 0x88, 4, 0xA8, 2),
123 PINGROUP(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD, 0x20, 14, 0x98, 20, 0xA4, 24),
124 PINGROUP(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6, 0x88, 6, 0xAC, 24),
125 PINGROUP(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1, 0x14, 7, 0x88, 20, 0xA0, 10),
126 PINGROUP(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2, 0x14, 8, 0x88, 22, 0xA0, 12),
127 PINGROUP(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3, 0x14, 9, 0x88, 24, 0xA0, 14),
128 PINGROUP(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4, 0x14, 10, 0x88, 26, 0xA0, 16),
129 PINGROUP(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4, 0x18, 31, 0x88, 0, 0xB0, 28),
130 PINGROUP(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4, 0x14, 11, 0x84, 20, 0xA0, 18),
131 PINGROUP(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 12, 0x84, 22, 0xA0, 20),
132 PINGROUP(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1, 0x14, 13, 0x84, 26, 0xA0, 22),
133 PINGROUP(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1, 0x14, 14, 0x84, 28, 0xA0, 24),
134 PINGROUP(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1, 0x14, 15, 0x84, 30, 0xA0, 26),
135 PINGROUP(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4, 0x20, 12, 0x98, 30, 0xA0, 28),
136 PINGROUP(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3, 0x14, 28, 0x84, 0, 0xB0, 20),
137 PINGROUP(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI, 0x18, 29, 0x88, 28, 0xB0, 22),
138 PINGROUP(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4, 0x14, 29, 0x84, 2, 0xB0, 24),
139 PINGROUP(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI, 0x18, 30, 0x88, 30, 0xB0, 26),
140 PINGROUP(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI, 0x18, 0, 0x8C, 0, 0xA8, 24),
141 PINGROUP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4, 0x14, 16, 0x8C, 4, 0xA4, 20),
142 PINGROUP(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK, 0x20, 11, 0x98, 28, 0xA4, 6),
143 PINGROUP(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE, 0x14, 17, 0x8C, 2, 0xA0, 30),
144 PINGROUP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI, 0x1C, 23, 0x84, 4, 0xAC, 22),
145 PINGROUP(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 18, 0x88, 8, 0xA4, 2),
146 PINGROUP(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 20, 0x88, 18, 0xA8, 22),
147 PINGROUP(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB, 0x14, 19, 0x88, 16, 0xA8, 20),
148 PINGROUP(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC, 0x14, 22, 0x88, 10, 0xA4, 8),
149 PINGROUP(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x14, 21, 0x88, 12, 0xA4, 10),
150 PINGROUP(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC, 0x18, 26, 0x88, 14, 0xA4, 12),
151 PINGROUP(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC, 0x20, 10, 0x98, 26, 0xA4, 14),
152 PINGROUP(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC, 0x14, 26, 0x80, 28, 0xB0, 2),
153 PINGROUP(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC, 0x14, 27, 0x80, 26, 0xB0, 0),
154 PINGROUP(LCSN, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 31, 0x90, 12, 0xAC, 20),
155 PINGROUP(LD0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 0, 0x94, 0, 0xAC, 12),
156 PINGROUP(LD1, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 1, 0x94, 2, 0xAC, 12),
157 PINGROUP(LD10, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 10, 0x94, 20, 0xAC, 12),
158 PINGROUP(LD11, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 11, 0x94, 22, 0xAC, 12),
159 PINGROUP(LD12, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 12, 0x94, 24, 0xAC, 12),
160 PINGROUP(LD13, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 13, 0x94, 26, 0xAC, 12),
161 PINGROUP(LD14, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 14, 0x94, 28, 0xAC, 12),
162 PINGROUP(LD15, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 15, 0x94, 30, 0xAC, 12),
163 PINGROUP(LD16, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 16, 0x98, 0, 0xAC, 12),
164 PINGROUP(LD17, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 17, 0x98, 2, 0xAC, 12),
165 PINGROUP(LD2, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 2, 0x94, 4, 0xAC, 12),
166 PINGROUP(LD3, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 3, 0x94, 6, 0xAC, 12),
167 PINGROUP(LD4, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 4, 0x94, 8, 0xAC, 12),
168 PINGROUP(LD5, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 5, 0x94, 10, 0xAC, 12),
169 PINGROUP(LD6, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 6, 0x94, 12, 0xAC, 12),
170 PINGROUP(LD7, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 7, 0x94, 14, 0xAC, 12),
171 PINGROUP(LD8, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 8, 0x94, 16, 0xAC, 12),
172 PINGROUP(LD9, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 9, 0x94, 18, 0xAC, 12),
173 PINGROUP(LDC, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 30, 0x90, 14, 0xAC, 20),
174 PINGROUP(LDI, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 6, 0x98, 16, 0xAC, 18),
175 PINGROUP(LHP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 18, 0x98, 10, 0xAC, 16),
176 PINGROUP(LHP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 19, 0x98, 4, 0xAC, 14),
177 PINGROUP(LHP2, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 20, 0x98, 6, 0xAC, 14),
178 PINGROUP(LHS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x20, 7, 0x90, 22, 0xAC, 22),
179 PINGROUP(LM0, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, RSVD4, 0x1C, 24, 0x90, 26, 0xAC, 22),
180 PINGROUP(LM1, LCD, DISPLAYA, DISPLAYB, RSVD, CRT, RSVD3, 0x1C, 25, 0x90, 28, 0xAC, 22),
181 PINGROUP(LPP, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 8, 0x98, 14, 0xAC, 18),
182 PINGROUP(LPW0, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 3, 0x90, 0, 0xAC, 20),
183 PINGROUP(LPW1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x20, 4, 0x90, 2, 0xAC, 20),
184 PINGROUP(LPW2, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 5, 0x90, 4, 0xAC, 20),
185 PINGROUP(LSC0, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 27, 0x90, 18, 0xAC, 22),
186 PINGROUP(LSC1, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 28, 0x90, 20, 0xAC, 20),
187 PINGROUP(LSCK, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x1C, 29, 0x90, 16, 0xAC, 20),
188 PINGROUP(LSDA, LCD, DISPLAYA, DISPLAYB, SPI3, HDMI, DISPLAYA, 0x20, 1, 0x90, 8, 0xAC, 20),
189 PINGROUP(LSDI, LCD, DISPLAYA, DISPLAYB, SPI3, RSVD, DISPLAYA, 0x20, 2, 0x90, 6, 0xAC, 20),
190 PINGROUP(LSPI, LCD, DISPLAYA, DISPLAYB, XIO, HDMI, DISPLAYA, 0x20, 0, 0x90, 10, 0xAC, 22),
191 PINGROUP(LVP0, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 21, 0x90, 30, 0xAC, 22),
192 PINGROUP(LVP1, LCD, DISPLAYA, DISPLAYB, RSVD, RSVD, RSVD4, 0x1C, 22, 0x98, 8, 0xAC, 16),
193 PINGROUP(LVS, LCD, DISPLAYA, DISPLAYB, XIO, RSVD, RSVD4, 0x1C, 26, 0x90, 24, 0xAC, 22),
194 PINGROUP(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR, 0x14, 31, 0x84, 8, 0xB0, 30),
195 PINGROUP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, 0x14, 23, 0x98, 18, -1, -1),
196 PINGROUP(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4, 0x14, 24, 0x98, 22, 0xA4, 4),
197 PINGROUP(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4, 0x14, 25, 0x80, 14, 0xA4, 0),
198 PINGROUP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, 0x20, 15, 0x8C, 10, -1, -1),
199 PINGROUP(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC, 0x18, 1, 0x8C, 12, 0xAC, 28),
200 PINGROUP(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM, 0x18, 2, 0x8C, 14, 0xAC, 30),
201 PINGROUP(SDIO1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2, 0x14, 30, 0x80, 30, 0xB0, 18),
202 PINGROUP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 3, 0x84, 6, 0xA4, 22),
203 PINGROUP(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 5, 0x84, 10, 0xA4, 26),
204 PINGROUP(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4, 0x18, 6, 0x84, 12, 0xA4, 28),
205 PINGROUP(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, 0x18, 7, 0x84, 14, 0xA4, 30),
206 PINGROUP(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 8, 0x8C, 8, 0xA4, 16),
207 PINGROUP(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2, 0x18, 9, 0x8C, 6, 0xA4, 18),
208 PINGROUP(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 10, 0x8C, 30, 0xA8, 4),
209 PINGROUP(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 11, 0x8C, 28, 0xA8, 6),
210 PINGROUP(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI, 0x18, 12, 0x8C, 26, 0xA8, 8),
211 PINGROUP(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 13, 0x8C, 24, 0xA8, 10),
212 PINGROUP(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI, 0x18, 14, 0x8C, 22, 0xA8, 12),
213 PINGROUP(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4, 0x18, 15, 0x8C, 20, 0xA8, 14),
214 PINGROUP(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 16, 0x8C, 18, 0xA8, 16),
215 PINGROUP(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT, 0x18, 17, 0x8C, 16, 0xA8, 18),
216 PINGROUP(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 18, 0x80, 0, 0xAC, 0),
217 PINGROUP(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS, 0x18, 19, 0x80, 2, 0xAC, 2),
218 PINGROUP(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4, 0x18, 20, 0x80, 4, 0xAC, 4),
219 PINGROUP(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF, 0x18, 21, 0x80, 6, 0xAC, 6),
220 PINGROUP(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4, 0x18, 22, 0x84, 16, 0xAC, 8),
221 PINGROUP(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4, 0x18, 23, 0x84, 18, 0xAC, 10),
222 PINGROUP(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2, 0x20, 13, 0x80, 8, 0xB0, 16),
223 /* these pin groups only have pullup and pull down control */
224 PINGROUP(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 14),
225 PINGROUP(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xAC, 26),
226 PINGROUP(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 4),
227 PINGROUP(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 6),
228 PINGROUP(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 8),
229 PINGROUP(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 10),
230 PINGROUP(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xB0, 12),
231 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
232 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
233};
234
235void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
236 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
237 int *pgdrive_max)
238{
239 *pg = tegra_soc_pingroups;
240 *pg_max = TEGRA_MAX_PINGROUP;
241 *pgdrive = tegra_soc_drive_pingroups;
242 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
243}
244
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4c1c44..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
3 *
4 * Common pinmux configurations for Tegra30 SoCs
5 *
6 * Copyright (C) 2010,2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
26#include <linux/init.h>
27#include <linux/string.h>
28
29#include <mach/iomap.h>
30#include <mach/pinmux.h>
31#include <mach/pinmux-tegra30.h>
32#include <mach/suspend.h>
33
34#define PINGROUP_REG_A 0x868
35#define MUXCTL_REG_A 0x3000
36
37#define DRIVE_PINGROUP(pg_name, r) \
38 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
39 .name = #pg_name, \
40 .reg_bank = 0, \
41 .reg = ((r) - PINGROUP_REG_A) \
42 }
43
44static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
45 DRIVE_PINGROUP(AO1, 0x868),
46 DRIVE_PINGROUP(AO2, 0x86c),
47 DRIVE_PINGROUP(AT1, 0x870),
48 DRIVE_PINGROUP(AT2, 0x874),
49 DRIVE_PINGROUP(AT3, 0x878),
50 DRIVE_PINGROUP(AT4, 0x87c),
51 DRIVE_PINGROUP(AT5, 0x880),
52 DRIVE_PINGROUP(CDEV1, 0x884),
53 DRIVE_PINGROUP(CDEV2, 0x888),
54 DRIVE_PINGROUP(CSUS, 0x88c),
55 DRIVE_PINGROUP(DAP1, 0x890),
56 DRIVE_PINGROUP(DAP2, 0x894),
57 DRIVE_PINGROUP(DAP3, 0x898),
58 DRIVE_PINGROUP(DAP4, 0x89c),
59 DRIVE_PINGROUP(DBG, 0x8a0),
60 DRIVE_PINGROUP(LCD1, 0x8a4),
61 DRIVE_PINGROUP(LCD2, 0x8a8),
62 DRIVE_PINGROUP(SDIO2, 0x8ac),
63 DRIVE_PINGROUP(SDIO3, 0x8b0),
64 DRIVE_PINGROUP(SPI, 0x8b4),
65 DRIVE_PINGROUP(UAA, 0x8b8),
66 DRIVE_PINGROUP(UAB, 0x8bc),
67 DRIVE_PINGROUP(UART2, 0x8c0),
68 DRIVE_PINGROUP(UART3, 0x8c4),
69 DRIVE_PINGROUP(VI1, 0x8c8),
70 DRIVE_PINGROUP(SDIO1, 0x8ec),
71 DRIVE_PINGROUP(CRT, 0x8f8),
72 DRIVE_PINGROUP(DDC, 0x8fc),
73 DRIVE_PINGROUP(GMA, 0x900),
74 DRIVE_PINGROUP(GMB, 0x904),
75 DRIVE_PINGROUP(GMC, 0x908),
76 DRIVE_PINGROUP(GMD, 0x90c),
77 DRIVE_PINGROUP(GME, 0x910),
78 DRIVE_PINGROUP(GMF, 0x914),
79 DRIVE_PINGROUP(GMG, 0x918),
80 DRIVE_PINGROUP(GMH, 0x91c),
81 DRIVE_PINGROUP(OWR, 0x920),
82 DRIVE_PINGROUP(UAD, 0x924),
83 DRIVE_PINGROUP(GPV, 0x928),
84 DRIVE_PINGROUP(DEV3, 0x92c),
85 DRIVE_PINGROUP(CEC, 0x938),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
89 [TEGRA_PINGROUP_ ## pg_name] = { \
90 .name = #pg_name, \
91 .vddio = TEGRA_VDDIO_ ## vdd, \
92 .funcs = { \
93 TEGRA_MUX_ ## f0, \
94 TEGRA_MUX_ ## f1, \
95 TEGRA_MUX_ ## f2, \
96 TEGRA_MUX_ ## f3, \
97 }, \
98 .func_safe = TEGRA_MUX_ ## fs, \
99 .tri_bank = 1, \
100 .tri_reg = ((reg) - MUXCTL_REG_A), \
101 .tri_bit = 4, \
102 .mux_bank = 1, \
103 .mux_reg = ((reg) - MUXCTL_REG_A), \
104 .mux_bit = 0, \
105 .pupd_bank = 1, \
106 .pupd_reg = ((reg) - MUXCTL_REG_A), \
107 .pupd_bit = 2, \
108 .io_default = TEGRA_PIN_ ## iod, \
109 .od_bit = 6, \
110 .lock_bit = 7, \
111 .ioreset_bit = 8, \
112 }
113
114static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
115 /* NAME VDD f0 f1 f2 f3 fSafe io reg */
116 PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
117 PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
118 PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
119 PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
120 PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
121 PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
122 PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
123 PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
124 PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
125 PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
126 PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
127 PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
128 PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
129 PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
130 PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
131 PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
132 PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
133 PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
134 PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
135 PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
136 PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
137 PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
138 PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
139 PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
140 PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
141 PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
142 PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
143 PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
144 PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
145 PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
146 PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
147 PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
148 PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
149 PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
150 PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
151 PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
152 PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
153 PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
154 PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
155 PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
156 PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
157 PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
158 PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
159 PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
160 PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
161 PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
162 PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
163 PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
164 PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
165 PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
166 PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
167 PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
168 PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
169 PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
170 PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
171 PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
172 PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
173 PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
174 PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
175 PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
176 PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
177 PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
178 PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
179 PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
180 PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
181 PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
182 PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
183 PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
184 PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
185 PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
186 PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
187 PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
188 PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
189 PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
190 PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
191 PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
192 PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
193 PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
194 PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
195 PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
196 PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
197 PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
198 PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
199 PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
200 PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
201 PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
202 PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
203 PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
204 PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
205 PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
206 PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
207 PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
208 PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
209 PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
210 PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
211 PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
212 PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
213 PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
214 PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
215 PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
216 PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
217 PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
218 PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
219 PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
220 PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
221 PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
222 PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
223 PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
224 PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
225 PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
226 PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
227 PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
228 PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
229 PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
230 PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
231 PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
232 PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
233 PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
234 PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
235 PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
236 PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
237 PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
238 PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
239 PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
240 PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
241 PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
242 PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
243 PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
244 PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
245 PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
246 PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
247 PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
248 PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
249 PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
250 PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
251 PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
252 PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
253 PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
254 PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
255 PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
256 PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
257 PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
258 PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
259 PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
260 PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
261 PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
262 PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
263 PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
264 PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
265 PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
266 PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
267 PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
268 PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
269 PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
270 PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
271 PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
272 PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
273 PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
274 PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
275 PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
276 PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
277 PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
278 PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
279 PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
280 PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
281 PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
282 PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
283 PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
284 PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
285 PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
286 PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
287 PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
288 PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
289 PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
290 PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
291 PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
292 PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
293 PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
294 PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
295 PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
296 PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
297 PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
298 PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
299 PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
300 PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
301 PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
302 PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
303 PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
304 PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
305 PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
306 PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
307 PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
308 PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
309 PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
310 PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
311 PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
312 PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
313 PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
314 PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
315 PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
316 PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
317 PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
318 PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
319 PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
320 PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
321 PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
322 PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
323 PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
324 PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
325 PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
326 PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
327 PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
328 PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
329 PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
330 PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
331 PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
332 PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
333 PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
334 PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
335 PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
336 PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
337 PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
338 PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
339 PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
340 PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
341 PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
342 PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
343 PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
344 PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
345 PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
346 PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
347 PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
348 PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
349 PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
350 PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
351 PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
352 PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
353 PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
354 PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
355 PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
356 PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
357 PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
358 PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
359 PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
360 PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
361 PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
362 PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
363 PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
364 PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
365};
366
367void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
368 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
369 int *pgdrive_max)
370{
371 *pg = tegra_soc_pingroups;
372 *pg_max = TEGRA_MAX_PINGROUP;
373 *pgdrive = tegra_soc_drive_pingroups;
374 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
375}
376
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index 7867a12748dd..000000000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/platform_device.h>
24#include <linux/of_device.h>
25
26#include <mach/iomap.h>
27#include <mach/pinmux.h>
28
29#define HSM_EN(reg) (((reg) >> 2) & 0x1)
30#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
31#define LPMD(reg) (((reg) >> 4) & 0x3)
32#define DRVDN(reg) (((reg) >> 12) & 0x1f)
33#define DRVUP(reg) (((reg) >> 20) & 0x1f)
34#define SLWR(reg) (((reg) >> 28) & 0x3)
35#define SLWF(reg) (((reg) >> 30) & 0x3)
36
37static const struct tegra_pingroup_desc *pingroups;
38static const struct tegra_drive_pingroup_desc *drive_pingroups;
39static int pingroup_max;
40static int drive_max;
41
42static char *tegra_mux_names[TEGRA_MAX_MUX] = {
43 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
44 [TEGRA_MUX_APB_CLK] = "APB_CLK",
45 [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
46 [TEGRA_MUX_CRT] = "CRT",
47 [TEGRA_MUX_DAP1] = "DAP1",
48 [TEGRA_MUX_DAP2] = "DAP2",
49 [TEGRA_MUX_DAP3] = "DAP3",
50 [TEGRA_MUX_DAP4] = "DAP4",
51 [TEGRA_MUX_DAP5] = "DAP5",
52 [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
53 [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
54 [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
55 [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
56 [TEGRA_MUX_GMI] = "GMI",
57 [TEGRA_MUX_GMI_INT] = "GMI_INT",
58 [TEGRA_MUX_HDMI] = "HDMI",
59 [TEGRA_MUX_I2C] = "I2C",
60 [TEGRA_MUX_I2C2] = "I2C2",
61 [TEGRA_MUX_I2C3] = "I2C3",
62 [TEGRA_MUX_IDE] = "IDE",
63 [TEGRA_MUX_IRDA] = "IRDA",
64 [TEGRA_MUX_KBC] = "KBC",
65 [TEGRA_MUX_MIO] = "MIO",
66 [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
67 [TEGRA_MUX_NAND] = "NAND",
68 [TEGRA_MUX_OSC] = "OSC",
69 [TEGRA_MUX_OWR] = "OWR",
70 [TEGRA_MUX_PCIE] = "PCIE",
71 [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
72 [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
73 [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
74 [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
75 [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
76 [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
77 [TEGRA_MUX_PWM] = "PWM",
78 [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
79 [TEGRA_MUX_PWR_ON] = "PWR_ON",
80 [TEGRA_MUX_RTCK] = "RTCK",
81 [TEGRA_MUX_SDIO1] = "SDIO1",
82 [TEGRA_MUX_SDIO2] = "SDIO2",
83 [TEGRA_MUX_SDIO3] = "SDIO3",
84 [TEGRA_MUX_SDIO4] = "SDIO4",
85 [TEGRA_MUX_SFLASH] = "SFLASH",
86 [TEGRA_MUX_SPDIF] = "SPDIF",
87 [TEGRA_MUX_SPI1] = "SPI1",
88 [TEGRA_MUX_SPI2] = "SPI2",
89 [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
90 [TEGRA_MUX_SPI3] = "SPI3",
91 [TEGRA_MUX_SPI4] = "SPI4",
92 [TEGRA_MUX_TRACE] = "TRACE",
93 [TEGRA_MUX_TWC] = "TWC",
94 [TEGRA_MUX_UARTA] = "UARTA",
95 [TEGRA_MUX_UARTB] = "UARTB",
96 [TEGRA_MUX_UARTC] = "UARTC",
97 [TEGRA_MUX_UARTD] = "UARTD",
98 [TEGRA_MUX_UARTE] = "UARTE",
99 [TEGRA_MUX_ULPI] = "ULPI",
100 [TEGRA_MUX_VI] = "VI",
101 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
102 [TEGRA_MUX_XIO] = "XIO",
103 [TEGRA_MUX_BLINK] = "BLINK",
104 [TEGRA_MUX_CEC] = "CEC",
105 [TEGRA_MUX_CLK12] = "CLK12",
106 [TEGRA_MUX_DAP] = "DAP",
107 [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
108 [TEGRA_MUX_DDR] = "DDR",
109 [TEGRA_MUX_DEV3] = "DEV3",
110 [TEGRA_MUX_DTV] = "DTV",
111 [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
112 [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
113 [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
114 [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
115 [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
116 [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
117 [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
118 [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
119 [TEGRA_MUX_HDA] = "HDA",
120 [TEGRA_MUX_HSI] = "HSI",
121 [TEGRA_MUX_I2C4] = "I2C4",
122 [TEGRA_MUX_I2C5] = "I2C5",
123 [TEGRA_MUX_I2CPWR] = "I2CPWR",
124 [TEGRA_MUX_I2S0] = "I2S0",
125 [TEGRA_MUX_I2S1] = "I2S1",
126 [TEGRA_MUX_I2S2] = "I2S2",
127 [TEGRA_MUX_I2S3] = "I2S3",
128 [TEGRA_MUX_I2S4] = "I2S4",
129 [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
130 [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
131 [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
132 [TEGRA_MUX_PWM0] = "PWM0",
133 [TEGRA_MUX_PWM1] = "PWM2",
134 [TEGRA_MUX_PWM2] = "PWM2",
135 [TEGRA_MUX_PWM3] = "PWM3",
136 [TEGRA_MUX_SATA] = "SATA",
137 [TEGRA_MUX_SPI5] = "SPI5",
138 [TEGRA_MUX_SPI6] = "SPI6",
139 [TEGRA_MUX_SYSCLK] = "SYSCLK",
140 [TEGRA_MUX_VGP1] = "VGP1",
141 [TEGRA_MUX_VGP2] = "VGP2",
142 [TEGRA_MUX_VGP3] = "VGP3",
143 [TEGRA_MUX_VGP4] = "VGP4",
144 [TEGRA_MUX_VGP5] = "VGP5",
145 [TEGRA_MUX_VGP6] = "VGP6",
146 [TEGRA_MUX_SAFE] = "<safe>",
147};
148
149static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
150 [TEGRA_DRIVE_DIV_8] = "DIV_8",
151 [TEGRA_DRIVE_DIV_4] = "DIV_4",
152 [TEGRA_DRIVE_DIV_2] = "DIV_2",
153 [TEGRA_DRIVE_DIV_1] = "DIV_1",
154};
155
156static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
157 [TEGRA_SLEW_FASTEST] = "FASTEST",
158 [TEGRA_SLEW_FAST] = "FAST",
159 [TEGRA_SLEW_SLOW] = "SLOW",
160 [TEGRA_SLEW_SLOWEST] = "SLOWEST",
161};
162
163static DEFINE_SPINLOCK(mux_lock);
164
165static const char *pingroup_name(int pg)
166{
167 if (pg < 0 || pg >= pingroup_max)
168 return "<UNKNOWN>";
169
170 return pingroups[pg].name;
171}
172
173static const char *func_name(enum tegra_mux_func func)
174{
175 if (func == TEGRA_MUX_RSVD1)
176 return "RSVD1";
177
178 if (func == TEGRA_MUX_RSVD2)
179 return "RSVD2";
180
181 if (func == TEGRA_MUX_RSVD3)
182 return "RSVD3";
183
184 if (func == TEGRA_MUX_RSVD4)
185 return "RSVD4";
186
187 if (func == TEGRA_MUX_NONE)
188 return "NONE";
189
190 if (func < 0 || func >= TEGRA_MAX_MUX)
191 return "<UNKNOWN>";
192
193 return tegra_mux_names[func];
194}
195
196
197static const char *tri_name(unsigned long val)
198{
199 return val ? "TRISTATE" : "NORMAL";
200}
201
202static const char *pupd_name(unsigned long val)
203{
204 switch (val) {
205 case 0:
206 return "NORMAL";
207
208 case 1:
209 return "PULL_DOWN";
210
211 case 2:
212 return "PULL_UP";
213
214 default:
215 return "RSVD";
216 }
217}
218
219static int nbanks;
220static void __iomem **regs;
221
222static inline u32 pg_readl(u32 bank, u32 reg)
223{
224 return readl(regs[bank] + reg);
225}
226
227static inline void pg_writel(u32 val, u32 bank, u32 reg)
228{
229 writel(val, regs[bank] + reg);
230}
231
232static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
233{
234 int mux = -1;
235 int i;
236 unsigned long reg;
237 unsigned long flags;
238 int pg = config->pingroup;
239 enum tegra_mux_func func = config->func;
240
241 if (pg < 0 || pg >= pingroup_max)
242 return -ERANGE;
243
244 if (pingroups[pg].mux_reg < 0)
245 return -EINVAL;
246
247 if (func < 0)
248 return -ERANGE;
249
250 if (func == TEGRA_MUX_SAFE)
251 func = pingroups[pg].func_safe;
252
253 if (func & TEGRA_MUX_RSVD) {
254 mux = func & 0x3;
255 } else {
256 for (i = 0; i < 4; i++) {
257 if (pingroups[pg].funcs[i] == func) {
258 mux = i;
259 break;
260 }
261 }
262 }
263
264 if (mux < 0)
265 return -EINVAL;
266
267 spin_lock_irqsave(&mux_lock, flags);
268
269 reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
270 reg &= ~(0x3 << pingroups[pg].mux_bit);
271 reg |= mux << pingroups[pg].mux_bit;
272 pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
273
274 spin_unlock_irqrestore(&mux_lock, flags);
275
276 return 0;
277}
278
279int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
280{
281 unsigned long reg;
282 unsigned long flags;
283
284 if (pg < 0 || pg >= pingroup_max)
285 return -ERANGE;
286
287 if (pingroups[pg].tri_reg < 0)
288 return -EINVAL;
289
290 spin_lock_irqsave(&mux_lock, flags);
291
292 reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
293 reg &= ~(0x1 << pingroups[pg].tri_bit);
294 if (tristate)
295 reg |= 1 << pingroups[pg].tri_bit;
296 pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
297
298 spin_unlock_irqrestore(&mux_lock, flags);
299
300 return 0;
301}
302
303int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
304{
305 unsigned long reg;
306 unsigned long flags;
307
308 if (pg < 0 || pg >= pingroup_max)
309 return -ERANGE;
310
311 if (pingroups[pg].pupd_reg < 0)
312 return -EINVAL;
313
314 if (pupd != TEGRA_PUPD_NORMAL &&
315 pupd != TEGRA_PUPD_PULL_DOWN &&
316 pupd != TEGRA_PUPD_PULL_UP)
317 return -EINVAL;
318
319
320 spin_lock_irqsave(&mux_lock, flags);
321
322 reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
323 reg &= ~(0x3 << pingroups[pg].pupd_bit);
324 reg |= pupd << pingroups[pg].pupd_bit;
325 pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
326
327 spin_unlock_irqrestore(&mux_lock, flags);
328
329 return 0;
330}
331
332static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
333{
334 int pingroup = config->pingroup;
335 enum tegra_mux_func func = config->func;
336 enum tegra_pullupdown pupd = config->pupd;
337 enum tegra_tristate tristate = config->tristate;
338 int err;
339
340 if (pingroups[pingroup].mux_reg >= 0) {
341 err = tegra_pinmux_set_func(config);
342 if (err < 0)
343 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
344 pingroup_name(pingroup), func_name(func), err);
345 }
346
347 if (pingroups[pingroup].pupd_reg >= 0) {
348 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
349 if (err < 0)
350 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
351 pingroup_name(pingroup), pupd_name(pupd), err);
352 }
353
354 if (pingroups[pingroup].tri_reg >= 0) {
355 err = tegra_pinmux_set_tristate(pingroup, tristate);
356 if (err < 0)
357 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
358 pingroup_name(pingroup), tri_name(func), err);
359 }
360}
361
362void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
363{
364 int i;
365
366 for (i = 0; i < len; i++)
367 tegra_pinmux_config_pingroup(&config[i]);
368}
369
370static const char *drive_pinmux_name(int pg)
371{
372 if (pg < 0 || pg >= drive_max)
373 return "<UNKNOWN>";
374
375 return drive_pingroups[pg].name;
376}
377
378static const char *enable_name(unsigned long val)
379{
380 return val ? "ENABLE" : "DISABLE";
381}
382
383static const char *drive_name(unsigned long val)
384{
385 if (val >= TEGRA_MAX_DRIVE)
386 return "<UNKNOWN>";
387
388 return tegra_drive_names[val];
389}
390
391static const char *slew_name(unsigned long val)
392{
393 if (val >= TEGRA_MAX_SLEW)
394 return "<UNKNOWN>";
395
396 return tegra_slew_names[val];
397}
398
399static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
400{
401 unsigned long flags;
402 u32 reg;
403 if (pg < 0 || pg >= drive_max)
404 return -ERANGE;
405
406 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
407 return -EINVAL;
408
409 spin_lock_irqsave(&mux_lock, flags);
410
411 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
412 if (hsm == TEGRA_HSM_ENABLE)
413 reg |= (1 << 2);
414 else
415 reg &= ~(1 << 2);
416 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
417
418 spin_unlock_irqrestore(&mux_lock, flags);
419
420 return 0;
421}
422
423static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
424{
425 unsigned long flags;
426 u32 reg;
427 if (pg < 0 || pg >= drive_max)
428 return -ERANGE;
429
430 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
431 return -EINVAL;
432
433 spin_lock_irqsave(&mux_lock, flags);
434
435 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
436 if (schmitt == TEGRA_SCHMITT_ENABLE)
437 reg |= (1 << 3);
438 else
439 reg &= ~(1 << 3);
440 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
441
442 spin_unlock_irqrestore(&mux_lock, flags);
443
444 return 0;
445}
446
447static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
448{
449 unsigned long flags;
450 u32 reg;
451 if (pg < 0 || pg >= drive_max)
452 return -ERANGE;
453
454 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
455 return -EINVAL;
456
457 spin_lock_irqsave(&mux_lock, flags);
458
459 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
460 reg &= ~(0x3 << 4);
461 reg |= drive << 4;
462 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
463
464 spin_unlock_irqrestore(&mux_lock, flags);
465
466 return 0;
467}
468
469static int tegra_drive_pinmux_set_pull_down(int pg,
470 enum tegra_pull_strength pull_down)
471{
472 unsigned long flags;
473 u32 reg;
474 if (pg < 0 || pg >= drive_max)
475 return -ERANGE;
476
477 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
478 return -EINVAL;
479
480 spin_lock_irqsave(&mux_lock, flags);
481
482 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
483 reg &= ~(0x1f << 12);
484 reg |= pull_down << 12;
485 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
486
487 spin_unlock_irqrestore(&mux_lock, flags);
488
489 return 0;
490}
491
492static int tegra_drive_pinmux_set_pull_up(int pg,
493 enum tegra_pull_strength pull_up)
494{
495 unsigned long flags;
496 u32 reg;
497 if (pg < 0 || pg >= drive_max)
498 return -ERANGE;
499
500 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
501 return -EINVAL;
502
503 spin_lock_irqsave(&mux_lock, flags);
504
505 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
506 reg &= ~(0x1f << 12);
507 reg |= pull_up << 12;
508 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
509
510 spin_unlock_irqrestore(&mux_lock, flags);
511
512 return 0;
513}
514
515static int tegra_drive_pinmux_set_slew_rising(int pg,
516 enum tegra_slew slew_rising)
517{
518 unsigned long flags;
519 u32 reg;
520 if (pg < 0 || pg >= drive_max)
521 return -ERANGE;
522
523 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
524 return -EINVAL;
525
526 spin_lock_irqsave(&mux_lock, flags);
527
528 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
529 reg &= ~(0x3 << 28);
530 reg |= slew_rising << 28;
531 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
532
533 spin_unlock_irqrestore(&mux_lock, flags);
534
535 return 0;
536}
537
538static int tegra_drive_pinmux_set_slew_falling(int pg,
539 enum tegra_slew slew_falling)
540{
541 unsigned long flags;
542 u32 reg;
543 if (pg < 0 || pg >= drive_max)
544 return -ERANGE;
545
546 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
547 return -EINVAL;
548
549 spin_lock_irqsave(&mux_lock, flags);
550
551 reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
552 reg &= ~(0x3 << 30);
553 reg |= slew_falling << 30;
554 pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
555
556 spin_unlock_irqrestore(&mux_lock, flags);
557
558 return 0;
559}
560
561static void tegra_drive_pinmux_config_pingroup(int pingroup,
562 enum tegra_hsm hsm,
563 enum tegra_schmitt schmitt,
564 enum tegra_drive drive,
565 enum tegra_pull_strength pull_down,
566 enum tegra_pull_strength pull_up,
567 enum tegra_slew slew_rising,
568 enum tegra_slew slew_falling)
569{
570 int err;
571
572 err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
573 if (err < 0)
574 pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
575 drive_pinmux_name(pingroup),
576 enable_name(hsm), err);
577
578 err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
579 if (err < 0)
580 pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
581 drive_pinmux_name(pingroup),
582 enable_name(schmitt), err);
583
584 err = tegra_drive_pinmux_set_drive(pingroup, drive);
585 if (err < 0)
586 pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
587 drive_pinmux_name(pingroup),
588 drive_name(drive), err);
589
590 err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
591 if (err < 0)
592 pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
593 drive_pinmux_name(pingroup),
594 pull_down, err);
595
596 err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
597 if (err < 0)
598 pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
599 drive_pinmux_name(pingroup),
600 pull_up, err);
601
602 err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
603 if (err < 0)
604 pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
605 drive_pinmux_name(pingroup),
606 slew_name(slew_rising), err);
607
608 err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
609 if (err < 0)
610 pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
611 drive_pinmux_name(pingroup),
612 slew_name(slew_falling), err);
613}
614
615void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
616 int len)
617{
618 int i;
619
620 for (i = 0; i < len; i++)
621 tegra_drive_pinmux_config_pingroup(config[i].pingroup,
622 config[i].hsm,
623 config[i].schmitt,
624 config[i].drive,
625 config[i].pull_down,
626 config[i].pull_up,
627 config[i].slew_rising,
628 config[i].slew_falling);
629}
630
631void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
632 int len)
633{
634 int i;
635 struct tegra_pingroup_config c;
636
637 for (i = 0; i < len; i++) {
638 int err;
639 c = config[i];
640 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
641 WARN_ON(1);
642 continue;
643 }
644 c.func = pingroups[c.pingroup].func_safe;
645 err = tegra_pinmux_set_func(&c);
646 if (err < 0)
647 pr_err("%s: tegra_pinmux_set_func returned %d setting "
648 "%s to %s\n", __func__, err,
649 pingroup_name(c.pingroup), func_name(c.func));
650 }
651}
652
653void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
654 int len)
655{
656 int i;
657
658 for (i = 0; i < len; i++) {
659 int err;
660 if (config[i].pingroup < 0 ||
661 config[i].pingroup >= pingroup_max) {
662 WARN_ON(1);
663 continue;
664 }
665 err = tegra_pinmux_set_func(&config[i]);
666 if (err < 0)
667 pr_err("%s: tegra_pinmux_set_func returned %d setting "
668 "%s to %s\n", __func__, err,
669 pingroup_name(config[i].pingroup),
670 func_name(config[i].func));
671 }
672}
673
674void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
675 int len, enum tegra_tristate tristate)
676{
677 int i;
678 int err;
679 int pingroup;
680
681 for (i = 0; i < len; i++) {
682 pingroup = config[i].pingroup;
683 if (pingroups[pingroup].tri_reg >= 0) {
684 err = tegra_pinmux_set_tristate(pingroup, tristate);
685 if (err < 0)
686 pr_err("pinmux: can't set pingroup %s tristate"
687 " to %s: %d\n", pingroup_name(pingroup),
688 tri_name(tristate), err);
689 }
690 }
691}
692
693void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
694 int len, enum tegra_pullupdown pupd)
695{
696 int i;
697 int err;
698 int pingroup;
699
700 for (i = 0; i < len; i++) {
701 pingroup = config[i].pingroup;
702 if (pingroups[pingroup].pupd_reg >= 0) {
703 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
704 if (err < 0)
705 pr_err("pinmux: can't set pingroup %s pullupdown"
706 " to %s: %d\n", pingroup_name(pingroup),
707 pupd_name(pupd), err);
708 }
709 }
710}
711
712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
713#ifdef CONFIG_ARCH_TEGRA_2x_SOC
714 { .compatible = "nvidia,tegra20-pinmux-disabled", tegra20_pinmux_init },
715#endif
716#ifdef CONFIG_ARCH_TEGRA_3x_SOC
717 { .compatible = "nvidia,tegra30-pinmux-disabled", tegra30_pinmux_init },
718#endif
719 { },
720};
721
722static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
723{
724 struct resource *res;
725 int i;
726 int config_bad = 0;
727 const struct of_device_id *match;
728
729 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
730
731 if (match)
732 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
733 &drive_pingroups, &drive_max);
734#ifdef CONFIG_ARCH_TEGRA_2x_SOC
735 else
736 /* no device tree available, so we must be on tegra20 */
737 tegra20_pinmux_init(&pingroups, &pingroup_max,
738 &drive_pingroups, &drive_max);
739#else
740 pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
741#endif
742
743 for (i = 0; ; i++) {
744 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
745 if (!res)
746 break;
747 }
748 nbanks = i;
749
750 for (i = 0; i < pingroup_max; i++) {
751 if (pingroups[i].tri_bank >= nbanks) {
752 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
753 config_bad = 1;
754 }
755
756 if (pingroups[i].mux_bank >= nbanks) {
757 dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
758 config_bad = 1;
759 }
760
761 if (pingroups[i].pupd_bank >= nbanks) {
762 dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
763 config_bad = 1;
764 }
765 }
766
767 for (i = 0; i < drive_max; i++) {
768 if (drive_pingroups[i].reg_bank >= nbanks) {
769 dev_err(&pdev->dev,
770 "drive pingroup %d: bad reg_bank\n", i);
771 config_bad = 1;
772 }
773 }
774
775 if (config_bad)
776 return -ENODEV;
777
778 regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
779 if (!regs) {
780 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
781 return -ENODEV;
782 }
783
784 for (i = 0; i < nbanks; i++) {
785 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
786 if (!res) {
787 dev_err(&pdev->dev, "Missing MEM resource\n");
788 return -ENODEV;
789 }
790
791 if (!devm_request_mem_region(&pdev->dev, res->start,
792 resource_size(res),
793 dev_name(&pdev->dev))) {
794 dev_err(&pdev->dev,
795 "Couldn't request MEM resource %d\n", i);
796 return -ENODEV;
797 }
798
799 regs[i] = devm_ioremap(&pdev->dev, res->start,
800 resource_size(res));
801 if (!regs) {
802 dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
803 return -ENODEV;
804 }
805 }
806
807 return 0;
808}
809
810static struct platform_driver tegra_pinmux_driver = {
811 .driver = {
812 .name = "tegra-pinmux-disabled",
813 .owner = THIS_MODULE,
814 .of_match_table = tegra_pinmux_of_match,
815 },
816 .probe = tegra_pinmux_probe,
817};
818
819static int __init tegra_pinmux_init(void)
820{
821 return platform_driver_register(&tegra_pinmux_driver);
822}
823postcore_initcall(tegra_pinmux_init);
824
825#ifdef CONFIG_DEBUG_FS
826
827#include <linux/debugfs.h>
828#include <linux/seq_file.h>
829
830static void dbg_pad_field(struct seq_file *s, int len)
831{
832 seq_putc(s, ',');
833
834 while (len-- > -1)
835 seq_putc(s, ' ');
836}
837
838static int dbg_pinmux_show(struct seq_file *s, void *unused)
839{
840 int i;
841 int len;
842
843 for (i = 0; i < pingroup_max; i++) {
844 unsigned long reg;
845 unsigned long tri;
846 unsigned long mux;
847 unsigned long pupd;
848
849 seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
850 len = strlen(pingroups[i].name);
851 dbg_pad_field(s, 5 - len);
852
853 if (pingroups[i].mux_reg < 0) {
854 seq_printf(s, "TEGRA_MUX_NONE");
855 len = strlen("NONE");
856 } else {
857 reg = pg_readl(pingroups[i].mux_bank,
858 pingroups[i].mux_reg);
859 mux = (reg >> pingroups[i].mux_bit) & 0x3;
860 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
861 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
862 len = 5;
863 } else {
864 seq_printf(s, "TEGRA_MUX_%s",
865 tegra_mux_names[pingroups[i].funcs[mux]]);
866 len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
867 }
868 }
869 dbg_pad_field(s, 13-len);
870
871 if (pingroups[i].pupd_reg < 0) {
872 seq_printf(s, "TEGRA_PUPD_NORMAL");
873 len = strlen("NORMAL");
874 } else {
875 reg = pg_readl(pingroups[i].pupd_bank,
876 pingroups[i].pupd_reg);
877 pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
878 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
879 len = strlen(pupd_name(pupd));
880 }
881 dbg_pad_field(s, 9 - len);
882
883 if (pingroups[i].tri_reg < 0) {
884 seq_printf(s, "TEGRA_TRI_NORMAL");
885 } else {
886 reg = pg_readl(pingroups[i].tri_bank,
887 pingroups[i].tri_reg);
888 tri = (reg >> pingroups[i].tri_bit) & 0x1;
889
890 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
891 }
892 seq_printf(s, "},\n");
893 }
894 return 0;
895}
896
897static int dbg_pinmux_open(struct inode *inode, struct file *file)
898{
899 return single_open(file, dbg_pinmux_show, &inode->i_private);
900}
901
902static const struct file_operations debug_fops = {
903 .open = dbg_pinmux_open,
904 .read = seq_read,
905 .llseek = seq_lseek,
906 .release = single_release,
907};
908
909static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
910{
911 int i;
912 int len;
913
914 for (i = 0; i < drive_max; i++) {
915 u32 reg;
916
917 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
918 drive_pingroups[i].name);
919 len = strlen(drive_pingroups[i].name);
920 dbg_pad_field(s, 7 - len);
921
922
923 reg = pg_readl(drive_pingroups[i].reg_bank,
924 drive_pingroups[i].reg);
925 if (HSM_EN(reg)) {
926 seq_printf(s, "TEGRA_HSM_ENABLE");
927 len = 16;
928 } else {
929 seq_printf(s, "TEGRA_HSM_DISABLE");
930 len = 17;
931 }
932 dbg_pad_field(s, 17 - len);
933
934 if (SCHMT_EN(reg)) {
935 seq_printf(s, "TEGRA_SCHMITT_ENABLE");
936 len = 21;
937 } else {
938 seq_printf(s, "TEGRA_SCHMITT_DISABLE");
939 len = 22;
940 }
941 dbg_pad_field(s, 22 - len);
942
943 seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
944 len = strlen(drive_name(LPMD(reg)));
945 dbg_pad_field(s, 5 - len);
946
947 seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
948 len = DRVDN(reg) < 10 ? 1 : 2;
949 dbg_pad_field(s, 2 - len);
950
951 seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
952 len = DRVUP(reg) < 10 ? 1 : 2;
953 dbg_pad_field(s, 2 - len);
954
955 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
956 len = strlen(slew_name(SLWR(reg)));
957 dbg_pad_field(s, 7 - len);
958
959 seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
960
961 seq_printf(s, "},\n");
962 }
963 return 0;
964}
965
966static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
967{
968 return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
969}
970
971static const struct file_operations debug_drive_fops = {
972 .open = dbg_drive_pinmux_open,
973 .read = seq_read,
974 .llseek = seq_lseek,
975 .release = single_release,
976};
977
978static int __init tegra_pinmux_debuginit(void)
979{
980 (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
981 NULL, NULL, &debug_fops);
982 (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
983 NULL, NULL, &debug_drive_fops);
984 return 0;
985}
986late_initcall(tegra_pinmux_debuginit);
987#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 03:29:43 -0400