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authorThierry Reding <thierry.reding@avionic-design.de>2012-11-15 16:07:58 -0500
committerStephen Warren <swarren@nvidia.com>2012-11-15 16:46:28 -0500
commit2acc1fc28244465f1c83690ce84516f4b0080456 (patch)
treed43db70af2d4e7ff5b241c3af961b919688d619b /arch/arm/mach-tegra
parent5f10778370e15ca6e74db75d7bbe888870e49e3f (diff)
ARM: tegra: Add AUXDATA for Tegra30 host1x
Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index cd3033874161..6497d1236b08 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -57,6 +57,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
57 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL), 57 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
58 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL), 58 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
59 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL), 59 OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
60 OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
61 OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
62 OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
63 OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
64 OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
65 OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
60 {} 66 {}
61}; 67};
62 68
@@ -82,6 +88,9 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
82 { "sbc4", "pll_p", 100000000, false}, 88 { "sbc4", "pll_p", 100000000, false},
83 { "sbc5", "pll_p", 100000000, false}, 89 { "sbc5", "pll_p", 100000000, false},
84 { "sbc6", "pll_p", 100000000, false}, 90 { "sbc6", "pll_p", 100000000, false},
91 { "host1x", "pll_c", 150000000, false},
92 { "disp1", "pll_p", 600000000, false},
93 { "disp2", "pll_p", 600000000, false},
85 { NULL, NULL, 0, 0}, 94 { NULL, NULL, 0, 0},
86}; 95};
87 96