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authorStephen Warren <swarren@nvidia.com>2011-08-08 17:01:05 -0400
committerOlof Johansson <olof@lixom.net>2011-08-09 15:08:07 -0400
commit11b3adb45da636a839bd2b7c300c616e0e2c38d6 (patch)
tree2a7d73f9fadc3875237aa8796b59da5fff4aa475 /arch/arm/mach-tegra
parent24810cb53c0c66eb2922117c6a53c64c3f7a07a6 (diff)
ARM: Tegra: Force PORT_TEGRA as the UART type
8250.c recently gained an explicit PORT_TEGRA port type. Specifically request this in all Tegra boards' UART platform data. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/board-harmony.c3
-rw-r--r--arch/arm/mach-tegra/board-paz00.c6
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c3
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c3
4 files changed, 10 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index f528a5a192a6..987dab527e8c 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -49,7 +49,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
49 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 49 .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
50 .mapbase = TEGRA_UARTD_BASE, 50 .mapbase = TEGRA_UARTD_BASE,
51 .irq = INT_UARTD, 51 .irq = INT_UARTD,
52 .flags = UPF_BOOT_AUTOCONF, 52 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
53 .type = PORT_TEGRA,
53 .iotype = UPIO_MEM, 54 .iotype = UPIO_MEM,
54 .regshift = 2, 55 .regshift = 2,
55 .uartclk = 216000000, 56 .uartclk = 216000000,
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 51d847f7fca9..7630c239e7a9 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -50,7 +50,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
50 .membase = IO_ADDRESS(TEGRA_UARTA_BASE), 50 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
51 .mapbase = TEGRA_UARTA_BASE, 51 .mapbase = TEGRA_UARTA_BASE,
52 .irq = INT_UARTA, 52 .irq = INT_UARTA,
53 .flags = UPF_BOOT_AUTOCONF, 53 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
54 .type = PORT_TEGRA,
54 .iotype = UPIO_MEM, 55 .iotype = UPIO_MEM,
55 .regshift = 2, 56 .regshift = 2,
56 .uartclk = 216000000, 57 .uartclk = 216000000,
@@ -59,7 +60,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
59 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 60 .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
60 .mapbase = TEGRA_UARTD_BASE, 61 .mapbase = TEGRA_UARTD_BASE,
61 .irq = INT_UARTD, 62 .irq = INT_UARTD,
62 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
64 .type = PORT_TEGRA,
63 .iotype = UPIO_MEM, 65 .iotype = UPIO_MEM,
64 .regshift = 2, 66 .regshift = 2,
65 .uartclk = 216000000, 67 .uartclk = 216000000,
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 237a94a1f44a..25446df00006 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -44,7 +44,8 @@
44static struct plat_serial8250_port debug_uart_platform_data[] = { 44static struct plat_serial8250_port debug_uart_platform_data[] = {
45 { 45 {
46 /* Memory and IRQ filled in before registration */ 46 /* Memory and IRQ filled in before registration */
47 .flags = UPF_BOOT_AUTOCONF, 47 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
48 .type = PORT_TEGRA,
48 .iotype = UPIO_MEM, 49 .iotype = UPIO_MEM,
49 .regshift = 2, 50 .regshift = 2,
50 .uartclk = 216000000, 51 .uartclk = 216000000,
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 89a6d2adc1de..91875b975563 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -46,7 +46,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
46 .membase = IO_ADDRESS(TEGRA_UARTA_BASE), 46 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
47 .mapbase = TEGRA_UARTA_BASE, 47 .mapbase = TEGRA_UARTA_BASE,
48 .irq = INT_UARTA, 48 .irq = INT_UARTA,
49 .flags = UPF_BOOT_AUTOCONF, 49 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
50 .type = PORT_TEGRA,
50 .iotype = UPIO_MEM, 51 .iotype = UPIO_MEM,
51 .regshift = 2, 52 .regshift = 2,
52 .uartclk = 216000000, 53 .uartclk = 216000000,