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authorThierry Reding <thierry.reding@avionic-design.de>2011-12-16 15:01:57 -0500
committerStephen Warren <swarren@nvidia.com>2012-07-02 17:01:34 -0400
commit094479915618c526a1409dd6704bcb4ff2c5c1c2 (patch)
tree7e1f8e656bb77519cd8f6b2004a6e01b8be3703b /arch/arm/mach-tegra/tegra2_clocks.c
parentbb1dccfc63f7a007c6347c75ba597d866749d9d2 (diff)
ARM: tegra: Provide clock for only one PWM controller
A subsequent patch will add a generic PWM API driver for the Tegra PWFM controller, supporting all four PWM devices with a single PWM chip. The device will be named tegra-pwm and only one clock needs to be provided. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 2016ba095816..a703844b2061 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2180,7 +2180,7 @@ static struct clk tegra_list_clks[] = {
2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), 2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2183 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM), 2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
@@ -2279,10 +2279,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), 2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), 2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2282 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2283 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2284 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2285 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2286 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), 2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2287 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), 2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2288 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), 2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),