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authorPeter De Schrijver <pdeschrijver@nvidia.com>2011-12-14 10:03:24 -0500
committerOlof Johansson <olof@lixom.net>2011-12-17 23:15:33 -0500
commit241682c8e0df98e710776ea09a7748938ca2578f (patch)
tree9d84534502bf0a4ccb7089a8735dcc733f43eb80 /arch/arm/mach-tegra/include/mach/pinmux.h
parent31e37a183e79e4ba6b6640d65279fa1e8394d24a (diff)
arm/tegra: pinmux tables and definitions for tegra30
Define the pinmuxing and pindrive tables for tegra30. The pinmux table defines the available functions for each pinmux group. The pindrive table defines the default pullup or pulldowns for each group. Derived from code by Scott Williams (scwilliams@nvidia.com) Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/pinmux.h')
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h53
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index 988c6c5ec9ec..055f1792c8ff 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -24,6 +24,7 @@ enum tegra_mux_func {
24 TEGRA_MUX_RSVD2 = 0x8001, 24 TEGRA_MUX_RSVD2 = 0x8001,
25 TEGRA_MUX_RSVD3 = 0x8002, 25 TEGRA_MUX_RSVD3 = 0x8002,
26 TEGRA_MUX_RSVD4 = 0x8003, 26 TEGRA_MUX_RSVD4 = 0x8003,
27 TEGRA_MUX_INVALID = 0x4000,
27 TEGRA_MUX_NONE = -1, 28 TEGRA_MUX_NONE = -1,
28 TEGRA_MUX_AHB_CLK, 29 TEGRA_MUX_AHB_CLK,
29 TEGRA_MUX_APB_CLK, 30 TEGRA_MUX_APB_CLK,
@@ -85,6 +86,49 @@ enum tegra_mux_func {
85 TEGRA_MUX_VI, 86 TEGRA_MUX_VI,
86 TEGRA_MUX_VI_SENSOR_CLK, 87 TEGRA_MUX_VI_SENSOR_CLK,
87 TEGRA_MUX_XIO, 88 TEGRA_MUX_XIO,
89 TEGRA_MUX_BLINK,
90 TEGRA_MUX_CEC,
91 TEGRA_MUX_CLK12,
92 TEGRA_MUX_DAP,
93 TEGRA_MUX_DAPSDMMC2,
94 TEGRA_MUX_DDR,
95 TEGRA_MUX_DEV3,
96 TEGRA_MUX_DTV,
97 TEGRA_MUX_VI_ALT1,
98 TEGRA_MUX_VI_ALT2,
99 TEGRA_MUX_VI_ALT3,
100 TEGRA_MUX_EMC_DLL,
101 TEGRA_MUX_EXTPERIPH1,
102 TEGRA_MUX_EXTPERIPH2,
103 TEGRA_MUX_EXTPERIPH3,
104 TEGRA_MUX_GMI_ALT,
105 TEGRA_MUX_HDA,
106 TEGRA_MUX_HSI,
107 TEGRA_MUX_I2C4,
108 TEGRA_MUX_I2C5,
109 TEGRA_MUX_I2CPWR,
110 TEGRA_MUX_I2S0,
111 TEGRA_MUX_I2S1,
112 TEGRA_MUX_I2S2,
113 TEGRA_MUX_I2S3,
114 TEGRA_MUX_I2S4,
115 TEGRA_MUX_NAND_ALT,
116 TEGRA_MUX_POPSDIO4,
117 TEGRA_MUX_POPSDMMC4,
118 TEGRA_MUX_PWM0,
119 TEGRA_MUX_PWM1,
120 TEGRA_MUX_PWM2,
121 TEGRA_MUX_PWM3,
122 TEGRA_MUX_SATA,
123 TEGRA_MUX_SPI5,
124 TEGRA_MUX_SPI6,
125 TEGRA_MUX_SYSCLK,
126 TEGRA_MUX_VGP1,
127 TEGRA_MUX_VGP2,
128 TEGRA_MUX_VGP3,
129 TEGRA_MUX_VGP4,
130 TEGRA_MUX_VGP5,
131 TEGRA_MUX_VGP6,
88 TEGRA_MUX_SAFE, 132 TEGRA_MUX_SAFE,
89 TEGRA_MAX_MUX, 133 TEGRA_MAX_MUX,
90}; 134};
@@ -115,6 +159,12 @@ enum tegra_vddio {
115 TEGRA_VDDIO_SYS, 159 TEGRA_VDDIO_SYS,
116 TEGRA_VDDIO_AUDIO, 160 TEGRA_VDDIO_AUDIO,
117 TEGRA_VDDIO_SD, 161 TEGRA_VDDIO_SD,
162 TEGRA_VDDIO_CAM,
163 TEGRA_VDDIO_GMI,
164 TEGRA_VDDIO_PEXCTL,
165 TEGRA_VDDIO_SDMMC1,
166 TEGRA_VDDIO_SDMMC3,
167 TEGRA_VDDIO_SDMMC4,
118}; 168};
119 169
120struct tegra_pingroup_config { 170struct tegra_pingroup_config {
@@ -230,6 +280,9 @@ typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
230void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max, 280void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
231 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max); 281 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
232 282
283void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
284 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
285
233int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate); 286int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
234int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd); 287int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
235 288