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authorJoseph Lo <josephl@nvidia.com>2012-10-29 06:25:57 -0400
committerStephen Warren <swarren@nvidia.com>2012-11-05 13:36:23 -0500
commitd065ab7189f368bbe9505865d63a0ebc470c409e (patch)
treea70c97633e6542f61f1fccbdccbe757ea2c46f51 /arch/arm/mach-tegra/common.c
parent5ab134ad09988ca8225e759a052df7a1bbd26145 (diff)
ARM: tegra: common: using OF api for L2 cache init
Moving L2 cache init to DT support. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r--arch/arm/mach-tegra/common.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 3f55a3615413..6c04a18a88d6 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -113,20 +113,17 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
113#endif 113#endif
114 114
115 115
116static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) 116static void __init tegra_init_cache(void)
117{ 117{
118#ifdef CONFIG_CACHE_L2X0 118#ifdef CONFIG_CACHE_L2X0
119 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; 119 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
120 u32 aux_ctrl, cache_type; 120 u32 aux_ctrl, cache_type;
121 121
122 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
123 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
124
125 cache_type = readl(p + L2X0_CACHE_TYPE); 122 cache_type = readl(p + L2X0_CACHE_TYPE);
126 aux_ctrl = (cache_type & 0x700) << (17-8); 123 aux_ctrl = (cache_type & 0x700) << (17-8);
127 aux_ctrl |= 0x6C000001; 124 aux_ctrl |= 0x6C000001;
128 125
129 l2x0_init(p, aux_ctrl, 0x8200c3fe); 126 l2x0_of_init(aux_ctrl, 0x8200c3fe);
130#endif 127#endif
131 128
132} 129}
@@ -138,7 +135,7 @@ void __init tegra20_init_early(void)
138 tegra_init_fuse(); 135 tegra_init_fuse();
139 tegra2_init_clocks(); 136 tegra2_init_clocks();
140 tegra_clk_init_from_table(tegra20_clk_init_table); 137 tegra_clk_init_from_table(tegra20_clk_init_table);
141 tegra_init_cache(0x331, 0x441); 138 tegra_init_cache();
142 tegra_pmc_init(); 139 tegra_pmc_init();
143 tegra_powergate_init(); 140 tegra_powergate_init();
144 tegra20_hotplug_init(); 141 tegra20_hotplug_init();
@@ -151,7 +148,7 @@ void __init tegra30_init_early(void)
151 tegra_init_fuse(); 148 tegra_init_fuse();
152 tegra30_init_clocks(); 149 tegra30_init_clocks();
153 tegra_clk_init_from_table(tegra30_clk_init_table); 150 tegra_clk_init_from_table(tegra30_clk_init_table);
154 tegra_init_cache(0x441, 0x551); 151 tegra_init_cache();
155 tegra_pmc_init(); 152 tegra_pmc_init();
156 tegra_powergate_init(); 153 tegra_powergate_init();
157 tegra30_hotplug_init(); 154 tegra30_hotplug_init();