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authorArnd Bergmann <arnd@arndb.de>2012-05-14 09:33:42 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 09:33:42 -0400
commitd2819f80d465672b09c2f4cb52303b7f951c4d0f (patch)
treeaa0262703e86b97ad1460c722e78d7233e24e3bb /arch/arm/mach-spear6xx/spear6xx.c
parent5df33a62c4a028d6fc7f2dcc159827d09b7334b8 (diff)
parent366695ff706669d40459174b1cbb78fca42f4e06 (diff)
Merge branch 'spear/pinctrl' into spear/clock
Conflicts: arch/arm/mach-spear3xx/Makefile arch/arm/mach-spear3xx/clock.c arch/arm/mach-spear3xx/include/mach/generic.h arch/arm/mach-spear6xx/clock.c arch/arm/plat-spear/Makefile drivers/pinctrl/core.c This resolves some annoying merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-spear6xx/spear6xx.c')
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c372
1 files changed, 371 insertions, 1 deletions
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 771e19e3c43c..e9031ec6d6e0 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,15 +13,377 @@
13 * warranty of any kind, whether express or implied. 13 * warranty of any kind, whether express or implied.
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h> 18#include <linux/of_address.h>
18#include <linux/of_irq.h> 19#include <linux/of_irq.h>
19#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <asm/hardware/pl080.h>
20#include <asm/hardware/vic.h> 22#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <plat/pl080.h>
22#include <mach/generic.h> 25#include <mach/generic.h>
23#include <mach/hardware.h> 26#include <mach/hardware.h>
24 27
28/* dmac device registration */
29static struct pl08x_channel_data spear600_dma_info[] = {
30 {
31 .bus_id = "ssp1_rx",
32 .min_signal = 0,
33 .max_signal = 0,
34 .muxval = 0,
35 .cctl = 0,
36 .periph_buses = PL08X_AHB1,
37 }, {
38 .bus_id = "ssp1_tx",
39 .min_signal = 1,
40 .max_signal = 1,
41 .muxval = 0,
42 .cctl = 0,
43 .periph_buses = PL08X_AHB1,
44 }, {
45 .bus_id = "uart0_rx",
46 .min_signal = 2,
47 .max_signal = 2,
48 .muxval = 0,
49 .cctl = 0,
50 .periph_buses = PL08X_AHB1,
51 }, {
52 .bus_id = "uart0_tx",
53 .min_signal = 3,
54 .max_signal = 3,
55 .muxval = 0,
56 .cctl = 0,
57 .periph_buses = PL08X_AHB1,
58 }, {
59 .bus_id = "uart1_rx",
60 .min_signal = 4,
61 .max_signal = 4,
62 .muxval = 0,
63 .cctl = 0,
64 .periph_buses = PL08X_AHB1,
65 }, {
66 .bus_id = "uart1_tx",
67 .min_signal = 5,
68 .max_signal = 5,
69 .muxval = 0,
70 .cctl = 0,
71 .periph_buses = PL08X_AHB1,
72 }, {
73 .bus_id = "ssp2_rx",
74 .min_signal = 6,
75 .max_signal = 6,
76 .muxval = 0,
77 .cctl = 0,
78 .periph_buses = PL08X_AHB2,
79 }, {
80 .bus_id = "ssp2_tx",
81 .min_signal = 7,
82 .max_signal = 7,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB2,
86 }, {
87 .bus_id = "ssp0_rx",
88 .min_signal = 8,
89 .max_signal = 8,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_tx",
95 .min_signal = 9,
96 .max_signal = 9,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "i2c_rx",
102 .min_signal = 10,
103 .max_signal = 10,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_tx",
109 .min_signal = 11,
110 .max_signal = 11,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "irda",
116 .min_signal = 12,
117 .max_signal = 12,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "adc",
123 .min_signal = 13,
124 .max_signal = 13,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB2,
128 }, {
129 .bus_id = "to_jpeg",
130 .min_signal = 14,
131 .max_signal = 14,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "from_jpeg",
137 .min_signal = 15,
138 .max_signal = 15,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "ras0_rx",
144 .min_signal = 0,
145 .max_signal = 0,
146 .muxval = 1,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_tx",
151 .min_signal = 1,
152 .max_signal = 1,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras1_rx",
158 .min_signal = 2,
159 .max_signal = 2,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_tx",
165 .min_signal = 3,
166 .max_signal = 3,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras2_rx",
172 .min_signal = 4,
173 .max_signal = 4,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_tx",
179 .min_signal = 5,
180 .max_signal = 5,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras3_rx",
186 .min_signal = 6,
187 .max_signal = 6,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_tx",
193 .min_signal = 7,
194 .max_signal = 7,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras4_rx",
200 .min_signal = 8,
201 .max_signal = 8,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_tx",
207 .min_signal = 9,
208 .max_signal = 9,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras5_rx",
214 .min_signal = 10,
215 .max_signal = 10,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_tx",
221 .min_signal = 11,
222 .max_signal = 11,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras6_rx",
228 .min_signal = 12,
229 .max_signal = 12,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_tx",
235 .min_signal = 13,
236 .max_signal = 13,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras7_rx",
242 .min_signal = 14,
243 .max_signal = 14,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_tx",
249 .min_signal = 15,
250 .max_signal = 15,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ext0_rx",
256 .min_signal = 0,
257 .max_signal = 0,
258 .muxval = 2,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB2,
261 }, {
262 .bus_id = "ext0_tx",
263 .min_signal = 1,
264 .max_signal = 1,
265 .muxval = 2,
266 .cctl = 0,
267 .periph_buses = PL08X_AHB2,
268 }, {
269 .bus_id = "ext1_rx",
270 .min_signal = 2,
271 .max_signal = 2,
272 .muxval = 2,
273 .cctl = 0,
274 .periph_buses = PL08X_AHB2,
275 }, {
276 .bus_id = "ext1_tx",
277 .min_signal = 3,
278 .max_signal = 3,
279 .muxval = 2,
280 .cctl = 0,
281 .periph_buses = PL08X_AHB2,
282 }, {
283 .bus_id = "ext2_rx",
284 .min_signal = 4,
285 .max_signal = 4,
286 .muxval = 2,
287 .cctl = 0,
288 .periph_buses = PL08X_AHB2,
289 }, {
290 .bus_id = "ext2_tx",
291 .min_signal = 5,
292 .max_signal = 5,
293 .muxval = 2,
294 .cctl = 0,
295 .periph_buses = PL08X_AHB2,
296 }, {
297 .bus_id = "ext3_rx",
298 .min_signal = 6,
299 .max_signal = 6,
300 .muxval = 2,
301 .cctl = 0,
302 .periph_buses = PL08X_AHB2,
303 }, {
304 .bus_id = "ext3_tx",
305 .min_signal = 7,
306 .max_signal = 7,
307 .muxval = 2,
308 .cctl = 0,
309 .periph_buses = PL08X_AHB2,
310 }, {
311 .bus_id = "ext4_rx",
312 .min_signal = 8,
313 .max_signal = 8,
314 .muxval = 2,
315 .cctl = 0,
316 .periph_buses = PL08X_AHB2,
317 }, {
318 .bus_id = "ext4_tx",
319 .min_signal = 9,
320 .max_signal = 9,
321 .muxval = 2,
322 .cctl = 0,
323 .periph_buses = PL08X_AHB2,
324 }, {
325 .bus_id = "ext5_rx",
326 .min_signal = 10,
327 .max_signal = 10,
328 .muxval = 2,
329 .cctl = 0,
330 .periph_buses = PL08X_AHB2,
331 }, {
332 .bus_id = "ext5_tx",
333 .min_signal = 11,
334 .max_signal = 11,
335 .muxval = 2,
336 .cctl = 0,
337 .periph_buses = PL08X_AHB2,
338 }, {
339 .bus_id = "ext6_rx",
340 .min_signal = 12,
341 .max_signal = 12,
342 .muxval = 2,
343 .cctl = 0,
344 .periph_buses = PL08X_AHB2,
345 }, {
346 .bus_id = "ext6_tx",
347 .min_signal = 13,
348 .max_signal = 13,
349 .muxval = 2,
350 .cctl = 0,
351 .periph_buses = PL08X_AHB2,
352 }, {
353 .bus_id = "ext7_rx",
354 .min_signal = 14,
355 .max_signal = 14,
356 .muxval = 2,
357 .cctl = 0,
358 .periph_buses = PL08X_AHB2,
359 }, {
360 .bus_id = "ext7_tx",
361 .min_signal = 15,
362 .max_signal = 15,
363 .muxval = 2,
364 .cctl = 0,
365 .periph_buses = PL08X_AHB2,
366 },
367};
368
369struct pl08x_platform_data pl080_plat_data = {
370 .memcpy_channel = {
371 .bus_id = "memcpy",
372 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
373 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
374 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
375 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
376 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
377 PL080_CONTROL_PROT_SYS),
378 },
379 .lli_buses = PL08X_AHB1,
380 .mem_buses = PL08X_AHB1,
381 .get_signal = pl080_get_signal,
382 .put_signal = pl080_put_signal,
383 .slave_channels = spear600_dma_info,
384 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
385};
386
25/* Following will create static virtual/physical mappings */ 387/* Following will create static virtual/physical mappings */
26static struct map_desc spear6xx_io_desc[] __initdata = { 388static struct map_desc spear6xx_io_desc[] __initdata = {
27 { 389 {
@@ -91,9 +453,17 @@ struct sys_timer spear6xx_timer = {
91 .init = spear6xx_timer_init, 453 .init = spear6xx_timer_init,
92}; 454};
93 455
456/* Add auxdata to pass platform data */
457struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
458 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
459 &pl080_plat_data),
460 {}
461};
462
94static void __init spear600_dt_init(void) 463static void __init spear600_dt_init(void)
95{ 464{
96 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 465 of_platform_populate(NULL, of_default_bus_match_table,
466 spear6xx_auxdata_lookup, NULL);
97} 467}
98 468
99static const char *spear600_dt_board_compat[] = { 469static const char *spear600_dt_board_compat[] = {
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