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authorShiraz Hashim <shiraz.hashim@st.com>2011-03-06 23:57:08 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-09 04:50:04 -0500
commit981a95d37126cdf09e1dba3884305c2e25375bfb (patch)
tree280cad24a89b16dd91b392b50a6f7c141183c243 /arch/arm/mach-spear6xx/include
parent8fc4ef451eebc72d10c6987b59ec3316da62f02b (diff)
ARM: 6794/1: SPEAr: Append UL to device address macros.
Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-spear6xx/include')
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h91
1 files changed, 46 insertions, 45 deletions
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index c9bba39dddce..7fd621532def 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,69 +14,70 @@
14#ifndef __MACH_SPEAR6XX_H 14#ifndef __MACH_SPEAR6XX_H
15#define __MACH_SPEAR6XX_H 15#define __MACH_SPEAR6XX_H
16 16
17#include <asm/memory.h>
17#include <mach/spear600.h> 18#include <mach/spear600.h>
18 19
19#define SPEAR6XX_ML_SDRAM_BASE 0x00000000 20#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
20/* ICM1 - Low speed connection */ 21/* ICM1 - Low speed connection */
21#define SPEAR6XX_ICM1_BASE 0xD0000000 22#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
22 23
23#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 24#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
24#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) 25#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
25 26
26#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 27#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
27#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 28#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
28#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 29#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
29#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 30#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
30#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 31#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
31#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 32#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
32#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 33#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
33#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 34#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
34#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 35#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
35 36
36/* ICM2 - Application Subsystem */ 37/* ICM2 - Application Subsystem */
37#define SPEAR6XX_ICM2_BASE 0xD8000000 38#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
38#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 39#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
39#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 40#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
40#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 41#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
41#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 42#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
42#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 43#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
43 44
44/* ML-1, 2 - Multi Layer CPU Subsystem */ 45/* ML-1, 2 - Multi Layer CPU Subsystem */
45#define SPEAR6XX_ML_CPU_BASE 0xF0000000 46#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
46#define SPEAR6XX_CPU_TMR_BASE 0xF0000000 47#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
47#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 48#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
48#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 49#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
49#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) 50#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
50#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 51#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
51#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) 52#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
52 53
53/* ICM3 - Basic Subsystem */ 54/* ICM3 - Basic Subsystem */
54#define SPEAR6XX_ICM3_BASE 0xF8000000 55#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
55#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000 56#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
56#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000 57#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
57#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 58#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
58#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 59#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
59#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 60#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
60#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 61#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
61#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 62#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
62#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 63#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
63#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 64#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
64#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 65#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
65#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) 66#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
66#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 67#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
67#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) 68#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
68 69
69/* ICM4 - High Speed Connection */ 70/* ICM4 - High Speed Connection */
70#define SPEAR6XX_ICM4_BASE 0xE0000000 71#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
71#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 72#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
72#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 73#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
73#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000 74#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
74#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000 75#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
75#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 76#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
76#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 77#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
77#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 78#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
78#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 79#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
79#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000 80#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
80 81
81/* Debug uart for linux, will be used for debug and uncompress messages */ 82/* Debug uart for linux, will be used for debug and uncompress messages */
82#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE 83#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE