diff options
author | Viresh Kumar <viresh.kumar@st.com> | 2012-04-03 07:57:10 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-04-22 16:49:26 -0400 |
commit | 8076dd1b7deeaeb5c6f0b58be95c0a13164e1a99 (patch) | |
tree | 96e3741dec72d84de577b23c9e821a27bf371f63 /arch/arm/mach-spear3xx | |
parent | 52130b6033c580c27d968f64cd73209c9609e4e0 (diff) |
SPEAr: Remove existing padmux support for SPEAr
We must use pinctrl framework instead of defining per SoC pinmux drivers. This
patch removes existing padmux support present for SPEAr platform.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Diffstat (limited to 'arch/arm/mach-spear3xx')
-rw-r--r-- | arch/arm/mach-spear3xx/include/mach/generic.h | 128 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear300.c | 389 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear310.c | 161 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear320.c | 403 | ||||
-rw-r--r-- | arch/arm/mach-spear3xx/spear3xx.c | 425 |
5 files changed, 3 insertions, 1503 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index a7569584cbe8..9603bf4d5119 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/amba/bus.h> | 20 | #include <linux/amba/bus.h> |
21 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
22 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
23 | #include <plat/padmux.h> | ||
24 | 23 | ||
25 | /* spear3xx declarations */ | 24 | /* spear3xx declarations */ |
26 | /* | 25 | /* |
@@ -43,147 +42,20 @@ void __init spear3xx_dt_init_irq(void); | |||
43 | 42 | ||
44 | void spear_restart(char, const char *); | 43 | void spear_restart(char, const char *); |
45 | 44 | ||
46 | /* pad mux declarations */ | ||
47 | #define PMX_FIRDA_MASK (1 << 14) | ||
48 | #define PMX_I2C_MASK (1 << 13) | ||
49 | #define PMX_SSP_CS_MASK (1 << 12) | ||
50 | #define PMX_SSP_MASK (1 << 11) | ||
51 | #define PMX_MII_MASK (1 << 10) | ||
52 | #define PMX_GPIO_PIN0_MASK (1 << 9) | ||
53 | #define PMX_GPIO_PIN1_MASK (1 << 8) | ||
54 | #define PMX_GPIO_PIN2_MASK (1 << 7) | ||
55 | #define PMX_GPIO_PIN3_MASK (1 << 6) | ||
56 | #define PMX_GPIO_PIN4_MASK (1 << 5) | ||
57 | #define PMX_GPIO_PIN5_MASK (1 << 4) | ||
58 | #define PMX_UART0_MODEM_MASK (1 << 3) | ||
59 | #define PMX_UART0_MASK (1 << 2) | ||
60 | #define PMX_TIMER_3_4_MASK (1 << 1) | ||
61 | #define PMX_TIMER_1_2_MASK (1 << 0) | ||
62 | |||
63 | /* pad mux devices */ | ||
64 | extern struct pmx_dev spear3xx_pmx_firda; | ||
65 | extern struct pmx_dev spear3xx_pmx_i2c; | ||
66 | extern struct pmx_dev spear3xx_pmx_ssp_cs; | ||
67 | extern struct pmx_dev spear3xx_pmx_ssp; | ||
68 | extern struct pmx_dev spear3xx_pmx_mii; | ||
69 | extern struct pmx_dev spear3xx_pmx_gpio_pin0; | ||
70 | extern struct pmx_dev spear3xx_pmx_gpio_pin1; | ||
71 | extern struct pmx_dev spear3xx_pmx_gpio_pin2; | ||
72 | extern struct pmx_dev spear3xx_pmx_gpio_pin3; | ||
73 | extern struct pmx_dev spear3xx_pmx_gpio_pin4; | ||
74 | extern struct pmx_dev spear3xx_pmx_gpio_pin5; | ||
75 | extern struct pmx_dev spear3xx_pmx_uart0_modem; | ||
76 | extern struct pmx_dev spear3xx_pmx_uart0; | ||
77 | extern struct pmx_dev spear3xx_pmx_timer_3_4; | ||
78 | extern struct pmx_dev spear3xx_pmx_timer_1_2; | ||
79 | |||
80 | #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) | ||
81 | /* padmux plgpio devices */ | ||
82 | extern struct pmx_dev spear3xx_pmx_plgpio_0_1; | ||
83 | extern struct pmx_dev spear3xx_pmx_plgpio_2_3; | ||
84 | extern struct pmx_dev spear3xx_pmx_plgpio_4_5; | ||
85 | extern struct pmx_dev spear3xx_pmx_plgpio_6_9; | ||
86 | extern struct pmx_dev spear3xx_pmx_plgpio_10_27; | ||
87 | extern struct pmx_dev spear3xx_pmx_plgpio_28; | ||
88 | extern struct pmx_dev spear3xx_pmx_plgpio_29; | ||
89 | extern struct pmx_dev spear3xx_pmx_plgpio_30; | ||
90 | extern struct pmx_dev spear3xx_pmx_plgpio_31; | ||
91 | extern struct pmx_dev spear3xx_pmx_plgpio_32; | ||
92 | extern struct pmx_dev spear3xx_pmx_plgpio_33; | ||
93 | extern struct pmx_dev spear3xx_pmx_plgpio_34_36; | ||
94 | extern struct pmx_dev spear3xx_pmx_plgpio_37_42; | ||
95 | extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48; | ||
96 | extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; | ||
97 | #endif | ||
98 | |||
99 | /* spear300 declarations */ | 45 | /* spear300 declarations */ |
100 | #ifdef CONFIG_MACH_SPEAR300 | 46 | #ifdef CONFIG_MACH_SPEAR300 |
101 | /* pad mux modes */ | ||
102 | extern struct pmx_mode spear300_nand_mode; | ||
103 | extern struct pmx_mode spear300_nor_mode; | ||
104 | extern struct pmx_mode spear300_photo_frame_mode; | ||
105 | extern struct pmx_mode spear300_lend_ip_phone_mode; | ||
106 | extern struct pmx_mode spear300_hend_ip_phone_mode; | ||
107 | extern struct pmx_mode spear300_lend_wifi_phone_mode; | ||
108 | extern struct pmx_mode spear300_hend_wifi_phone_mode; | ||
109 | extern struct pmx_mode spear300_ata_pabx_wi2s_mode; | ||
110 | extern struct pmx_mode spear300_ata_pabx_i2s_mode; | ||
111 | extern struct pmx_mode spear300_caml_lcdw_mode; | ||
112 | extern struct pmx_mode spear300_camu_lcd_mode; | ||
113 | extern struct pmx_mode spear300_camu_wlcd_mode; | ||
114 | extern struct pmx_mode spear300_caml_lcd_mode; | ||
115 | |||
116 | /* pad mux devices */ | ||
117 | extern struct pmx_dev spear300_pmx_fsmc_2_chips; | ||
118 | extern struct pmx_dev spear300_pmx_fsmc_4_chips; | ||
119 | extern struct pmx_dev spear300_pmx_keyboard; | ||
120 | extern struct pmx_dev spear300_pmx_clcd; | ||
121 | extern struct pmx_dev spear300_pmx_telecom_gpio; | ||
122 | extern struct pmx_dev spear300_pmx_telecom_tdm; | ||
123 | extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk; | ||
124 | extern struct pmx_dev spear300_pmx_telecom_camera; | ||
125 | extern struct pmx_dev spear300_pmx_telecom_dac; | ||
126 | extern struct pmx_dev spear300_pmx_telecom_i2s; | ||
127 | extern struct pmx_dev spear300_pmx_telecom_boot_pins; | ||
128 | extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; | ||
129 | extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; | ||
130 | extern struct pmx_dev spear300_pmx_gpio1; | ||
131 | |||
132 | /* Add spear300 machine declarations here */ | ||
133 | void __init spear300_clk_init(void); | 47 | void __init spear300_clk_init(void); |
134 | 48 | ||
135 | #endif /* CONFIG_MACH_SPEAR300 */ | 49 | #endif /* CONFIG_MACH_SPEAR300 */ |
136 | 50 | ||
137 | /* spear310 declarations */ | 51 | /* spear310 declarations */ |
138 | #ifdef CONFIG_MACH_SPEAR310 | 52 | #ifdef CONFIG_MACH_SPEAR310 |
139 | /* pad mux devices */ | ||
140 | extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; | ||
141 | extern struct pmx_dev spear310_pmx_emi_cs_2_3; | ||
142 | extern struct pmx_dev spear310_pmx_uart1; | ||
143 | extern struct pmx_dev spear310_pmx_uart2; | ||
144 | extern struct pmx_dev spear310_pmx_uart3_4_5; | ||
145 | extern struct pmx_dev spear310_pmx_fsmc; | ||
146 | extern struct pmx_dev spear310_pmx_rs485_0_1; | ||
147 | extern struct pmx_dev spear310_pmx_tdm0; | ||
148 | |||
149 | /* Add spear310 machine declarations here */ | ||
150 | void __init spear310_clk_init(void); | 53 | void __init spear310_clk_init(void); |
151 | 54 | ||
152 | #endif /* CONFIG_MACH_SPEAR310 */ | 55 | #endif /* CONFIG_MACH_SPEAR310 */ |
153 | 56 | ||
154 | /* spear320 declarations */ | 57 | /* spear320 declarations */ |
155 | #ifdef CONFIG_MACH_SPEAR320 | 58 | #ifdef CONFIG_MACH_SPEAR320 |
156 | /* pad mux modes */ | ||
157 | extern struct pmx_mode spear320_auto_net_smii_mode; | ||
158 | extern struct pmx_mode spear320_auto_net_mii_mode; | ||
159 | extern struct pmx_mode spear320_auto_exp_mode; | ||
160 | extern struct pmx_mode spear320_small_printers_mode; | ||
161 | |||
162 | /* pad mux devices */ | ||
163 | extern struct pmx_dev spear320_pmx_clcd; | ||
164 | extern struct pmx_dev spear320_pmx_emi; | ||
165 | extern struct pmx_dev spear320_pmx_fsmc; | ||
166 | extern struct pmx_dev spear320_pmx_spp; | ||
167 | extern struct pmx_dev spear320_pmx_sdhci; | ||
168 | extern struct pmx_dev spear320_pmx_i2s; | ||
169 | extern struct pmx_dev spear320_pmx_uart1; | ||
170 | extern struct pmx_dev spear320_pmx_uart1_modem; | ||
171 | extern struct pmx_dev spear320_pmx_uart2; | ||
172 | extern struct pmx_dev spear320_pmx_touchscreen; | ||
173 | extern struct pmx_dev spear320_pmx_can; | ||
174 | extern struct pmx_dev spear320_pmx_sdhci_led; | ||
175 | extern struct pmx_dev spear320_pmx_pwm0; | ||
176 | extern struct pmx_dev spear320_pmx_pwm1; | ||
177 | extern struct pmx_dev spear320_pmx_pwm2; | ||
178 | extern struct pmx_dev spear320_pmx_pwm3; | ||
179 | extern struct pmx_dev spear320_pmx_ssp1; | ||
180 | extern struct pmx_dev spear320_pmx_ssp2; | ||
181 | extern struct pmx_dev spear320_pmx_mii1; | ||
182 | extern struct pmx_dev spear320_pmx_smii0; | ||
183 | extern struct pmx_dev spear320_pmx_smii1; | ||
184 | extern struct pmx_dev spear320_pmx_i2c1; | ||
185 | |||
186 | /* Add spear320 machine declarations here */ | ||
187 | void __init spear320_clk_init(void); | 59 | void __init spear320_clk_init(void); |
188 | 60 | ||
189 | #endif /* CONFIG_MACH_SPEAR320 */ | 61 | #endif /* CONFIG_MACH_SPEAR320 */ |
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index f46fc2692ab6..2db0bd14e481 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c | |||
@@ -21,357 +21,6 @@ | |||
21 | #include <mach/generic.h> | 21 | #include <mach/generic.h> |
22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
23 | 23 | ||
24 | /* pad multiplexing support */ | ||
25 | /* muxing registers */ | ||
26 | #define PAD_MUX_CONFIG_REG 0x00 | ||
27 | #define MODE_CONFIG_REG 0x04 | ||
28 | |||
29 | /* modes */ | ||
30 | #define NAND_MODE (1 << 0) | ||
31 | #define NOR_MODE (1 << 1) | ||
32 | #define PHOTO_FRAME_MODE (1 << 2) | ||
33 | #define LEND_IP_PHONE_MODE (1 << 3) | ||
34 | #define HEND_IP_PHONE_MODE (1 << 4) | ||
35 | #define LEND_WIFI_PHONE_MODE (1 << 5) | ||
36 | #define HEND_WIFI_PHONE_MODE (1 << 6) | ||
37 | #define ATA_PABX_WI2S_MODE (1 << 7) | ||
38 | #define ATA_PABX_I2S_MODE (1 << 8) | ||
39 | #define CAML_LCDW_MODE (1 << 9) | ||
40 | #define CAMU_LCD_MODE (1 << 10) | ||
41 | #define CAMU_WLCD_MODE (1 << 11) | ||
42 | #define CAML_LCD_MODE (1 << 12) | ||
43 | #define ALL_MODES 0x1FFF | ||
44 | |||
45 | struct pmx_mode spear300_nand_mode = { | ||
46 | .id = NAND_MODE, | ||
47 | .name = "nand mode", | ||
48 | .mask = 0x00, | ||
49 | }; | ||
50 | |||
51 | struct pmx_mode spear300_nor_mode = { | ||
52 | .id = NOR_MODE, | ||
53 | .name = "nor mode", | ||
54 | .mask = 0x01, | ||
55 | }; | ||
56 | |||
57 | struct pmx_mode spear300_photo_frame_mode = { | ||
58 | .id = PHOTO_FRAME_MODE, | ||
59 | .name = "photo frame mode", | ||
60 | .mask = 0x02, | ||
61 | }; | ||
62 | |||
63 | struct pmx_mode spear300_lend_ip_phone_mode = { | ||
64 | .id = LEND_IP_PHONE_MODE, | ||
65 | .name = "lend ip phone mode", | ||
66 | .mask = 0x03, | ||
67 | }; | ||
68 | |||
69 | struct pmx_mode spear300_hend_ip_phone_mode = { | ||
70 | .id = HEND_IP_PHONE_MODE, | ||
71 | .name = "hend ip phone mode", | ||
72 | .mask = 0x04, | ||
73 | }; | ||
74 | |||
75 | struct pmx_mode spear300_lend_wifi_phone_mode = { | ||
76 | .id = LEND_WIFI_PHONE_MODE, | ||
77 | .name = "lend wifi phone mode", | ||
78 | .mask = 0x05, | ||
79 | }; | ||
80 | |||
81 | struct pmx_mode spear300_hend_wifi_phone_mode = { | ||
82 | .id = HEND_WIFI_PHONE_MODE, | ||
83 | .name = "hend wifi phone mode", | ||
84 | .mask = 0x06, | ||
85 | }; | ||
86 | |||
87 | struct pmx_mode spear300_ata_pabx_wi2s_mode = { | ||
88 | .id = ATA_PABX_WI2S_MODE, | ||
89 | .name = "ata pabx wi2s mode", | ||
90 | .mask = 0x07, | ||
91 | }; | ||
92 | |||
93 | struct pmx_mode spear300_ata_pabx_i2s_mode = { | ||
94 | .id = ATA_PABX_I2S_MODE, | ||
95 | .name = "ata pabx i2s mode", | ||
96 | .mask = 0x08, | ||
97 | }; | ||
98 | |||
99 | struct pmx_mode spear300_caml_lcdw_mode = { | ||
100 | .id = CAML_LCDW_MODE, | ||
101 | .name = "caml lcdw mode", | ||
102 | .mask = 0x0C, | ||
103 | }; | ||
104 | |||
105 | struct pmx_mode spear300_camu_lcd_mode = { | ||
106 | .id = CAMU_LCD_MODE, | ||
107 | .name = "camu lcd mode", | ||
108 | .mask = 0x0D, | ||
109 | }; | ||
110 | |||
111 | struct pmx_mode spear300_camu_wlcd_mode = { | ||
112 | .id = CAMU_WLCD_MODE, | ||
113 | .name = "camu wlcd mode", | ||
114 | .mask = 0x0E, | ||
115 | }; | ||
116 | |||
117 | struct pmx_mode spear300_caml_lcd_mode = { | ||
118 | .id = CAML_LCD_MODE, | ||
119 | .name = "caml lcd mode", | ||
120 | .mask = 0x0F, | ||
121 | }; | ||
122 | |||
123 | /* devices */ | ||
124 | static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { | ||
125 | { | ||
126 | .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | | ||
127 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, | ||
128 | .mask = PMX_FIRDA_MASK, | ||
129 | }, | ||
130 | }; | ||
131 | |||
132 | struct pmx_dev spear300_pmx_fsmc_2_chips = { | ||
133 | .name = "fsmc_2_chips", | ||
134 | .modes = pmx_fsmc_2_chips_modes, | ||
135 | .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), | ||
136 | .enb_on_reset = 1, | ||
137 | }; | ||
138 | |||
139 | static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { | ||
140 | { | ||
141 | .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | | ||
142 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, | ||
143 | .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, | ||
144 | }, | ||
145 | }; | ||
146 | |||
147 | struct pmx_dev spear300_pmx_fsmc_4_chips = { | ||
148 | .name = "fsmc_4_chips", | ||
149 | .modes = pmx_fsmc_4_chips_modes, | ||
150 | .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), | ||
151 | .enb_on_reset = 1, | ||
152 | }; | ||
153 | |||
154 | static struct pmx_dev_mode pmx_keyboard_modes[] = { | ||
155 | { | ||
156 | .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | | ||
157 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | | ||
158 | CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | | ||
159 | CAML_LCD_MODE, | ||
160 | .mask = 0x0, | ||
161 | }, | ||
162 | }; | ||
163 | |||
164 | struct pmx_dev spear300_pmx_keyboard = { | ||
165 | .name = "keyboard", | ||
166 | .modes = pmx_keyboard_modes, | ||
167 | .mode_count = ARRAY_SIZE(pmx_keyboard_modes), | ||
168 | .enb_on_reset = 1, | ||
169 | }; | ||
170 | |||
171 | static struct pmx_dev_mode pmx_clcd_modes[] = { | ||
172 | { | ||
173 | .ids = PHOTO_FRAME_MODE, | ||
174 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , | ||
175 | }, { | ||
176 | .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | | ||
177 | CAMU_LCD_MODE | CAML_LCD_MODE, | ||
178 | .mask = PMX_TIMER_3_4_MASK, | ||
179 | }, | ||
180 | }; | ||
181 | |||
182 | struct pmx_dev spear300_pmx_clcd = { | ||
183 | .name = "clcd", | ||
184 | .modes = pmx_clcd_modes, | ||
185 | .mode_count = ARRAY_SIZE(pmx_clcd_modes), | ||
186 | .enb_on_reset = 1, | ||
187 | }; | ||
188 | |||
189 | static struct pmx_dev_mode pmx_telecom_gpio_modes[] = { | ||
190 | { | ||
191 | .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, | ||
192 | .mask = PMX_MII_MASK, | ||
193 | }, { | ||
194 | .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE, | ||
195 | .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, | ||
196 | }, { | ||
197 | .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE, | ||
198 | .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK, | ||
199 | }, { | ||
200 | .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE, | ||
201 | .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK, | ||
202 | }, { | ||
203 | .ids = ATA_PABX_WI2S_MODE, | ||
204 | .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | ||
205 | | PMX_UART0_MODEM_MASK, | ||
206 | }, | ||
207 | }; | ||
208 | |||
209 | struct pmx_dev spear300_pmx_telecom_gpio = { | ||
210 | .name = "telecom_gpio", | ||
211 | .modes = pmx_telecom_gpio_modes, | ||
212 | .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), | ||
213 | .enb_on_reset = 1, | ||
214 | }; | ||
215 | |||
216 | static struct pmx_dev_mode pmx_telecom_tdm_modes[] = { | ||
217 | { | ||
218 | .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | | ||
219 | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | ||
220 | | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE | ||
221 | | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | ||
222 | | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
223 | .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, | ||
224 | }, | ||
225 | }; | ||
226 | |||
227 | struct pmx_dev spear300_pmx_telecom_tdm = { | ||
228 | .name = "telecom_tdm", | ||
229 | .modes = pmx_telecom_tdm_modes, | ||
230 | .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), | ||
231 | .enb_on_reset = 1, | ||
232 | }; | ||
233 | |||
234 | static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { | ||
235 | { | ||
236 | .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | | ||
237 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | ||
238 | | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | | ||
239 | CAML_LCDW_MODE | CAML_LCD_MODE, | ||
240 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, | ||
241 | }, | ||
242 | }; | ||
243 | |||
244 | struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = { | ||
245 | .name = "telecom_spi_cs_i2c_clk", | ||
246 | .modes = pmx_telecom_spi_cs_i2c_clk_modes, | ||
247 | .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), | ||
248 | .enb_on_reset = 1, | ||
249 | }; | ||
250 | |||
251 | static struct pmx_dev_mode pmx_telecom_camera_modes[] = { | ||
252 | { | ||
253 | .ids = CAML_LCDW_MODE | CAML_LCD_MODE, | ||
254 | .mask = PMX_MII_MASK, | ||
255 | }, { | ||
256 | .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE, | ||
257 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK, | ||
258 | }, | ||
259 | }; | ||
260 | |||
261 | struct pmx_dev spear300_pmx_telecom_camera = { | ||
262 | .name = "telecom_camera", | ||
263 | .modes = pmx_telecom_camera_modes, | ||
264 | .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), | ||
265 | .enb_on_reset = 1, | ||
266 | }; | ||
267 | |||
268 | static struct pmx_dev_mode pmx_telecom_dac_modes[] = { | ||
269 | { | ||
270 | .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | ||
271 | | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
272 | .mask = PMX_TIMER_1_2_MASK, | ||
273 | }, | ||
274 | }; | ||
275 | |||
276 | struct pmx_dev spear300_pmx_telecom_dac = { | ||
277 | .name = "telecom_dac", | ||
278 | .modes = pmx_telecom_dac_modes, | ||
279 | .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), | ||
280 | .enb_on_reset = 1, | ||
281 | }; | ||
282 | |||
283 | static struct pmx_dev_mode pmx_telecom_i2s_modes[] = { | ||
284 | { | ||
285 | .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | ||
286 | | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | | ||
287 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | ||
288 | | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
289 | .mask = PMX_UART0_MODEM_MASK, | ||
290 | }, | ||
291 | }; | ||
292 | |||
293 | struct pmx_dev spear300_pmx_telecom_i2s = { | ||
294 | .name = "telecom_i2s", | ||
295 | .modes = pmx_telecom_i2s_modes, | ||
296 | .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), | ||
297 | .enb_on_reset = 1, | ||
298 | }; | ||
299 | |||
300 | static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { | ||
301 | { | ||
302 | .ids = NAND_MODE | NOR_MODE, | ||
303 | .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | | ||
304 | PMX_TIMER_3_4_MASK, | ||
305 | }, | ||
306 | }; | ||
307 | |||
308 | struct pmx_dev spear300_pmx_telecom_boot_pins = { | ||
309 | .name = "telecom_boot_pins", | ||
310 | .modes = pmx_telecom_boot_pins_modes, | ||
311 | .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), | ||
312 | .enb_on_reset = 1, | ||
313 | }; | ||
314 | |||
315 | static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { | ||
316 | { | ||
317 | .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | | ||
318 | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | | ||
319 | HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | | ||
320 | CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE | | ||
321 | ATA_PABX_I2S_MODE, | ||
322 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | | ||
323 | PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | | ||
324 | PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, | ||
325 | }, | ||
326 | }; | ||
327 | |||
328 | struct pmx_dev spear300_pmx_telecom_sdhci_4bit = { | ||
329 | .name = "telecom_sdhci_4bit", | ||
330 | .modes = pmx_telecom_sdhci_4bit_modes, | ||
331 | .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), | ||
332 | .enb_on_reset = 1, | ||
333 | }; | ||
334 | |||
335 | static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { | ||
336 | { | ||
337 | .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | | ||
338 | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | | ||
339 | HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | | ||
340 | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
341 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | | ||
342 | PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | | ||
343 | PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, | ||
344 | }, | ||
345 | }; | ||
346 | |||
347 | struct pmx_dev spear300_pmx_telecom_sdhci_8bit = { | ||
348 | .name = "telecom_sdhci_8bit", | ||
349 | .modes = pmx_telecom_sdhci_8bit_modes, | ||
350 | .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), | ||
351 | .enb_on_reset = 1, | ||
352 | }; | ||
353 | |||
354 | static struct pmx_dev_mode pmx_gpio1_modes[] = { | ||
355 | { | ||
356 | .ids = PHOTO_FRAME_MODE, | ||
357 | .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | | ||
358 | PMX_TIMER_3_4_MASK, | ||
359 | }, | ||
360 | }; | ||
361 | |||
362 | struct pmx_dev spear300_pmx_gpio1 = { | ||
363 | .name = "arm gpio1", | ||
364 | .modes = pmx_gpio1_modes, | ||
365 | .mode_count = ARRAY_SIZE(pmx_gpio1_modes), | ||
366 | .enb_on_reset = 1, | ||
367 | }; | ||
368 | |||
369 | /* pmx driver structure */ | ||
370 | static struct pmx_driver pmx_driver = { | ||
371 | .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, | ||
372 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, | ||
373 | }; | ||
374 | |||
375 | /* spear3xx shared irq */ | 24 | /* spear3xx shared irq */ |
376 | static struct shirq_dev_config shirq_ras1_config[] = { | 25 | static struct shirq_dev_config shirq_ras1_config[] = { |
377 | { | 26 | { |
@@ -425,22 +74,6 @@ static struct spear_shirq shirq_ras1 = { | |||
425 | }, | 74 | }, |
426 | }; | 75 | }; |
427 | 76 | ||
428 | /* padmux devices to enable */ | ||
429 | static struct pmx_dev *spear300_evb_pmx_devs[] = { | ||
430 | /* spear3xx specific devices */ | ||
431 | &spear3xx_pmx_i2c, | ||
432 | &spear3xx_pmx_ssp_cs, | ||
433 | &spear3xx_pmx_ssp, | ||
434 | &spear3xx_pmx_mii, | ||
435 | &spear3xx_pmx_uart0, | ||
436 | |||
437 | /* spear300 specific devices */ | ||
438 | &spear300_pmx_fsmc_2_chips, | ||
439 | &spear300_pmx_clcd, | ||
440 | &spear300_pmx_telecom_sdhci_4bit, | ||
441 | &spear300_pmx_gpio1, | ||
442 | }; | ||
443 | |||
444 | /* DMAC platform data's slave info */ | 77 | /* DMAC platform data's slave info */ |
445 | struct pl08x_channel_data spear300_dma_info[] = { | 78 | struct pl08x_channel_data spear300_dma_info[] = { |
446 | { | 79 | { |
@@ -639,7 +272,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { | |||
639 | 272 | ||
640 | static void __init spear300_dt_init(void) | 273 | static void __init spear300_dt_init(void) |
641 | { | 274 | { |
642 | int ret = -EINVAL; | 275 | int ret; |
643 | 276 | ||
644 | pl080_plat_data.slave_channels = spear300_dma_info; | 277 | pl080_plat_data.slave_channels = spear300_dma_info; |
645 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); | 278 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); |
@@ -654,26 +287,6 @@ static void __init spear300_dt_init(void) | |||
654 | if (ret) | 287 | if (ret) |
655 | pr_err("Error registering Shared IRQ\n"); | 288 | pr_err("Error registering Shared IRQ\n"); |
656 | } | 289 | } |
657 | |||
658 | if (of_machine_is_compatible("st,spear300-evb")) { | ||
659 | /* pmx initialization */ | ||
660 | pmx_driver.mode = &spear300_photo_frame_mode; | ||
661 | pmx_driver.devs = spear300_evb_pmx_devs; | ||
662 | pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs); | ||
663 | |||
664 | pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); | ||
665 | if (pmx_driver.base) { | ||
666 | ret = pmx_register(&pmx_driver); | ||
667 | if (ret) | ||
668 | pr_err("padmux: registration failed. err no: %d\n", | ||
669 | ret); | ||
670 | /* Free Mapping, device selection already done */ | ||
671 | iounmap(pmx_driver.base); | ||
672 | } | ||
673 | |||
674 | if (ret) | ||
675 | pr_err("Initialization Failed"); | ||
676 | } | ||
677 | } | 290 | } |
678 | 291 | ||
679 | static const char * const spear300_dt_board_compat[] = { | 292 | static const char * const spear300_dt_board_compat[] = { |
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index 063e7da0438a..aec07c951205 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c | |||
@@ -22,128 +22,6 @@ | |||
22 | #include <mach/generic.h> | 22 | #include <mach/generic.h> |
23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
24 | 24 | ||
25 | /* pad multiplexing support */ | ||
26 | /* muxing registers */ | ||
27 | #define PAD_MUX_CONFIG_REG 0x08 | ||
28 | |||
29 | /* devices */ | ||
30 | static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { | ||
31 | { | ||
32 | .ids = 0x00, | ||
33 | .mask = PMX_TIMER_3_4_MASK, | ||
34 | }, | ||
35 | }; | ||
36 | |||
37 | struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { | ||
38 | .name = "emi_cs_0_1_4_5", | ||
39 | .modes = pmx_emi_cs_0_1_4_5_modes, | ||
40 | .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), | ||
41 | .enb_on_reset = 1, | ||
42 | }; | ||
43 | |||
44 | static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { | ||
45 | { | ||
46 | .ids = 0x00, | ||
47 | .mask = PMX_TIMER_1_2_MASK, | ||
48 | }, | ||
49 | }; | ||
50 | |||
51 | struct pmx_dev spear310_pmx_emi_cs_2_3 = { | ||
52 | .name = "emi_cs_2_3", | ||
53 | .modes = pmx_emi_cs_2_3_modes, | ||
54 | .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), | ||
55 | .enb_on_reset = 1, | ||
56 | }; | ||
57 | |||
58 | static struct pmx_dev_mode pmx_uart1_modes[] = { | ||
59 | { | ||
60 | .ids = 0x00, | ||
61 | .mask = PMX_FIRDA_MASK, | ||
62 | }, | ||
63 | }; | ||
64 | |||
65 | struct pmx_dev spear310_pmx_uart1 = { | ||
66 | .name = "uart1", | ||
67 | .modes = pmx_uart1_modes, | ||
68 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), | ||
69 | .enb_on_reset = 1, | ||
70 | }; | ||
71 | |||
72 | static struct pmx_dev_mode pmx_uart2_modes[] = { | ||
73 | { | ||
74 | .ids = 0x00, | ||
75 | .mask = PMX_TIMER_1_2_MASK, | ||
76 | }, | ||
77 | }; | ||
78 | |||
79 | struct pmx_dev spear310_pmx_uart2 = { | ||
80 | .name = "uart2", | ||
81 | .modes = pmx_uart2_modes, | ||
82 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), | ||
83 | .enb_on_reset = 1, | ||
84 | }; | ||
85 | |||
86 | static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { | ||
87 | { | ||
88 | .ids = 0x00, | ||
89 | .mask = PMX_UART0_MODEM_MASK, | ||
90 | }, | ||
91 | }; | ||
92 | |||
93 | struct pmx_dev spear310_pmx_uart3_4_5 = { | ||
94 | .name = "uart3_4_5", | ||
95 | .modes = pmx_uart3_4_5_modes, | ||
96 | .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), | ||
97 | .enb_on_reset = 1, | ||
98 | }; | ||
99 | |||
100 | static struct pmx_dev_mode pmx_fsmc_modes[] = { | ||
101 | { | ||
102 | .ids = 0x00, | ||
103 | .mask = PMX_SSP_CS_MASK, | ||
104 | }, | ||
105 | }; | ||
106 | |||
107 | struct pmx_dev spear310_pmx_fsmc = { | ||
108 | .name = "fsmc", | ||
109 | .modes = pmx_fsmc_modes, | ||
110 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), | ||
111 | .enb_on_reset = 1, | ||
112 | }; | ||
113 | |||
114 | static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { | ||
115 | { | ||
116 | .ids = 0x00, | ||
117 | .mask = PMX_MII_MASK, | ||
118 | }, | ||
119 | }; | ||
120 | |||
121 | struct pmx_dev spear310_pmx_rs485_0_1 = { | ||
122 | .name = "rs485_0_1", | ||
123 | .modes = pmx_rs485_0_1_modes, | ||
124 | .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), | ||
125 | .enb_on_reset = 1, | ||
126 | }; | ||
127 | |||
128 | static struct pmx_dev_mode pmx_tdm0_modes[] = { | ||
129 | { | ||
130 | .ids = 0x00, | ||
131 | .mask = PMX_MII_MASK, | ||
132 | }, | ||
133 | }; | ||
134 | |||
135 | struct pmx_dev spear310_pmx_tdm0 = { | ||
136 | .name = "tdm0", | ||
137 | .modes = pmx_tdm0_modes, | ||
138 | .mode_count = ARRAY_SIZE(pmx_tdm0_modes), | ||
139 | .enb_on_reset = 1, | ||
140 | }; | ||
141 | |||
142 | /* pmx driver structure */ | ||
143 | static struct pmx_driver pmx_driver = { | ||
144 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, | ||
145 | }; | ||
146 | |||
147 | /* spear3xx shared irq */ | 25 | /* spear3xx shared irq */ |
148 | static struct shirq_dev_config shirq_ras1_config[] = { | 26 | static struct shirq_dev_config shirq_ras1_config[] = { |
149 | { | 27 | { |
@@ -260,30 +138,6 @@ static struct spear_shirq shirq_intrcomm_ras = { | |||
260 | }, | 138 | }, |
261 | }; | 139 | }; |
262 | 140 | ||
263 | /* padmux devices to enable */ | ||
264 | static struct pmx_dev *spear310_evb_pmx_devs[] = { | ||
265 | /* spear3xx specific devices */ | ||
266 | &spear3xx_pmx_i2c, | ||
267 | &spear3xx_pmx_ssp, | ||
268 | &spear3xx_pmx_gpio_pin0, | ||
269 | &spear3xx_pmx_gpio_pin1, | ||
270 | &spear3xx_pmx_gpio_pin2, | ||
271 | &spear3xx_pmx_gpio_pin3, | ||
272 | &spear3xx_pmx_gpio_pin4, | ||
273 | &spear3xx_pmx_gpio_pin5, | ||
274 | &spear3xx_pmx_uart0, | ||
275 | |||
276 | /* spear310 specific devices */ | ||
277 | &spear310_pmx_emi_cs_0_1_4_5, | ||
278 | &spear310_pmx_emi_cs_2_3, | ||
279 | &spear310_pmx_uart1, | ||
280 | &spear310_pmx_uart2, | ||
281 | &spear310_pmx_uart3_4_5, | ||
282 | &spear310_pmx_fsmc, | ||
283 | &spear310_pmx_rs485_0_1, | ||
284 | &spear310_pmx_tdm0, | ||
285 | }; | ||
286 | |||
287 | /* DMAC platform data's slave info */ | 141 | /* DMAC platform data's slave info */ |
288 | struct pl08x_channel_data spear310_dma_info[] = { | 142 | struct pl08x_channel_data spear310_dma_info[] = { |
289 | { | 143 | { |
@@ -518,7 +372,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { | |||
518 | static void __init spear310_dt_init(void) | 372 | static void __init spear310_dt_init(void) |
519 | { | 373 | { |
520 | void __iomem *base; | 374 | void __iomem *base; |
521 | int ret = 0; | 375 | int ret; |
522 | 376 | ||
523 | pl080_plat_data.slave_channels = spear310_dma_info; | 377 | pl080_plat_data.slave_channels = spear310_dma_info; |
524 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); | 378 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); |
@@ -553,19 +407,6 @@ static void __init spear310_dt_init(void) | |||
553 | if (ret) | 407 | if (ret) |
554 | pr_err("Error registering Shared IRQ 4\n"); | 408 | pr_err("Error registering Shared IRQ 4\n"); |
555 | } | 409 | } |
556 | |||
557 | if (of_machine_is_compatible("st,spear310-evb")) { | ||
558 | /* pmx initialization */ | ||
559 | pmx_driver.base = base; | ||
560 | pmx_driver.mode = NULL; | ||
561 | pmx_driver.devs = spear310_evb_pmx_devs; | ||
562 | pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs); | ||
563 | |||
564 | ret = pmx_register(&pmx_driver); | ||
565 | if (ret) | ||
566 | pr_err("padmux: registration failed. err no: %d\n", | ||
567 | ret); | ||
568 | } | ||
569 | } | 410 | } |
570 | 411 | ||
571 | static const char * const spear310_dt_board_compat[] = { | 412 | static const char * const spear310_dt_board_compat[] = { |
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index 1e74031e1213..4812c692ca35 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c | |||
@@ -23,373 +23,6 @@ | |||
23 | #include <mach/generic.h> | 23 | #include <mach/generic.h> |
24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
25 | 25 | ||
26 | /* pad multiplexing support */ | ||
27 | /* muxing registers */ | ||
28 | #define PAD_MUX_CONFIG_REG 0x0C | ||
29 | #define MODE_CONFIG_REG 0x10 | ||
30 | |||
31 | /* modes */ | ||
32 | #define AUTO_NET_SMII_MODE (1 << 0) | ||
33 | #define AUTO_NET_MII_MODE (1 << 1) | ||
34 | #define AUTO_EXP_MODE (1 << 2) | ||
35 | #define SMALL_PRINTERS_MODE (1 << 3) | ||
36 | #define ALL_MODES 0xF | ||
37 | |||
38 | struct pmx_mode spear320_auto_net_smii_mode = { | ||
39 | .id = AUTO_NET_SMII_MODE, | ||
40 | .name = "Automation Networking SMII Mode", | ||
41 | .mask = 0x00, | ||
42 | }; | ||
43 | |||
44 | struct pmx_mode spear320_auto_net_mii_mode = { | ||
45 | .id = AUTO_NET_MII_MODE, | ||
46 | .name = "Automation Networking MII Mode", | ||
47 | .mask = 0x01, | ||
48 | }; | ||
49 | |||
50 | struct pmx_mode spear320_auto_exp_mode = { | ||
51 | .id = AUTO_EXP_MODE, | ||
52 | .name = "Automation Expanded Mode", | ||
53 | .mask = 0x02, | ||
54 | }; | ||
55 | |||
56 | struct pmx_mode spear320_small_printers_mode = { | ||
57 | .id = SMALL_PRINTERS_MODE, | ||
58 | .name = "Small Printers Mode", | ||
59 | .mask = 0x03, | ||
60 | }; | ||
61 | |||
62 | /* devices */ | ||
63 | static struct pmx_dev_mode pmx_clcd_modes[] = { | ||
64 | { | ||
65 | .ids = AUTO_NET_SMII_MODE, | ||
66 | .mask = 0x0, | ||
67 | }, | ||
68 | }; | ||
69 | |||
70 | struct pmx_dev spear320_pmx_clcd = { | ||
71 | .name = "clcd", | ||
72 | .modes = pmx_clcd_modes, | ||
73 | .mode_count = ARRAY_SIZE(pmx_clcd_modes), | ||
74 | .enb_on_reset = 1, | ||
75 | }; | ||
76 | |||
77 | static struct pmx_dev_mode pmx_emi_modes[] = { | ||
78 | { | ||
79 | .ids = AUTO_EXP_MODE, | ||
80 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, | ||
81 | }, | ||
82 | }; | ||
83 | |||
84 | struct pmx_dev spear320_pmx_emi = { | ||
85 | .name = "emi", | ||
86 | .modes = pmx_emi_modes, | ||
87 | .mode_count = ARRAY_SIZE(pmx_emi_modes), | ||
88 | .enb_on_reset = 1, | ||
89 | }; | ||
90 | |||
91 | static struct pmx_dev_mode pmx_fsmc_modes[] = { | ||
92 | { | ||
93 | .ids = ALL_MODES, | ||
94 | .mask = 0x0, | ||
95 | }, | ||
96 | }; | ||
97 | |||
98 | struct pmx_dev spear320_pmx_fsmc = { | ||
99 | .name = "fsmc", | ||
100 | .modes = pmx_fsmc_modes, | ||
101 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), | ||
102 | .enb_on_reset = 1, | ||
103 | }; | ||
104 | |||
105 | static struct pmx_dev_mode pmx_spp_modes[] = { | ||
106 | { | ||
107 | .ids = SMALL_PRINTERS_MODE, | ||
108 | .mask = 0x0, | ||
109 | }, | ||
110 | }; | ||
111 | |||
112 | struct pmx_dev spear320_pmx_spp = { | ||
113 | .name = "spp", | ||
114 | .modes = pmx_spp_modes, | ||
115 | .mode_count = ARRAY_SIZE(pmx_spp_modes), | ||
116 | .enb_on_reset = 1, | ||
117 | }; | ||
118 | |||
119 | static struct pmx_dev_mode pmx_sdhci_modes[] = { | ||
120 | { | ||
121 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | | ||
122 | SMALL_PRINTERS_MODE, | ||
123 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, | ||
124 | }, | ||
125 | }; | ||
126 | |||
127 | struct pmx_dev spear320_pmx_sdhci = { | ||
128 | .name = "sdhci", | ||
129 | .modes = pmx_sdhci_modes, | ||
130 | .mode_count = ARRAY_SIZE(pmx_sdhci_modes), | ||
131 | .enb_on_reset = 1, | ||
132 | }; | ||
133 | |||
134 | static struct pmx_dev_mode pmx_i2s_modes[] = { | ||
135 | { | ||
136 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, | ||
137 | .mask = PMX_UART0_MODEM_MASK, | ||
138 | }, | ||
139 | }; | ||
140 | |||
141 | struct pmx_dev spear320_pmx_i2s = { | ||
142 | .name = "i2s", | ||
143 | .modes = pmx_i2s_modes, | ||
144 | .mode_count = ARRAY_SIZE(pmx_i2s_modes), | ||
145 | .enb_on_reset = 1, | ||
146 | }; | ||
147 | |||
148 | static struct pmx_dev_mode pmx_uart1_modes[] = { | ||
149 | { | ||
150 | .ids = ALL_MODES, | ||
151 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, | ||
152 | }, | ||
153 | }; | ||
154 | |||
155 | struct pmx_dev spear320_pmx_uart1 = { | ||
156 | .name = "uart1", | ||
157 | .modes = pmx_uart1_modes, | ||
158 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), | ||
159 | .enb_on_reset = 1, | ||
160 | }; | ||
161 | |||
162 | static struct pmx_dev_mode pmx_uart1_modem_modes[] = { | ||
163 | { | ||
164 | .ids = AUTO_EXP_MODE, | ||
165 | .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | | ||
166 | PMX_SSP_CS_MASK, | ||
167 | }, { | ||
168 | .ids = SMALL_PRINTERS_MODE, | ||
169 | .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | | ||
170 | PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, | ||
171 | }, | ||
172 | }; | ||
173 | |||
174 | struct pmx_dev spear320_pmx_uart1_modem = { | ||
175 | .name = "uart1_modem", | ||
176 | .modes = pmx_uart1_modem_modes, | ||
177 | .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), | ||
178 | .enb_on_reset = 1, | ||
179 | }; | ||
180 | |||
181 | static struct pmx_dev_mode pmx_uart2_modes[] = { | ||
182 | { | ||
183 | .ids = ALL_MODES, | ||
184 | .mask = PMX_FIRDA_MASK, | ||
185 | }, | ||
186 | }; | ||
187 | |||
188 | struct pmx_dev spear320_pmx_uart2 = { | ||
189 | .name = "uart2", | ||
190 | .modes = pmx_uart2_modes, | ||
191 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), | ||
192 | .enb_on_reset = 1, | ||
193 | }; | ||
194 | |||
195 | static struct pmx_dev_mode pmx_touchscreen_modes[] = { | ||
196 | { | ||
197 | .ids = AUTO_NET_SMII_MODE, | ||
198 | .mask = PMX_SSP_CS_MASK, | ||
199 | }, | ||
200 | }; | ||
201 | |||
202 | struct pmx_dev spear320_pmx_touchscreen = { | ||
203 | .name = "touchscreen", | ||
204 | .modes = pmx_touchscreen_modes, | ||
205 | .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), | ||
206 | .enb_on_reset = 1, | ||
207 | }; | ||
208 | |||
209 | static struct pmx_dev_mode pmx_can_modes[] = { | ||
210 | { | ||
211 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, | ||
212 | .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | | ||
213 | PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, | ||
214 | }, | ||
215 | }; | ||
216 | |||
217 | struct pmx_dev spear320_pmx_can = { | ||
218 | .name = "can", | ||
219 | .modes = pmx_can_modes, | ||
220 | .mode_count = ARRAY_SIZE(pmx_can_modes), | ||
221 | .enb_on_reset = 1, | ||
222 | }; | ||
223 | |||
224 | static struct pmx_dev_mode pmx_sdhci_led_modes[] = { | ||
225 | { | ||
226 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, | ||
227 | .mask = PMX_SSP_CS_MASK, | ||
228 | }, | ||
229 | }; | ||
230 | |||
231 | struct pmx_dev spear320_pmx_sdhci_led = { | ||
232 | .name = "sdhci_led", | ||
233 | .modes = pmx_sdhci_led_modes, | ||
234 | .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), | ||
235 | .enb_on_reset = 1, | ||
236 | }; | ||
237 | |||
238 | static struct pmx_dev_mode pmx_pwm0_modes[] = { | ||
239 | { | ||
240 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, | ||
241 | .mask = PMX_UART0_MODEM_MASK, | ||
242 | }, { | ||
243 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, | ||
244 | .mask = PMX_MII_MASK, | ||
245 | }, | ||
246 | }; | ||
247 | |||
248 | struct pmx_dev spear320_pmx_pwm0 = { | ||
249 | .name = "pwm0", | ||
250 | .modes = pmx_pwm0_modes, | ||
251 | .mode_count = ARRAY_SIZE(pmx_pwm0_modes), | ||
252 | .enb_on_reset = 1, | ||
253 | }; | ||
254 | |||
255 | static struct pmx_dev_mode pmx_pwm1_modes[] = { | ||
256 | { | ||
257 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, | ||
258 | .mask = PMX_UART0_MODEM_MASK, | ||
259 | }, { | ||
260 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, | ||
261 | .mask = PMX_MII_MASK, | ||
262 | }, | ||
263 | }; | ||
264 | |||
265 | struct pmx_dev spear320_pmx_pwm1 = { | ||
266 | .name = "pwm1", | ||
267 | .modes = pmx_pwm1_modes, | ||
268 | .mode_count = ARRAY_SIZE(pmx_pwm1_modes), | ||
269 | .enb_on_reset = 1, | ||
270 | }; | ||
271 | |||
272 | static struct pmx_dev_mode pmx_pwm2_modes[] = { | ||
273 | { | ||
274 | .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, | ||
275 | .mask = PMX_SSP_CS_MASK, | ||
276 | }, { | ||
277 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, | ||
278 | .mask = PMX_MII_MASK, | ||
279 | }, | ||
280 | }; | ||
281 | |||
282 | struct pmx_dev spear320_pmx_pwm2 = { | ||
283 | .name = "pwm2", | ||
284 | .modes = pmx_pwm2_modes, | ||
285 | .mode_count = ARRAY_SIZE(pmx_pwm2_modes), | ||
286 | .enb_on_reset = 1, | ||
287 | }; | ||
288 | |||
289 | static struct pmx_dev_mode pmx_pwm3_modes[] = { | ||
290 | { | ||
291 | .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, | ||
292 | .mask = PMX_MII_MASK, | ||
293 | }, | ||
294 | }; | ||
295 | |||
296 | struct pmx_dev spear320_pmx_pwm3 = { | ||
297 | .name = "pwm3", | ||
298 | .modes = pmx_pwm3_modes, | ||
299 | .mode_count = ARRAY_SIZE(pmx_pwm3_modes), | ||
300 | .enb_on_reset = 1, | ||
301 | }; | ||
302 | |||
303 | static struct pmx_dev_mode pmx_ssp1_modes[] = { | ||
304 | { | ||
305 | .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, | ||
306 | .mask = PMX_MII_MASK, | ||
307 | }, | ||
308 | }; | ||
309 | |||
310 | struct pmx_dev spear320_pmx_ssp1 = { | ||
311 | .name = "ssp1", | ||
312 | .modes = pmx_ssp1_modes, | ||
313 | .mode_count = ARRAY_SIZE(pmx_ssp1_modes), | ||
314 | .enb_on_reset = 1, | ||
315 | }; | ||
316 | |||
317 | static struct pmx_dev_mode pmx_ssp2_modes[] = { | ||
318 | { | ||
319 | .ids = AUTO_NET_SMII_MODE, | ||
320 | .mask = PMX_MII_MASK, | ||
321 | }, | ||
322 | }; | ||
323 | |||
324 | struct pmx_dev spear320_pmx_ssp2 = { | ||
325 | .name = "ssp2", | ||
326 | .modes = pmx_ssp2_modes, | ||
327 | .mode_count = ARRAY_SIZE(pmx_ssp2_modes), | ||
328 | .enb_on_reset = 1, | ||
329 | }; | ||
330 | |||
331 | static struct pmx_dev_mode pmx_mii1_modes[] = { | ||
332 | { | ||
333 | .ids = AUTO_NET_MII_MODE, | ||
334 | .mask = 0x0, | ||
335 | }, | ||
336 | }; | ||
337 | |||
338 | struct pmx_dev spear320_pmx_mii1 = { | ||
339 | .name = "mii1", | ||
340 | .modes = pmx_mii1_modes, | ||
341 | .mode_count = ARRAY_SIZE(pmx_mii1_modes), | ||
342 | .enb_on_reset = 1, | ||
343 | }; | ||
344 | |||
345 | static struct pmx_dev_mode pmx_smii0_modes[] = { | ||
346 | { | ||
347 | .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, | ||
348 | .mask = PMX_MII_MASK, | ||
349 | }, | ||
350 | }; | ||
351 | |||
352 | struct pmx_dev spear320_pmx_smii0 = { | ||
353 | .name = "smii0", | ||
354 | .modes = pmx_smii0_modes, | ||
355 | .mode_count = ARRAY_SIZE(pmx_smii0_modes), | ||
356 | .enb_on_reset = 1, | ||
357 | }; | ||
358 | |||
359 | static struct pmx_dev_mode pmx_smii1_modes[] = { | ||
360 | { | ||
361 | .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, | ||
362 | .mask = PMX_MII_MASK, | ||
363 | }, | ||
364 | }; | ||
365 | |||
366 | struct pmx_dev spear320_pmx_smii1 = { | ||
367 | .name = "smii1", | ||
368 | .modes = pmx_smii1_modes, | ||
369 | .mode_count = ARRAY_SIZE(pmx_smii1_modes), | ||
370 | .enb_on_reset = 1, | ||
371 | }; | ||
372 | |||
373 | static struct pmx_dev_mode pmx_i2c1_modes[] = { | ||
374 | { | ||
375 | .ids = AUTO_EXP_MODE, | ||
376 | .mask = 0x0, | ||
377 | }, | ||
378 | }; | ||
379 | |||
380 | struct pmx_dev spear320_pmx_i2c1 = { | ||
381 | .name = "i2c1", | ||
382 | .modes = pmx_i2c1_modes, | ||
383 | .mode_count = ARRAY_SIZE(pmx_i2c1_modes), | ||
384 | .enb_on_reset = 1, | ||
385 | }; | ||
386 | |||
387 | /* pmx driver structure */ | ||
388 | static struct pmx_driver pmx_driver = { | ||
389 | .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, | ||
390 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, | ||
391 | }; | ||
392 | |||
393 | /* spear3xx shared irq */ | 26 | /* spear3xx shared irq */ |
394 | static struct shirq_dev_config shirq_ras1_config[] = { | 27 | static struct shirq_dev_config shirq_ras1_config[] = { |
395 | { | 28 | { |
@@ -514,27 +147,6 @@ static struct spear_shirq shirq_intrcomm_ras = { | |||
514 | }, | 147 | }, |
515 | }; | 148 | }; |
516 | 149 | ||
517 | /* padmux devices to enable */ | ||
518 | static struct pmx_dev *spear320_evb_pmx_devs[] = { | ||
519 | /* spear3xx specific devices */ | ||
520 | &spear3xx_pmx_i2c, | ||
521 | &spear3xx_pmx_ssp, | ||
522 | &spear3xx_pmx_mii, | ||
523 | &spear3xx_pmx_uart0, | ||
524 | |||
525 | /* spear320 specific devices */ | ||
526 | &spear320_pmx_fsmc, | ||
527 | &spear320_pmx_sdhci, | ||
528 | &spear320_pmx_i2s, | ||
529 | &spear320_pmx_uart1, | ||
530 | &spear320_pmx_uart2, | ||
531 | &spear320_pmx_can, | ||
532 | &spear320_pmx_pwm0, | ||
533 | &spear320_pmx_pwm1, | ||
534 | &spear320_pmx_pwm2, | ||
535 | &spear320_pmx_mii1, | ||
536 | }; | ||
537 | |||
538 | /* DMAC platform data's slave info */ | 150 | /* DMAC platform data's slave info */ |
539 | struct pl08x_channel_data spear320_dma_info[] = { | 151 | struct pl08x_channel_data spear320_dma_info[] = { |
540 | { | 152 | { |
@@ -772,7 +384,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { | |||
772 | static void __init spear320_dt_init(void) | 384 | static void __init spear320_dt_init(void) |
773 | { | 385 | { |
774 | void __iomem *base; | 386 | void __iomem *base; |
775 | int ret = 0; | 387 | int ret; |
776 | 388 | ||
777 | pl080_plat_data.slave_channels = spear320_dma_info; | 389 | pl080_plat_data.slave_channels = spear320_dma_info; |
778 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); | 390 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); |
@@ -801,19 +413,6 @@ static void __init spear320_dt_init(void) | |||
801 | if (ret) | 413 | if (ret) |
802 | pr_err("Error registering Shared IRQ 4\n"); | 414 | pr_err("Error registering Shared IRQ 4\n"); |
803 | } | 415 | } |
804 | |||
805 | if (of_machine_is_compatible("st,spear320-evb")) { | ||
806 | /* pmx initialization */ | ||
807 | pmx_driver.base = base; | ||
808 | pmx_driver.mode = &spear320_auto_net_mii_mode; | ||
809 | pmx_driver.devs = spear320_evb_pmx_devs; | ||
810 | pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs); | ||
811 | |||
812 | ret = pmx_register(&pmx_driver); | ||
813 | if (ret) | ||
814 | pr_err("padmux: registration failed. err no: %d\n", | ||
815 | ret); | ||
816 | } | ||
817 | } | 416 | } |
818 | 417 | ||
819 | static const char * const spear320_dt_board_compat[] = { | 418 | static const char * const spear320_dt_board_compat[] = { |
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 17d4ac9a95e1..12bf879a9ef1 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c | |||
@@ -23,431 +23,6 @@ | |||
23 | #include <mach/generic.h> | 23 | #include <mach/generic.h> |
24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
25 | 25 | ||
26 | /* pad multiplexing support */ | ||
27 | /* devices */ | ||
28 | static struct pmx_dev_mode pmx_firda_modes[] = { | ||
29 | { | ||
30 | .ids = 0xffffffff, | ||
31 | .mask = PMX_FIRDA_MASK, | ||
32 | }, | ||
33 | }; | ||
34 | |||
35 | struct pmx_dev spear3xx_pmx_firda = { | ||
36 | .name = "firda", | ||
37 | .modes = pmx_firda_modes, | ||
38 | .mode_count = ARRAY_SIZE(pmx_firda_modes), | ||
39 | .enb_on_reset = 0, | ||
40 | }; | ||
41 | |||
42 | static struct pmx_dev_mode pmx_i2c_modes[] = { | ||
43 | { | ||
44 | .ids = 0xffffffff, | ||
45 | .mask = PMX_I2C_MASK, | ||
46 | }, | ||
47 | }; | ||
48 | |||
49 | struct pmx_dev spear3xx_pmx_i2c = { | ||
50 | .name = "i2c", | ||
51 | .modes = pmx_i2c_modes, | ||
52 | .mode_count = ARRAY_SIZE(pmx_i2c_modes), | ||
53 | .enb_on_reset = 0, | ||
54 | }; | ||
55 | |||
56 | static struct pmx_dev_mode pmx_ssp_cs_modes[] = { | ||
57 | { | ||
58 | .ids = 0xffffffff, | ||
59 | .mask = PMX_SSP_CS_MASK, | ||
60 | }, | ||
61 | }; | ||
62 | |||
63 | struct pmx_dev spear3xx_pmx_ssp_cs = { | ||
64 | .name = "ssp_chip_selects", | ||
65 | .modes = pmx_ssp_cs_modes, | ||
66 | .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), | ||
67 | .enb_on_reset = 0, | ||
68 | }; | ||
69 | |||
70 | static struct pmx_dev_mode pmx_ssp_modes[] = { | ||
71 | { | ||
72 | .ids = 0xffffffff, | ||
73 | .mask = PMX_SSP_MASK, | ||
74 | }, | ||
75 | }; | ||
76 | |||
77 | struct pmx_dev spear3xx_pmx_ssp = { | ||
78 | .name = "ssp", | ||
79 | .modes = pmx_ssp_modes, | ||
80 | .mode_count = ARRAY_SIZE(pmx_ssp_modes), | ||
81 | .enb_on_reset = 0, | ||
82 | }; | ||
83 | |||
84 | static struct pmx_dev_mode pmx_mii_modes[] = { | ||
85 | { | ||
86 | .ids = 0xffffffff, | ||
87 | .mask = PMX_MII_MASK, | ||
88 | }, | ||
89 | }; | ||
90 | |||
91 | struct pmx_dev spear3xx_pmx_mii = { | ||
92 | .name = "mii", | ||
93 | .modes = pmx_mii_modes, | ||
94 | .mode_count = ARRAY_SIZE(pmx_mii_modes), | ||
95 | .enb_on_reset = 0, | ||
96 | }; | ||
97 | |||
98 | static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { | ||
99 | { | ||
100 | .ids = 0xffffffff, | ||
101 | .mask = PMX_GPIO_PIN0_MASK, | ||
102 | }, | ||
103 | }; | ||
104 | |||
105 | struct pmx_dev spear3xx_pmx_gpio_pin0 = { | ||
106 | .name = "gpio_pin0", | ||
107 | .modes = pmx_gpio_pin0_modes, | ||
108 | .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), | ||
109 | .enb_on_reset = 0, | ||
110 | }; | ||
111 | |||
112 | static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { | ||
113 | { | ||
114 | .ids = 0xffffffff, | ||
115 | .mask = PMX_GPIO_PIN1_MASK, | ||
116 | }, | ||
117 | }; | ||
118 | |||
119 | struct pmx_dev spear3xx_pmx_gpio_pin1 = { | ||
120 | .name = "gpio_pin1", | ||
121 | .modes = pmx_gpio_pin1_modes, | ||
122 | .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), | ||
123 | .enb_on_reset = 0, | ||
124 | }; | ||
125 | |||
126 | static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { | ||
127 | { | ||
128 | .ids = 0xffffffff, | ||
129 | .mask = PMX_GPIO_PIN2_MASK, | ||
130 | }, | ||
131 | }; | ||
132 | |||
133 | struct pmx_dev spear3xx_pmx_gpio_pin2 = { | ||
134 | .name = "gpio_pin2", | ||
135 | .modes = pmx_gpio_pin2_modes, | ||
136 | .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), | ||
137 | .enb_on_reset = 0, | ||
138 | }; | ||
139 | |||
140 | static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { | ||
141 | { | ||
142 | .ids = 0xffffffff, | ||
143 | .mask = PMX_GPIO_PIN3_MASK, | ||
144 | }, | ||
145 | }; | ||
146 | |||
147 | struct pmx_dev spear3xx_pmx_gpio_pin3 = { | ||
148 | .name = "gpio_pin3", | ||
149 | .modes = pmx_gpio_pin3_modes, | ||
150 | .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), | ||
151 | .enb_on_reset = 0, | ||
152 | }; | ||
153 | |||
154 | static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { | ||
155 | { | ||
156 | .ids = 0xffffffff, | ||
157 | .mask = PMX_GPIO_PIN4_MASK, | ||
158 | }, | ||
159 | }; | ||
160 | |||
161 | struct pmx_dev spear3xx_pmx_gpio_pin4 = { | ||
162 | .name = "gpio_pin4", | ||
163 | .modes = pmx_gpio_pin4_modes, | ||
164 | .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), | ||
165 | .enb_on_reset = 0, | ||
166 | }; | ||
167 | |||
168 | static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { | ||
169 | { | ||
170 | .ids = 0xffffffff, | ||
171 | .mask = PMX_GPIO_PIN5_MASK, | ||
172 | }, | ||
173 | }; | ||
174 | |||
175 | struct pmx_dev spear3xx_pmx_gpio_pin5 = { | ||
176 | .name = "gpio_pin5", | ||
177 | .modes = pmx_gpio_pin5_modes, | ||
178 | .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), | ||
179 | .enb_on_reset = 0, | ||
180 | }; | ||
181 | |||
182 | static struct pmx_dev_mode pmx_uart0_modem_modes[] = { | ||
183 | { | ||
184 | .ids = 0xffffffff, | ||
185 | .mask = PMX_UART0_MODEM_MASK, | ||
186 | }, | ||
187 | }; | ||
188 | |||
189 | struct pmx_dev spear3xx_pmx_uart0_modem = { | ||
190 | .name = "uart0_modem", | ||
191 | .modes = pmx_uart0_modem_modes, | ||
192 | .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), | ||
193 | .enb_on_reset = 0, | ||
194 | }; | ||
195 | |||
196 | static struct pmx_dev_mode pmx_uart0_modes[] = { | ||
197 | { | ||
198 | .ids = 0xffffffff, | ||
199 | .mask = PMX_UART0_MASK, | ||
200 | }, | ||
201 | }; | ||
202 | |||
203 | struct pmx_dev spear3xx_pmx_uart0 = { | ||
204 | .name = "uart0", | ||
205 | .modes = pmx_uart0_modes, | ||
206 | .mode_count = ARRAY_SIZE(pmx_uart0_modes), | ||
207 | .enb_on_reset = 0, | ||
208 | }; | ||
209 | |||
210 | static struct pmx_dev_mode pmx_timer_3_4_modes[] = { | ||
211 | { | ||
212 | .ids = 0xffffffff, | ||
213 | .mask = PMX_TIMER_3_4_MASK, | ||
214 | }, | ||
215 | }; | ||
216 | |||
217 | struct pmx_dev spear3xx_pmx_timer_3_4 = { | ||
218 | .name = "timer_3_4", | ||
219 | .modes = pmx_timer_3_4_modes, | ||
220 | .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), | ||
221 | .enb_on_reset = 0, | ||
222 | }; | ||
223 | |||
224 | static struct pmx_dev_mode pmx_timer_1_2_modes[] = { | ||
225 | { | ||
226 | .ids = 0xffffffff, | ||
227 | .mask = PMX_TIMER_1_2_MASK, | ||
228 | }, | ||
229 | }; | ||
230 | |||
231 | struct pmx_dev spear3xx_pmx_timer_1_2 = { | ||
232 | .name = "timer_1_2", | ||
233 | .modes = pmx_timer_1_2_modes, | ||
234 | .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), | ||
235 | .enb_on_reset = 0, | ||
236 | }; | ||
237 | |||
238 | #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) | ||
239 | /* plgpios devices */ | ||
240 | static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { | ||
241 | { | ||
242 | .ids = 0x00, | ||
243 | .mask = PMX_FIRDA_MASK, | ||
244 | }, | ||
245 | }; | ||
246 | |||
247 | struct pmx_dev spear3xx_pmx_plgpio_0_1 = { | ||
248 | .name = "plgpio 0 and 1", | ||
249 | .modes = pmx_plgpio_0_1_modes, | ||
250 | .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), | ||
251 | .enb_on_reset = 1, | ||
252 | }; | ||
253 | |||
254 | static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { | ||
255 | { | ||
256 | .ids = 0x00, | ||
257 | .mask = PMX_UART0_MASK, | ||
258 | }, | ||
259 | }; | ||
260 | |||
261 | struct pmx_dev spear3xx_pmx_plgpio_2_3 = { | ||
262 | .name = "plgpio 2 and 3", | ||
263 | .modes = pmx_plgpio_2_3_modes, | ||
264 | .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), | ||
265 | .enb_on_reset = 1, | ||
266 | }; | ||
267 | |||
268 | static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { | ||
269 | { | ||
270 | .ids = 0x00, | ||
271 | .mask = PMX_I2C_MASK, | ||
272 | }, | ||
273 | }; | ||
274 | |||
275 | struct pmx_dev spear3xx_pmx_plgpio_4_5 = { | ||
276 | .name = "plgpio 4 and 5", | ||
277 | .modes = pmx_plgpio_4_5_modes, | ||
278 | .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), | ||
279 | .enb_on_reset = 1, | ||
280 | }; | ||
281 | |||
282 | static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { | ||
283 | { | ||
284 | .ids = 0x00, | ||
285 | .mask = PMX_SSP_MASK, | ||
286 | }, | ||
287 | }; | ||
288 | |||
289 | struct pmx_dev spear3xx_pmx_plgpio_6_9 = { | ||
290 | .name = "plgpio 6 to 9", | ||
291 | .modes = pmx_plgpio_6_9_modes, | ||
292 | .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), | ||
293 | .enb_on_reset = 1, | ||
294 | }; | ||
295 | |||
296 | static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { | ||
297 | { | ||
298 | .ids = 0x00, | ||
299 | .mask = PMX_MII_MASK, | ||
300 | }, | ||
301 | }; | ||
302 | |||
303 | struct pmx_dev spear3xx_pmx_plgpio_10_27 = { | ||
304 | .name = "plgpio 10 to 27", | ||
305 | .modes = pmx_plgpio_10_27_modes, | ||
306 | .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), | ||
307 | .enb_on_reset = 1, | ||
308 | }; | ||
309 | |||
310 | static struct pmx_dev_mode pmx_plgpio_28_modes[] = { | ||
311 | { | ||
312 | .ids = 0x00, | ||
313 | .mask = PMX_GPIO_PIN0_MASK, | ||
314 | }, | ||
315 | }; | ||
316 | |||
317 | struct pmx_dev spear3xx_pmx_plgpio_28 = { | ||
318 | .name = "plgpio 28", | ||
319 | .modes = pmx_plgpio_28_modes, | ||
320 | .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), | ||
321 | .enb_on_reset = 1, | ||
322 | }; | ||
323 | |||
324 | static struct pmx_dev_mode pmx_plgpio_29_modes[] = { | ||
325 | { | ||
326 | .ids = 0x00, | ||
327 | .mask = PMX_GPIO_PIN1_MASK, | ||
328 | }, | ||
329 | }; | ||
330 | |||
331 | struct pmx_dev spear3xx_pmx_plgpio_29 = { | ||
332 | .name = "plgpio 29", | ||
333 | .modes = pmx_plgpio_29_modes, | ||
334 | .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), | ||
335 | .enb_on_reset = 1, | ||
336 | }; | ||
337 | |||
338 | static struct pmx_dev_mode pmx_plgpio_30_modes[] = { | ||
339 | { | ||
340 | .ids = 0x00, | ||
341 | .mask = PMX_GPIO_PIN2_MASK, | ||
342 | }, | ||
343 | }; | ||
344 | |||
345 | struct pmx_dev spear3xx_pmx_plgpio_30 = { | ||
346 | .name = "plgpio 30", | ||
347 | .modes = pmx_plgpio_30_modes, | ||
348 | .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), | ||
349 | .enb_on_reset = 1, | ||
350 | }; | ||
351 | |||
352 | static struct pmx_dev_mode pmx_plgpio_31_modes[] = { | ||
353 | { | ||
354 | .ids = 0x00, | ||
355 | .mask = PMX_GPIO_PIN3_MASK, | ||
356 | }, | ||
357 | }; | ||
358 | |||
359 | struct pmx_dev spear3xx_pmx_plgpio_31 = { | ||
360 | .name = "plgpio 31", | ||
361 | .modes = pmx_plgpio_31_modes, | ||
362 | .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), | ||
363 | .enb_on_reset = 1, | ||
364 | }; | ||
365 | |||
366 | static struct pmx_dev_mode pmx_plgpio_32_modes[] = { | ||
367 | { | ||
368 | .ids = 0x00, | ||
369 | .mask = PMX_GPIO_PIN4_MASK, | ||
370 | }, | ||
371 | }; | ||
372 | |||
373 | struct pmx_dev spear3xx_pmx_plgpio_32 = { | ||
374 | .name = "plgpio 32", | ||
375 | .modes = pmx_plgpio_32_modes, | ||
376 | .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), | ||
377 | .enb_on_reset = 1, | ||
378 | }; | ||
379 | |||
380 | static struct pmx_dev_mode pmx_plgpio_33_modes[] = { | ||
381 | { | ||
382 | .ids = 0x00, | ||
383 | .mask = PMX_GPIO_PIN5_MASK, | ||
384 | }, | ||
385 | }; | ||
386 | |||
387 | struct pmx_dev spear3xx_pmx_plgpio_33 = { | ||
388 | .name = "plgpio 33", | ||
389 | .modes = pmx_plgpio_33_modes, | ||
390 | .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), | ||
391 | .enb_on_reset = 1, | ||
392 | }; | ||
393 | |||
394 | static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { | ||
395 | { | ||
396 | .ids = 0x00, | ||
397 | .mask = PMX_SSP_CS_MASK, | ||
398 | }, | ||
399 | }; | ||
400 | |||
401 | struct pmx_dev spear3xx_pmx_plgpio_34_36 = { | ||
402 | .name = "plgpio 34 to 36", | ||
403 | .modes = pmx_plgpio_34_36_modes, | ||
404 | .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), | ||
405 | .enb_on_reset = 1, | ||
406 | }; | ||
407 | |||
408 | static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { | ||
409 | { | ||
410 | .ids = 0x00, | ||
411 | .mask = PMX_UART0_MODEM_MASK, | ||
412 | }, | ||
413 | }; | ||
414 | |||
415 | struct pmx_dev spear3xx_pmx_plgpio_37_42 = { | ||
416 | .name = "plgpio 37 to 42", | ||
417 | .modes = pmx_plgpio_37_42_modes, | ||
418 | .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), | ||
419 | .enb_on_reset = 1, | ||
420 | }; | ||
421 | |||
422 | static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { | ||
423 | { | ||
424 | .ids = 0x00, | ||
425 | .mask = PMX_TIMER_1_2_MASK, | ||
426 | }, | ||
427 | }; | ||
428 | |||
429 | struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { | ||
430 | .name = "plgpio 43, 44, 47 and 48", | ||
431 | .modes = pmx_plgpio_43_44_47_48_modes, | ||
432 | .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), | ||
433 | .enb_on_reset = 1, | ||
434 | }; | ||
435 | |||
436 | static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { | ||
437 | { | ||
438 | .ids = 0x00, | ||
439 | .mask = PMX_TIMER_3_4_MASK, | ||
440 | }, | ||
441 | }; | ||
442 | |||
443 | struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { | ||
444 | .name = "plgpio 45, 46, 49 and 50", | ||
445 | .modes = pmx_plgpio_45_46_49_50_modes, | ||
446 | .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), | ||
447 | .enb_on_reset = 1, | ||
448 | }; | ||
449 | #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ | ||
450 | |||
451 | /* ssp device registration */ | 26 | /* ssp device registration */ |
452 | struct pl022_ssp_controller pl022_plat_data = { | 27 | struct pl022_ssp_controller pl022_plat_data = { |
453 | .bus_id = 0, | 28 | .bus_id = 0, |