diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2012-10-30 23:07:59 -0400 |
---|---|---|
committer | Simon Horman <horms@verge.net.au> | 2012-11-08 01:21:41 -0500 |
commit | dc3cad8222ca0fc67d3f7e867e8e39a64c28bedf (patch) | |
tree | 184a7f083131b1179d42e7b3eb7d88643250d7d0 /arch/arm/mach-shmobile | |
parent | 9ee8008e99b36fff6a06c41a76594dd1b9a0677a (diff) |
ARM: shmobile: sh7372: use sh_clk_fsidiv_register() for FSI-DIV clocks
Now, sh7372 can use sh_clk_fsidiv_register() for FSI-DIV clocks.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r-- | arch/arm/mach-shmobile/clock-sh7372.c | 94 |
1 files changed, 10 insertions, 84 deletions
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 18dcff7551c0..bee2d056f63c 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c | |||
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { | |||
420 | }; | 420 | }; |
421 | 421 | ||
422 | /* FSI DIV */ | 422 | /* FSI DIV */ |
423 | static unsigned long fsidiv_recalc(struct clk *clk) | 423 | enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR }; |
424 | { | ||
425 | unsigned long value; | ||
426 | |||
427 | value = __raw_readl(clk->mapping->base); | ||
428 | |||
429 | value >>= 16; | ||
430 | if (value < 2) | ||
431 | return 0; | ||
432 | |||
433 | return clk->parent->rate / value; | ||
434 | } | ||
435 | |||
436 | static long fsidiv_round_rate(struct clk *clk, unsigned long rate) | ||
437 | { | ||
438 | return clk_rate_div_range_round(clk, 2, 0xffff, rate); | ||
439 | } | ||
440 | |||
441 | static void fsidiv_disable(struct clk *clk) | ||
442 | { | ||
443 | __raw_writel(0, clk->mapping->base); | ||
444 | } | ||
445 | |||
446 | static int fsidiv_enable(struct clk *clk) | ||
447 | { | ||
448 | unsigned long value; | ||
449 | |||
450 | value = __raw_readl(clk->mapping->base) >> 16; | ||
451 | if (value < 2) | ||
452 | return -EIO; | ||
453 | |||
454 | __raw_writel((value << 16) | 0x3, clk->mapping->base); | ||
455 | |||
456 | return 0; | ||
457 | } | ||
458 | 424 | ||
459 | static int fsidiv_set_rate(struct clk *clk, unsigned long rate) | 425 | static struct clk fsidivs[] = { |
460 | { | 426 | [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]), |
461 | int idx; | 427 | [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]), |
462 | |||
463 | idx = (clk->parent->rate / rate) & 0xffff; | ||
464 | if (idx < 2) | ||
465 | return -EINVAL; | ||
466 | |||
467 | __raw_writel(idx << 16, clk->mapping->base); | ||
468 | return 0; | ||
469 | } | ||
470 | |||
471 | static struct sh_clk_ops fsidiv_clk_ops = { | ||
472 | .recalc = fsidiv_recalc, | ||
473 | .round_rate = fsidiv_round_rate, | ||
474 | .set_rate = fsidiv_set_rate, | ||
475 | .enable = fsidiv_enable, | ||
476 | .disable = fsidiv_disable, | ||
477 | }; | ||
478 | |||
479 | static struct clk_mapping fsidiva_clk_mapping = { | ||
480 | .phys = FSIDIVA, | ||
481 | .len = 8, | ||
482 | }; | ||
483 | |||
484 | static struct clk fsidiva_clk = { | ||
485 | .ops = &fsidiv_clk_ops, | ||
486 | .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */ | ||
487 | .mapping = &fsidiva_clk_mapping, | ||
488 | }; | ||
489 | |||
490 | static struct clk_mapping fsidivb_clk_mapping = { | ||
491 | .phys = FSIDIVB, | ||
492 | .len = 8, | ||
493 | }; | ||
494 | |||
495 | static struct clk fsidivb_clk = { | ||
496 | .ops = &fsidiv_clk_ops, | ||
497 | .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */ | ||
498 | .mapping = &fsidivb_clk_mapping, | ||
499 | }; | ||
500 | |||
501 | static struct clk *late_main_clks[] = { | ||
502 | &fsidiva_clk, | ||
503 | &fsidivb_clk, | ||
504 | }; | 428 | }; |
505 | 429 | ||
506 | enum { MSTP001, MSTP000, | 430 | enum { MSTP001, MSTP000, |
@@ -583,8 +507,8 @@ static struct clk_lookup lookups[] = { | |||
583 | CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), | 507 | CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), |
584 | CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), | 508 | CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), |
585 | CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), | 509 | CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), |
586 | CLKDEV_CON_ID("fsidiva", &fsidiva_clk), | 510 | CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]), |
587 | CLKDEV_CON_ID("fsidivb", &fsidivb_clk), | 511 | CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]), |
588 | 512 | ||
589 | /* DIV4 clocks */ | 513 | /* DIV4 clocks */ |
590 | CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), | 514 | CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), |
@@ -680,6 +604,8 @@ static struct clk_lookup lookups[] = { | |||
680 | CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), | 604 | CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), |
681 | CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), | 605 | CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), |
682 | CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]), | 606 | CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]), |
607 | CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]), | ||
608 | CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]), | ||
683 | }; | 609 | }; |
684 | 610 | ||
685 | void __init sh7372_clock_init(void) | 611 | void __init sh7372_clock_init(void) |
@@ -708,8 +634,8 @@ void __init sh7372_clock_init(void) | |||
708 | if (!ret) | 634 | if (!ret) |
709 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); | 635 | ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); |
710 | 636 | ||
711 | for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) | 637 | if (!ret) |
712 | ret = clk_register(late_main_clks[k]); | 638 | ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR); |
713 | 639 | ||
714 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | 640 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
715 | 641 | ||