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authorOlof Johansson <olof@lixom.net>2015-04-01 19:29:08 -0400
committerOlof Johansson <olof@lixom.net>2015-04-01 19:29:31 -0400
commitd36d520ae669ab95e6113f3a5e52493dfaa59f8d (patch)
tree1c68428a8f4b46db0a844684a41dbfde406af319 /arch/arm/mach-shmobile
parent369237ab1fe5539091320f47781d6fe2db0241b9 (diff)
parent914d7d148411997c2f76f689338d27c362300b7a (diff)
Merge tag 'renesas-r8a73a4-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Merge "Renesas ARM Based SoC r8a73a4 CCF and Multiplatform Updates for v4.1" from Simon Horman: * Add CCF and them multiplatform support to r8a73a4 SoC and its ape6evm board. * Then remove legacy r8a73a4 SoC and ape6evm board code. ---------------------------------------------------------------- Geert Uytterhoeven (6): ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node ARM: shmobile: ape6evm dts: Move Ethernet node to BSC ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug ARM: shmobile: ape6evm dts: Drop console= bootargs parameter PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding ARM: shmobile: r8a73a4 dtsi: Add PM domain support Laurent Pinchart (1): ARM: shmobile: r8a73a4: Remove legacy code Simon Horman (1): ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform Ulrich Hecht (5): ARM: shmobile: r8a73a4: Add CPG register bits header ARM: shmobile: r8a73a4: Common clock framework DT description ARM: shmobile: ape6evm: Disable legacy clock initialization ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT ARM: shmobile: ape6evm-reference: Remove board C code and DT file Documentation/devicetree/bindings/arm/shmobile.txt | 2 - .../bindings/power/renesas,sysc-rmobile.txt | 1 + MAINTAINERS | 1 - arch/arm/boot/dts/Makefile | 2 - arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 156 ----- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 37 +- arch/arm/boot/dts/r8a73a4.dtsi | 557 ++++++++++++++++- arch/arm/configs/ape6evm_defconfig | 109 ---- arch/arm/mach-shmobile/Kconfig | 25 - arch/arm/mach-shmobile/Makefile | 3 - arch/arm/mach-shmobile/Makefile.boot | 2 - arch/arm/mach-shmobile/board-ape6evm-reference.c | 60 -- arch/arm/mach-shmobile/board-ape6evm.c | 306 ---------- arch/arm/mach-shmobile/clock-r8a73a4.c | 659 --------------------- arch/arm/mach-shmobile/r8a73a4.h | 17 - arch/arm/mach-shmobile/setup-r8a73a4.c | 273 +-------- include/dt-bindings/clock/r8a73a4-clock.h | 62 ++ 17 files changed, 615 insertions(+), 1657 deletions(-) delete mode 100644 arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts delete mode 100644 arch/arm/configs/ape6evm_defconfig delete mode 100644 arch/arm/mach-shmobile/board-ape6evm-reference.c delete mode 100644 arch/arm/mach-shmobile/board-ape6evm.c delete mode 100644 arch/arm/mach-shmobile/clock-r8a73a4.c delete mode 100644 arch/arm/mach-shmobile/r8a73a4.h create mode 100644 include/dt-bindings/clock/r8a73a4-clock.h * tag 'renesas-r8a73a4-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a73a4: Remove legacy code ARM: shmobile: r8a73a4 dtsi: Add PM domain support PM / Domains: R-Mobile SYSC: Document R-Mobile APE6 (r8a73a4) binding ARM: shmobile: ape6evm dts: Drop console= bootargs parameter ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform ARM: shmobile: ape6evm-reference: Remove board C code and DT file ARM: shmobile: r8a73a4: Move pfc node to work around probe ordering bug ARM: shmobile: ape6evm dts: Move Ethernet node to BSC ARM: shmobile: r8a73a4 dtsi: Add Bus State Controller node ARM: shmobile: r8a73a4: Add MSTP clock assignments to DT ARM: shmobile: ape6evm: Disable legacy clock initialization ARM: shmobile: r8a73a4: Common clock framework DT description ARM: shmobile: r8a73a4: Add CPG register bits header Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/Kconfig25
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot2
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm-reference.c60
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm.c306
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c659
-rw-r--r--arch/arm/mach-shmobile/r8a73a4.h17
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c273
8 files changed, 2 insertions, 1343 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 15a7dba2a683..485961a4de1d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -105,13 +105,6 @@ config ARCH_SH73A0
105 select SH_INTC 105 select SH_INTC
106 select RENESAS_INTC_IRQPIN 106 select RENESAS_INTC_IRQPIN
107 107
108config ARCH_R8A73A4
109 bool "R-Mobile APE6 (R8A73A40)"
110 select ARCH_RMOBILE
111 select ARCH_WANT_OPTIONAL_GPIOLIB
112 select ARM_GIC
113 select RENESAS_IRQC
114
115config ARCH_R8A7740 108config ARCH_R8A7740
116 bool "R-Mobile A1 (R8A77400)" 109 bool "R-Mobile A1 (R8A77400)"
117 select ARCH_RMOBILE 110 select ARCH_RMOBILE
@@ -133,24 +126,6 @@ config ARCH_R8A7779
133 126
134comment "Renesas ARM SoCs Board Type" 127comment "Renesas ARM SoCs Board Type"
135 128
136config MACH_APE6EVM
137 bool "APE6EVM board"
138 depends on ARCH_R8A73A4
139 select SMSC_PHY if SMSC911X
140 select USE_OF
141
142config MACH_APE6EVM_REFERENCE
143 bool "APE6EVM board - Reference Device Tree Implementation"
144 depends on ARCH_R8A73A4
145 select SMSC_PHY if SMSC911X
146 select USE_OF
147 ---help---
148 Use reference implementation of APE6EVM board support
149 which makes a greater use of device tree at the expense
150 of not supporting a number of devices.
151
152 This is intended to aid developers
153
154config MACH_ARMADILLO800EVA 129config MACH_ARMADILLO800EVA
155 bool "Armadillo-800 EVA board" 130 bool "Armadillo-800 EVA board"
156 depends on ARCH_R8A7740 131 depends on ARCH_R8A7740
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index beb3f1491e68..ba7bb7847ae3 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
21ifndef CONFIG_COMMON_CLK 21ifndef CONFIG_COMMON_CLK
22obj-y += clock.o 22obj-y += clock.o
23obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o 23obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
24obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
25obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o 24obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
26obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 25obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
27obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 26obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
@@ -53,8 +52,6 @@ obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
53ifdef CONFIG_ARCH_SHMOBILE_MULTI 52ifdef CONFIG_ARCH_SHMOBILE_MULTI
54obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 53obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
55else 54else
56obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
57obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o
58obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 55obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
59obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 56obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
60obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 57obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index c496af795a6e..da9fc6d4a1da 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -1,7 +1,5 @@
1# per-board load address for uImage 1# per-board load address for uImage
2loadaddr-y := 2loadaddr-y :=
3loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
4loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 3loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
6loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 4loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 5loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
deleted file mode 100644
index 3b68370b03a0..000000000000
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * APE6EVM board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/gpio.h>
18#include <linux/kernel.h>
19#include <linux/of_platform.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/platform_device.h>
22#include <linux/sh_clk.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26
27#include "common.h"
28#include "r8a73a4.h"
29
30static void __init ape6evm_add_standard_devices(void)
31{
32
33 struct clk *parent;
34 struct clk *mp;
35
36 r8a73a4_clock_init();
37
38 /* MP clock parent = extal2 */
39 parent = clk_get(NULL, "extal2");
40 mp = clk_get(NULL, "mp");
41 BUG_ON(IS_ERR(parent) || IS_ERR(mp));
42
43 clk_set_parent(mp, parent);
44 clk_put(parent);
45 clk_put(mp);
46
47 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
48}
49
50static const char *ape6evm_boards_compat_dt[] __initdata = {
51 "renesas,ape6evm-reference",
52 NULL,
53};
54
55DT_MACHINE_START(APE6EVM_DT, "ape6evm")
56 .init_early = shmobile_init_delay,
57 .init_machine = ape6evm_add_standard_devices,
58 .init_late = shmobile_init_late,
59 .dt_compat = ape6evm_boards_compat_dt,
60MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
deleted file mode 100644
index 444f22d370f0..000000000000
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ /dev/null
@@ -1,306 +0,0 @@
1/*
2 * APE6EVM board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/gpio.h>
18#include <linux/gpio_keys.h>
19#include <linux/input.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip.h>
22#include <linux/irqchip/arm-gic.h>
23#include <linux/kernel.h>
24#include <linux/mfd/tmio.h>
25#include <linux/mmc/host.h>
26#include <linux/mmc/sh_mmcif.h>
27#include <linux/mmc/sh_mobile_sdhi.h>
28#include <linux/pinctrl/machine.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h>
32#include <linux/sh_clk.h>
33#include <linux/smsc911x.h>
34
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37
38#include "common.h"
39#include "irqs.h"
40#include "r8a73a4.h"
41
42/* LEDS */
43static struct gpio_led ape6evm_leds[] = {
44 {
45 .name = "gnss-en",
46 .gpio = 28,
47 .default_state = LEDS_GPIO_DEFSTATE_OFF,
48 }, {
49 .name = "nfc-nrst",
50 .gpio = 126,
51 .default_state = LEDS_GPIO_DEFSTATE_OFF,
52 }, {
53 .name = "gnss-nrst",
54 .gpio = 132,
55 .default_state = LEDS_GPIO_DEFSTATE_OFF,
56 }, {
57 .name = "bt-wakeup",
58 .gpio = 232,
59 .default_state = LEDS_GPIO_DEFSTATE_OFF,
60 }, {
61 .name = "strobe",
62 .gpio = 250,
63 .default_state = LEDS_GPIO_DEFSTATE_OFF,
64 }, {
65 .name = "bbresetout",
66 .gpio = 288,
67 .default_state = LEDS_GPIO_DEFSTATE_OFF,
68 },
69};
70
71static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = {
72 .leds = ape6evm_leds,
73 .num_leds = ARRAY_SIZE(ape6evm_leds),
74};
75
76/* GPIO KEY */
77#define GPIO_KEY(c, g, d, ...) \
78 { .code = c, .gpio = g, .desc = d, .active_low = 1 }
79
80static struct gpio_keys_button gpio_buttons[] = {
81 GPIO_KEY(KEY_0, 324, "S16"),
82 GPIO_KEY(KEY_MENU, 325, "S17"),
83 GPIO_KEY(KEY_HOME, 326, "S18"),
84 GPIO_KEY(KEY_BACK, 327, "S19"),
85 GPIO_KEY(KEY_VOLUMEUP, 328, "S20"),
86 GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"),
87};
88
89static struct gpio_keys_platform_data ape6evm_keys_pdata __initdata = {
90 .buttons = gpio_buttons,
91 .nbuttons = ARRAY_SIZE(gpio_buttons),
92};
93
94/* Dummy supplies, where voltage doesn't matter */
95static struct regulator_consumer_supply dummy_supplies[] = {
96 REGULATOR_SUPPLY("vddvario", "smsc911x"),
97 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
98};
99
100/* SMSC LAN9220 */
101static const struct resource lan9220_res[] __initconst = {
102 DEFINE_RES_MEM(0x08000000, 0x1000),
103 {
104 .start = irq_pin(40), /* IRQ40 */
105 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
106 },
107};
108
109static const struct smsc911x_platform_config lan9220_data __initconst = {
110 .flags = SMSC911X_USE_32BIT,
111 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
112 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
113};
114
115/*
116 * MMC0 power supplies:
117 * Both Vcc and VccQ to eMMC on APE6EVM are supplied by a tps80032 voltage
118 * regulator. Until support for it is added to this file we simulate the
119 * Vcc supply by a fixed always-on regulator
120 */
121static struct regulator_consumer_supply vcc_mmc0_consumers[] =
122{
123 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
124};
125
126/*
127 * SDHI0 power supplies:
128 * Vcc to SDHI0 on APE6EVM is supplied by a GPIO-switchable regulator. VccQ is
129 * provided by the same tps80032 regulator as both MMC0 voltages - see comment
130 * above
131 */
132static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
133{
134 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
135};
136
137static struct regulator_init_data vcc_sdhi0_init_data = {
138 .constraints = {
139 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
140 },
141 .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
142 .consumer_supplies = vcc_sdhi0_consumers,
143};
144
145static const struct fixed_voltage_config vcc_sdhi0_info __initconst = {
146 .supply_name = "SDHI0 Vcc",
147 .microvolts = 3300000,
148 .gpio = 76,
149 .enable_high = 1,
150 .init_data = &vcc_sdhi0_init_data,
151};
152
153/*
154 * SDHI1 power supplies:
155 * Vcc and VccQ to SDHI1 on APE6EVM are both fixed at 3.3V
156 */
157static struct regulator_consumer_supply vcc_sdhi1_consumers[] =
158{
159 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
160};
161
162/* MMCIF */
163static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = {
164 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
165 .slave_id_tx = SHDMA_SLAVE_MMCIF0_TX,
166 .slave_id_rx = SHDMA_SLAVE_MMCIF0_RX,
167 .ccs_unsupported = true,
168};
169
170static const struct resource mmcif0_resources[] __initconst = {
171 DEFINE_RES_MEM(0xee200000, 0x100),
172 DEFINE_RES_IRQ(gic_spi(169)),
173};
174
175/* SDHI0 */
176static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = {
177 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
178 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
179};
180
181static const struct resource sdhi0_resources[] __initconst = {
182 DEFINE_RES_MEM(0xee100000, 0x100),
183 DEFINE_RES_IRQ(gic_spi(165)),
184};
185
186/* SDHI1 */
187static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
188 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
189 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
190 MMC_CAP_NEEDS_POLL,
191};
192
193static const struct resource sdhi1_resources[] __initconst = {
194 DEFINE_RES_MEM(0xee120000, 0x100),
195 DEFINE_RES_IRQ(gic_spi(166)),
196};
197
198static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = {
199 /* SCIFA0 console */
200 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
201 "scifa0_data", "scifa0"),
202 /* SMSC */
203 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
204 "irqc_irq40", "irqc"),
205 /* MMCIF0 */
206 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
207 "mmc0_data8", "mmc0"),
208 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
209 "mmc0_ctrl", "mmc0"),
210 /* SDHI0: uSD: no WP */
211 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
212 "sdhi0_data4", "sdhi0"),
213 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
214 "sdhi0_ctrl", "sdhi0"),
215 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
216 "sdhi0_cd", "sdhi0"),
217 /* SDHI1 */
218 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
219 "sdhi1_data4", "sdhi1"),
220 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
221 "sdhi1_ctrl", "sdhi1"),
222};
223
224static void __init ape6evm_add_standard_devices(void)
225{
226
227 struct clk *parent;
228 struct clk *mp;
229
230 r8a73a4_clock_init();
231
232 /* MP clock parent = extal2 */
233 parent = clk_get(NULL, "extal2");
234 mp = clk_get(NULL, "mp");
235 BUG_ON(IS_ERR(parent) || IS_ERR(mp));
236
237 clk_set_parent(mp, parent);
238 clk_put(parent);
239 clk_put(mp);
240
241 pinctrl_register_mappings(ape6evm_pinctrl_map,
242 ARRAY_SIZE(ape6evm_pinctrl_map));
243 r8a73a4_pinmux_init();
244 r8a73a4_add_standard_devices();
245
246 /* LAN9220 ethernet */
247 gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
248
249 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
250
251 platform_device_register_resndata(NULL, "smsc911x", -1,
252 lan9220_res, ARRAY_SIZE(lan9220_res),
253 &lan9220_data, sizeof(lan9220_data));
254
255 regulator_register_always_on(1, "MMC0 Vcc", vcc_mmc0_consumers,
256 ARRAY_SIZE(vcc_mmc0_consumers), 2800000);
257 platform_device_register_resndata(NULL, "sh_mmcif", 0,
258 mmcif0_resources, ARRAY_SIZE(mmcif0_resources),
259 &mmcif0_pdata, sizeof(mmcif0_pdata));
260 platform_device_register_data(NULL, "reg-fixed-voltage", 2,
261 &vcc_sdhi0_info, sizeof(vcc_sdhi0_info));
262 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
263 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
264 &sdhi0_pdata, sizeof(sdhi0_pdata));
265 regulator_register_always_on(3, "SDHI1 Vcc", vcc_sdhi1_consumers,
266 ARRAY_SIZE(vcc_sdhi1_consumers), 3300000);
267 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 1,
268 sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
269 &sdhi1_pdata, sizeof(sdhi1_pdata));
270 platform_device_register_data(NULL, "gpio-keys", -1,
271 &ape6evm_keys_pdata,
272 sizeof(ape6evm_keys_pdata));
273 platform_device_register_data(NULL, "leds-gpio", -1,
274 &ape6evm_leds_pdata,
275 sizeof(ape6evm_leds_pdata));
276}
277
278static void __init ape6evm_legacy_init_time(void)
279{
280 /* Do not invoke DT-based timers via clocksource_of_init() */
281}
282
283static void __init ape6evm_legacy_init_irq(void)
284{
285 void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
286 void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
287
288 gic_init(0, 29, gic_dist_base, gic_cpu_base);
289
290 /* Do not invoke DT-based interrupt code via irqchip_init() */
291}
292
293
294static const char *ape6evm_boards_compat_dt[] __initdata = {
295 "renesas,ape6evm",
296 NULL,
297};
298
299DT_MACHINE_START(APE6EVM_DT, "ape6evm")
300 .init_early = shmobile_init_delay,
301 .init_irq = ape6evm_legacy_init_irq,
302 .init_machine = ape6evm_add_standard_devices,
303 .init_late = shmobile_init_late,
304 .dt_compat = ape6evm_boards_compat_dt,
305 .init_time = ape6evm_legacy_init_time,
306MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
deleted file mode 100644
index 1cf44dc6d718..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ /dev/null
@@ -1,659 +0,0 @@
1/*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/sh_clk.h>
20#include <linux/clkdev.h>
21#include "common.h"
22#include "clock.h"
23
24#define CPG_BASE 0xe6150000
25#define CPG_LEN 0x270
26
27#define SMSTPCR2 0xe6150138
28#define SMSTPCR3 0xe615013c
29#define SMSTPCR4 0xe6150140
30#define SMSTPCR5 0xe6150144
31
32#define FRQCRA 0xE6150000
33#define FRQCRB 0xE6150004
34#define FRQCRC 0xE61500E0
35#define VCLKCR1 0xE6150008
36#define VCLKCR2 0xE615000C
37#define VCLKCR3 0xE615001C
38#define VCLKCR4 0xE6150014
39#define VCLKCR5 0xE6150034
40#define ZBCKCR 0xE6150010
41#define SD0CKCR 0xE6150074
42#define SD1CKCR 0xE6150078
43#define SD2CKCR 0xE615007C
44#define MMC0CKCR 0xE6150240
45#define MMC1CKCR 0xE6150244
46#define FSIACKCR 0xE6150018
47#define FSIBCKCR 0xE6150090
48#define MPCKCR 0xe6150080
49#define SPUVCKCR 0xE6150094
50#define HSICKCR 0xE615026C
51#define M4CKCR 0xE6150098
52#define PLLECR 0xE61500D0
53#define PLL0CR 0xE61500D8
54#define PLL1CR 0xE6150028
55#define PLL2CR 0xE615002C
56#define PLL2SCR 0xE61501F4
57#define PLL2HCR 0xE61501E4
58#define CKSCR 0xE61500C0
59
60#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
61
62static struct clk_mapping cpg_mapping = {
63 .phys = CPG_BASE,
64 .len = CPG_LEN,
65};
66
67static struct clk extalr_clk = {
68 .rate = 32768,
69 .mapping = &cpg_mapping,
70};
71
72static struct clk extal1_clk = {
73 .rate = 26000000,
74 .mapping = &cpg_mapping,
75};
76
77static struct clk extal2_clk = {
78 .rate = 48000000,
79 .mapping = &cpg_mapping,
80};
81
82static struct sh_clk_ops followparent_clk_ops = {
83 .recalc = followparent_recalc,
84};
85
86static struct clk main_clk = {
87 /* .parent will be set r8a73a4_clock_init */
88 .ops = &followparent_clk_ops,
89};
90
91SH_CLK_RATIO(div2, 1, 2);
92SH_CLK_RATIO(div4, 1, 4);
93
94SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
95SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
96SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
97SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
98
99/* External FSIACK/FSIBCK clock */
100static struct clk fsiack_clk = {
101};
102
103static struct clk fsibck_clk = {
104};
105
106/*
107 * PLL clocks
108 */
109static struct clk *pll_parent_main[] = {
110 [0] = &main_clk,
111 [1] = &main_div2_clk
112};
113
114static struct clk *pll_parent_main_extal[8] = {
115 [0] = &main_div2_clk,
116 [1] = &extal2_div2_clk,
117 [3] = &extal2_div4_clk,
118 [4] = &main_clk,
119 [5] = &extal2_clk,
120};
121
122static unsigned long pll_recalc(struct clk *clk)
123{
124 unsigned long mult = 1;
125
126 if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
127 mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
128
129 return clk->parent->rate * mult;
130}
131
132static int pll_set_parent(struct clk *clk, struct clk *parent)
133{
134 u32 val;
135 int i, ret;
136
137 if (!clk->parent_table || !clk->parent_num)
138 return -EINVAL;
139
140 /* Search the parent */
141 for (i = 0; i < clk->parent_num; i++)
142 if (clk->parent_table[i] == parent)
143 break;
144
145 if (i == clk->parent_num)
146 return -ENODEV;
147
148 ret = clk_reparent(clk, parent);
149 if (ret < 0)
150 return ret;
151
152 val = ioread32(clk->mapped_reg) &
153 ~(((1 << clk->src_width) - 1) << clk->src_shift);
154
155 iowrite32(val | i << clk->src_shift, clk->mapped_reg);
156
157 return 0;
158}
159
160static struct sh_clk_ops pll_clk_ops = {
161 .recalc = pll_recalc,
162 .set_parent = pll_set_parent,
163};
164
165#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
166 static struct clk name = { \
167 .ops = &pll_clk_ops, \
168 .flags = CLK_ENABLE_ON_INIT, \
169 .parent = p, \
170 .parent_table = pt, \
171 .parent_num = ARRAY_SIZE(pt), \
172 .src_width = w, \
173 .src_shift = s, \
174 .enable_reg = (void __iomem *)reg, \
175 .enable_bit = e, \
176 .mapping = &cpg_mapping, \
177 }
178
179PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
180PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
181PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
182PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
183PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
184
185SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
186
187static atomic_t frqcr_lock;
188
189/* Several clocks need to access FRQCRB, have to lock */
190static bool frqcr_kick_check(struct clk *clk)
191{
192 return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
193}
194
195static int frqcr_kick_do(struct clk *clk)
196{
197 int i;
198
199 /* set KICK bit in FRQCRB to update hardware setting, check success */
200 iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
201 for (i = 1000; i; i--)
202 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
203 cpu_relax();
204 else
205 return 0;
206
207 return -ETIMEDOUT;
208}
209
210static int zclk_set_rate(struct clk *clk, unsigned long rate)
211{
212 void __iomem *frqcrc;
213 int ret;
214 unsigned long step, p_rate;
215 u32 val;
216
217 if (!clk->parent || !__clk_get(clk->parent))
218 return -ENODEV;
219
220 if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
221 ret = -EBUSY;
222 goto done;
223 }
224
225 /*
226 * Users are supposed to first call clk_set_rate() only with
227 * clk_round_rate() results. So, we don't fix wrong rates here, but
228 * guard against them anyway
229 */
230
231 p_rate = clk_get_rate(clk->parent);
232 if (rate == p_rate) {
233 val = 0;
234 } else {
235 step = DIV_ROUND_CLOSEST(p_rate, 32);
236
237 if (rate > p_rate || rate < step) {
238 ret = -EINVAL;
239 goto done;
240 }
241
242 val = 32 - rate / step;
243 }
244
245 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
246
247 iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
248 (val << clk->enable_bit), frqcrc);
249
250 ret = frqcr_kick_do(clk);
251
252done:
253 atomic_dec(&frqcr_lock);
254 __clk_put(clk->parent);
255 return ret;
256}
257
258static long zclk_round_rate(struct clk *clk, unsigned long rate)
259{
260 /*
261 * theoretical rate = parent rate * multiplier / 32,
262 * where 1 <= multiplier <= 32. Therefore we should do
263 * multiplier = rate * 32 / parent rate
264 * rounded rate = parent rate * multiplier / 32.
265 * However, multiplication before division won't fit in 32 bits, so
266 * we sacrifice some precision by first dividing and then multiplying.
267 * To find the nearest divisor we calculate both and pick up the best
268 * one. This avoids 64-bit arithmetics.
269 */
270 unsigned long step, mul_min, mul_max, rate_min, rate_max;
271
272 rate_max = clk_get_rate(clk->parent);
273
274 /* output freq <= parent */
275 if (rate >= rate_max)
276 return rate_max;
277
278 step = DIV_ROUND_CLOSEST(rate_max, 32);
279 /* output freq >= parent / 32 */
280 if (step >= rate)
281 return step;
282
283 mul_min = rate / step;
284 mul_max = DIV_ROUND_UP(rate, step);
285 rate_min = step * mul_min;
286 if (mul_max == mul_min)
287 return rate_min;
288
289 rate_max = step * mul_max;
290
291 if (rate_max - rate < rate - rate_min)
292 return rate_max;
293
294 return rate_min;
295}
296
297static unsigned long zclk_recalc(struct clk *clk)
298{
299 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
300 unsigned int max = clk->div_mask + 1;
301 unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
302 clk->div_mask);
303
304 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
305 (max - val);
306}
307
308static struct sh_clk_ops zclk_ops = {
309 .recalc = zclk_recalc,
310 .set_rate = zclk_set_rate,
311 .round_rate = zclk_round_rate,
312};
313
314static struct clk z_clk = {
315 .parent = &pll0_clk,
316 .div_mask = 0x1f,
317 .enable_bit = 8,
318 /* We'll need to access FRQCRB and FRQCRC */
319 .enable_reg = (void __iomem *)FRQCRB,
320 .ops = &zclk_ops,
321};
322
323/*
324 * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
325 * switching is only available in auto-DVFS mode
326 */
327SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
328
329static struct clk z2_clk = {
330 .parent = &pll0_div2_clk,
331 .div_mask = 0x1f,
332 .enable_bit = 0,
333 /* We'll need to access FRQCRB and FRQCRC */
334 .enable_reg = (void __iomem *)FRQCRB,
335 .ops = &zclk_ops,
336};
337
338static struct clk *main_clks[] = {
339 &extalr_clk,
340 &extal1_clk,
341 &extal1_div2_clk,
342 &extal2_clk,
343 &extal2_div2_clk,
344 &extal2_div4_clk,
345 &main_clk,
346 &main_div2_clk,
347 &fsiack_clk,
348 &fsibck_clk,
349 &pll0_clk,
350 &pll1_clk,
351 &pll1_div2_clk,
352 &pll2_clk,
353 &pll2s_clk,
354 &pll2h_clk,
355 &z_clk,
356 &pll0_div2_clk,
357 &z2_clk,
358};
359
360/* DIV4 */
361static void div4_kick(struct clk *clk)
362{
363 if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
364 frqcr_kick_do(clk);
365 atomic_dec(&frqcr_lock);
366}
367
368static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
369
370static struct clk_div_mult_table div4_div_mult_table = {
371 .divisors = divisors,
372 .nr_divisors = ARRAY_SIZE(divisors),
373};
374
375static struct clk_div4_table div4_table = {
376 .div_mult_table = &div4_div_mult_table,
377 .kick = div4_kick,
378};
379
380enum {
381 DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
382 DIV4_ZX, DIV4_ZS, DIV4_HP,
383 DIV4_NR };
384
385static struct clk div4_clks[DIV4_NR] = {
386 [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
387 [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
388 [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
389 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
390 [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
391 [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
392 [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
393 [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
394};
395
396enum {
397 DIV6_ZB,
398 DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
399 DIV6_MMC0, DIV6_MMC1,
400 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
401 DIV6_FSIA, DIV6_FSIB,
402 DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
403 DIV6_NR };
404
405static struct clk *div6_parents[8] = {
406 [0] = &pll1_div2_clk,
407 [1] = &pll2s_clk,
408 [3] = &extal2_clk,
409 [4] = &main_div2_clk,
410 [6] = &extalr_clk,
411};
412
413static struct clk *fsia_parents[4] = {
414 [0] = &pll1_div2_clk,
415 [1] = &pll2s_clk,
416 [2] = &fsiack_clk,
417};
418
419static struct clk *fsib_parents[4] = {
420 [0] = &pll1_div2_clk,
421 [1] = &pll2s_clk,
422 [2] = &fsibck_clk,
423};
424
425static struct clk *mp_parents[4] = {
426 [0] = &pll1_div2_clk,
427 [1] = &pll2s_clk,
428 [2] = &extal2_clk,
429 [3] = &extal2_clk,
430};
431
432static struct clk *m4_parents[2] = {
433 [0] = &pll2s_clk,
434};
435
436static struct clk *hsi_parents[4] = {
437 [0] = &pll2h_clk,
438 [1] = &pll1_div2_clk,
439 [3] = &pll2s_clk,
440};
441
442/*** FIXME ***
443 * SH_CLK_DIV6_EXT() macro doesn't care .mapping
444 * but, it is necessary on R-Car (= ioremap() base CPG)
445 * The difference between
446 * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
447 * is only .mapping
448 */
449#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
450 _num_parents, _src_shift, _src_width) \
451{ \
452 .enable_reg = (void __iomem *)_reg, \
453 .enable_bit = 0, /* unused */ \
454 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
455 .div_mask = SH_CLK_DIV6_MSK, \
456 .parent_table = _parents, \
457 .parent_num = _num_parents, \
458 .src_shift = _src_shift, \
459 .src_width = _src_width, \
460 .mapping = &cpg_mapping, \
461}
462
463static struct clk div6_clks[DIV6_NR] = {
464 [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
465 div6_parents, 2, 7, 1),
466 [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
467 div6_parents, 2, 6, 2),
468 [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
469 div6_parents, 2, 6, 2),
470 [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
471 div6_parents, 2, 6, 2),
472 [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
473 div6_parents, 2, 6, 2),
474 [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
475 div6_parents, 2, 6, 2),
476 [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
477 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
478 [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
479 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
480 [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
481 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
482 [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
483 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
484 [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
485 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
486 [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
487 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
488 [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
489 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
490 [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
491 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
492 /* pll2s will be selected always for M4 */
493 [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
494 m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
495 [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
496 hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
497 [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
498 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
499};
500
501/* MSTP */
502enum {
503 MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
504 MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
505 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
506 MSTP411, MSTP410, MSTP409,
507 MSTP522, MSTP515,
508 MSTP_NR
509};
510
511static struct clk mstp_clks[MSTP_NR] = {
512 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */
513 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */
514 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */
515 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
516 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
517 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
518 [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
519 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
520 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
521 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
522 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
523 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
524 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
525 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */
526 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */
527 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */
528 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
529 [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
530 [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */
531 [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
532 [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
533 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
534 [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */
535};
536
537static struct clk_lookup lookups[] = {
538 /* main clock */
539 CLKDEV_CON_ID("extal1", &extal1_clk),
540 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
541 CLKDEV_CON_ID("extal2", &extal2_clk),
542 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
543 CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
544 CLKDEV_CON_ID("fsiack", &fsiack_clk),
545 CLKDEV_CON_ID("fsibck", &fsibck_clk),
546
547 /* pll clock */
548 CLKDEV_CON_ID("pll1", &pll1_clk),
549 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
550 CLKDEV_CON_ID("pll2", &pll2_clk),
551 CLKDEV_CON_ID("pll2s", &pll2s_clk),
552 CLKDEV_CON_ID("pll2h", &pll2h_clk),
553
554 /* CPU clock */
555 CLKDEV_DEV_ID("cpu0", &z_clk),
556
557 /* DIV6 */
558 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
559 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
560 CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]),
561 CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]),
562 CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]),
563 CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]),
564 CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]),
565 CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]),
566 CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]),
567 CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]),
568 CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]),
569 CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]),
570
571 /* MSTP */
572 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
573 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
574 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
575 CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
576 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
577 CLKDEV_DEV_ID("e6c20000.serial", &mstp_clks[MSTP206]),
578 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
579 CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP207]),
580 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
581 CLKDEV_DEV_ID("e6ce0000.serial", &mstp_clks[MSTP216]),
582 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
583 CLKDEV_DEV_ID("e6cf0000.serial", &mstp_clks[MSTP217]),
584 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
585 CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
586 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
587 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
588 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
589 CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
590 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
591 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
592 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
593 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
594 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
595 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
596 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
597 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
598 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
599 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
600 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
601 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
602 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]),
603 CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]),
604 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
605 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
606 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
607 CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
608
609 /* for DT */
610 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
611};
612
613void __init r8a73a4_clock_init(void)
614{
615 void __iomem *reg;
616 int k, ret = 0;
617 u32 ckscr;
618
619 atomic_set(&frqcr_lock, -1);
620
621 reg = ioremap_nocache(CKSCR, PAGE_SIZE);
622 BUG_ON(!reg);
623 ckscr = ioread32(reg);
624 iounmap(reg);
625
626 switch ((ckscr >> 28) & 0x3) {
627 case 0:
628 main_clk.parent = &extal1_clk;
629 break;
630 case 1:
631 main_clk.parent = &extal1_div2_clk;
632 break;
633 case 2:
634 main_clk.parent = &extal2_clk;
635 break;
636 case 3:
637 main_clk.parent = &extal2_div2_clk;
638 break;
639 }
640
641 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
642 ret = clk_register(main_clks[k]);
643
644 if (!ret)
645 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
646
647 if (!ret)
648 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
649
650 if (!ret)
651 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
652
653 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
654
655 if (!ret)
656 shmobile_clk_init();
657 else
658 panic("failed to setup r8a73a4 clocks\n");
659}
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
deleted file mode 100644
index 70dcd847a86e..000000000000
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_R8A73A4_H__
2#define __ASM_R8A73A4_H__
3
4/* DMA slave IDs */
5enum {
6 SHDMA_SLAVE_INVALID,
7 SHDMA_SLAVE_MMCIF0_TX,
8 SHDMA_SLAVE_MMCIF0_RX,
9 SHDMA_SLAVE_MMCIF1_TX,
10 SHDMA_SLAVE_MMCIF1_RX,
11};
12
13void r8a73a4_add_standard_devices(void);
14void r8a73a4_clock_init(void);
15void r8a73a4_pinmux_init(void);
16
17#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index c27682291cbf..446cee611902 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -13,280 +13,12 @@
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16#include <linux/irq.h> 16
17#include <linux/kernel.h> 17#include <linux/init.h>
18#include <linux/of_platform.h>
19#include <linux/platform_data/irq-renesas-irqc.h>
20#include <linux/serial_sci.h>
21#include <linux/sh_dma.h>
22#include <linux/sh_timer.h>
23 18
24#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
25 20
26#include "common.h" 21#include "common.h"
27#include "dma-register.h"
28#include "irqs.h"
29#include "r8a73a4.h"
30
31static const struct resource pfc_resources[] = {
32 DEFINE_RES_MEM(0xe6050000, 0x9000),
33};
34
35void __init r8a73a4_pinmux_init(void)
36{
37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
38 ARRAY_SIZE(pfc_resources));
39}
40
41#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
42static struct plat_sci_port scif##index##_platform_data = { \
43 .type = scif_type, \
44 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
45 .scscr = _scscr, \
46}; \
47 \
48static struct resource scif##index##_resources[] = { \
49 DEFINE_RES_MEM(baseaddr, 0x100), \
50 DEFINE_RES_IRQ(irq), \
51}
52
53#define R8A73A4_SCIFA(index, baseaddr, irq) \
54 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
55 index, baseaddr, irq)
56
57#define R8A73A4_SCIFB(index, baseaddr, irq) \
58 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
59 index, baseaddr, irq)
60
61R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
62R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
63R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
64R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
65R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
66R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
67
68#define r8a73a4_register_scif(index) \
69 platform_device_register_resndata(NULL, "sh-sci", index, \
70 scif##index##_resources, \
71 ARRAY_SIZE(scif##index##_resources), \
72 &scif##index##_platform_data, \
73 sizeof(scif##index##_platform_data))
74
75static const struct renesas_irqc_config irqc0_data = {
76 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
77};
78
79static const struct resource irqc0_resources[] = {
80 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
81 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
82 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
83 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
84 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
85 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
86 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
87 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
88 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
89 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
90 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
91 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
92 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
93 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
94 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
95 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
96 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
97 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
98 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
99 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
100 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
101 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
102 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
103 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
104 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
105 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
106 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
107 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
108 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
109 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
110 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
111 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
112 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
113};
114
115static const struct renesas_irqc_config irqc1_data = {
116 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
117};
118
119static const struct resource irqc1_resources[] = {
120 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
121 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
122 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
123 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
124 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
125 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
126 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
127 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
128 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
129 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
130 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
131 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
132 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
133 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
134 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
135 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
136 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
137 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
138 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
139 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
140 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
141 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
142 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
143 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
144 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
145 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
146 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
147};
148
149#define r8a73a4_register_irqc(idx) \
150 platform_device_register_resndata(NULL, "renesas_irqc", \
151 idx, irqc##idx##_resources, \
152 ARRAY_SIZE(irqc##idx##_resources), \
153 &irqc##idx##_data, \
154 sizeof(struct renesas_irqc_config))
155
156/* Thermal0 -> Thermal2 */
157static const struct resource thermal0_resources[] = {
158 DEFINE_RES_MEM(0xe61f0000, 0x14),
159 DEFINE_RES_MEM(0xe61f0100, 0x38),
160 DEFINE_RES_MEM(0xe61f0200, 0x38),
161 DEFINE_RES_MEM(0xe61f0300, 0x38),
162 DEFINE_RES_IRQ(gic_spi(69)),
163};
164
165#define r8a73a4_register_thermal() \
166 platform_device_register_simple("rcar_thermal", -1, \
167 thermal0_resources, \
168 ARRAY_SIZE(thermal0_resources))
169
170static struct sh_timer_config cmt1_platform_data = {
171 .channels_mask = 0xff,
172};
173
174static struct resource cmt1_resources[] = {
175 DEFINE_RES_MEM(0xe6130000, 0x1004),
176 DEFINE_RES_IRQ(gic_spi(120)),
177};
178
179#define r8a73a4_register_cmt(idx) \
180 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
181 idx, cmt##idx##_resources, \
182 ARRAY_SIZE(cmt##idx##_resources), \
183 &cmt##idx##_platform_data, \
184 sizeof(struct sh_timer_config))
185
186/* DMA */
187static const struct sh_dmae_slave_config dma_slaves[] = {
188 {
189 .slave_id = SHDMA_SLAVE_MMCIF0_TX,
190 .addr = 0xee200034,
191 .chcr = CHCR_TX(XMIT_SZ_32BIT),
192 .mid_rid = 0xd1,
193 }, {
194 .slave_id = SHDMA_SLAVE_MMCIF0_RX,
195 .addr = 0xee200034,
196 .chcr = CHCR_RX(XMIT_SZ_32BIT),
197 .mid_rid = 0xd2,
198 }, {
199 .slave_id = SHDMA_SLAVE_MMCIF1_TX,
200 .addr = 0xee220034,
201 .chcr = CHCR_TX(XMIT_SZ_32BIT),
202 .mid_rid = 0xe1,
203 }, {
204 .slave_id = SHDMA_SLAVE_MMCIF1_RX,
205 .addr = 0xee220034,
206 .chcr = CHCR_RX(XMIT_SZ_32BIT),
207 .mid_rid = 0xe2,
208 },
209};
210
211#define DMAE_CHANNEL(a, b) \
212 { \
213 .offset = (a) - 0x20, \
214 .dmars = (a) - 0x20 + 0x40, \
215 .chclr_bit = (b), \
216 .chclr_offset = 0x80 - 0x20, \
217 }
218
219static const struct sh_dmae_channel dma_channels[] = {
220 DMAE_CHANNEL(0x8000, 0),
221 DMAE_CHANNEL(0x8080, 1),
222 DMAE_CHANNEL(0x8100, 2),
223 DMAE_CHANNEL(0x8180, 3),
224 DMAE_CHANNEL(0x8200, 4),
225 DMAE_CHANNEL(0x8280, 5),
226 DMAE_CHANNEL(0x8300, 6),
227 DMAE_CHANNEL(0x8380, 7),
228 DMAE_CHANNEL(0x8400, 8),
229 DMAE_CHANNEL(0x8480, 9),
230 DMAE_CHANNEL(0x8500, 10),
231 DMAE_CHANNEL(0x8580, 11),
232 DMAE_CHANNEL(0x8600, 12),
233 DMAE_CHANNEL(0x8680, 13),
234 DMAE_CHANNEL(0x8700, 14),
235 DMAE_CHANNEL(0x8780, 15),
236 DMAE_CHANNEL(0x8800, 16),
237 DMAE_CHANNEL(0x8880, 17),
238 DMAE_CHANNEL(0x8900, 18),
239 DMAE_CHANNEL(0x8980, 19),
240};
241
242static const struct sh_dmae_pdata dma_pdata = {
243 .slave = dma_slaves,
244 .slave_num = ARRAY_SIZE(dma_slaves),
245 .channel = dma_channels,
246 .channel_num = ARRAY_SIZE(dma_channels),
247 .ts_low_shift = TS_LOW_SHIFT,
248 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
249 .ts_high_shift = TS_HI_SHIFT,
250 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
251 .ts_shift = dma_ts_shift,
252 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
253 .dmaor_init = DMAOR_DME,
254 .chclr_present = 1,
255 .chclr_bitwise = 1,
256};
257
258static struct resource dma_resources[] = {
259 DEFINE_RES_MEM(0xe6700020, 0x89e0),
260 DEFINE_RES_IRQ(gic_spi(220)),
261 {
262 /* IRQ for channels 0-19 */
263 .start = gic_spi(200),
264 .end = gic_spi(219),
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
269#define r8a73a4_register_dmac() \
270 platform_device_register_resndata(NULL, "sh-dma-engine", 0, \
271 dma_resources, ARRAY_SIZE(dma_resources), \
272 &dma_pdata, sizeof(dma_pdata))
273
274void __init r8a73a4_add_standard_devices(void)
275{
276 r8a73a4_register_cmt(1);
277 r8a73a4_register_scif(0);
278 r8a73a4_register_scif(1);
279 r8a73a4_register_scif(2);
280 r8a73a4_register_scif(3);
281 r8a73a4_register_scif(4);
282 r8a73a4_register_scif(5);
283 r8a73a4_register_irqc(0);
284 r8a73a4_register_irqc(1);
285 r8a73a4_register_thermal();
286 r8a73a4_register_dmac();
287}
288
289#ifdef CONFIG_USE_OF
290 22
291static const char *r8a73a4_boards_compat_dt[] __initdata = { 23static const char *r8a73a4_boards_compat_dt[] __initdata = {
292 "renesas,r8a73a4", 24 "renesas,r8a73a4",
@@ -298,4 +30,3 @@ DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
298 .init_late = shmobile_init_late, 30 .init_late = shmobile_init_late,
299 .dt_compat = r8a73a4_boards_compat_dt, 31 .dt_compat = r8a73a4_boards_compat_dt,
300MACHINE_END 32MACHINE_END
301#endif /* CONFIG_USE_OF */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 06:29:24 -0500