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authorArnd Bergmann <arnd@arndb.de>2014-11-20 02:30:53 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-20 02:30:53 -0500
commit86dd04a22a9880a9f790473d535f77edee5f621f (patch)
treee105aab1465bddf69a72103b3904ee45507eac2e /arch/arm/mach-shmobile
parent21220a7a32c907d620ab60098c7da5bfdba24c13 (diff)
parent79e69d179cb3391040a3693fca8bc12ec03c05fc (diff)
Merge tag 'renesas-koelsch-board-removal-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Pull "Renesas ARM Based SoC Koelsch Board Removal Updates for v3.19" from Simon Horman: * Remove lecacy C koelsh board support * tag 'renesas-koelsch-board-removal-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: koelsch dts: Drop console= bootargs parameter ARM: dts: koelsch: Stop building r8a7791-koelsch.dtb in legacy builds MAINTAINERS: Remove reference to shmobile / koelsch_defconfig ARM: shmobile: koelsch: Remove reference board code ARM: shmobile: r8a7791: Remove legacy code ARM: shmobile: koelsch: Remove legacy C board code ARM: shmobile: Remove shmobile_clk_workaround() implementation Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/Kconfig19
-rw-r--r--arch/arm/mach-shmobile/Makefile5
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-koelsch-reference.c40
-rw-r--r--arch/arm/mach-shmobile/board-koelsch.c523
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c338
-rw-r--r--arch/arm/mach-shmobile/clock.c32
-rw-r--r--arch/arm/mach-shmobile/clock.h14
-rw-r--r--arch/arm/mach-shmobile/r8a7791.h3
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c181
10 files changed, 5 insertions, 1151 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f59019dd986e..0f2539550f1b 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -72,11 +72,6 @@ config ARCH_R8A7794
72 72
73comment "Renesas ARM SoCs Board Type" 73comment "Renesas ARM SoCs Board Type"
74 74
75config MACH_KOELSCH
76 bool "Koelsch board"
77 depends on ARCH_R8A7791
78 select MICREL_PHY if SH_ETH
79
80config MACH_LAGER 75config MACH_LAGER
81 bool "Lager board" 76 bool "Lager board"
82 depends on ARCH_R8A7790 77 depends on ARCH_R8A7790
@@ -144,14 +139,6 @@ config ARCH_R8A7790
144 select MIGHT_HAVE_PCI 139 select MIGHT_HAVE_PCI
145 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 140 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
146 141
147config ARCH_R8A7791
148 bool "R-Car M2-W (R8A77910)"
149 select ARCH_RCAR_GEN2
150 select ARCH_WANT_OPTIONAL_GPIOLIB
151 select ARM_GIC
152 select MIGHT_HAVE_PCI
153 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
154
155comment "Renesas ARM SoCs Board Type" 142comment "Renesas ARM SoCs Board Type"
156 143
157config MACH_APE6EVM 144config MACH_APE6EVM
@@ -226,12 +213,6 @@ config MACH_LAGER
226 select MICREL_PHY if SH_ETH 213 select MICREL_PHY if SH_ETH
227 select SND_SOC_AK4642 if SND_SIMPLE_CARD 214 select SND_SOC_AK4642 if SND_SIMPLE_CARD
228 215
229config MACH_KOELSCH
230 bool "Koelsch board"
231 depends on ARCH_R8A7791
232 select USE_OF
233 select MICREL_PHY if SH_ETH
234
235config MACH_KZM9G 216config MACH_KZM9G
236 bool "KZM-A9-GT board" 217 bool "KZM-A9-GT board"
237 depends on ARCH_SH73A0 218 depends on ARCH_SH73A0
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e20f2786ec72..7d68eba53be3 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -19,8 +19,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
19obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o 19obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
20 20
21# Clock objects 21# Clock objects
22obj-y += clock.o
23ifndef CONFIG_COMMON_CLK 22ifndef CONFIG_COMMON_CLK
23obj-y += clock.o
24obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o 24obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o
25obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o 25obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
26obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o 26obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
@@ -28,7 +28,6 @@ obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o 30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
31obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
32endif 31endif
33 32
34# CPU reset vector handling objects 33# CPU reset vector handling objects
@@ -57,7 +56,6 @@ obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
57 56
58# Board objects 57# Board objects
59ifdef CONFIG_ARCH_SHMOBILE_MULTI 58ifdef CONFIG_ARCH_SHMOBILE_MULTI
60obj-$(CONFIG_MACH_KOELSCH) += board-koelsch-reference.o
61obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o 59obj-$(CONFIG_MACH_LAGER) += board-lager-reference.o
62obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 60obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
63else 61else
@@ -69,7 +67,6 @@ obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
69obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 67obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
70obj-$(CONFIG_MACH_LAGER) += board-lager.o 68obj-$(CONFIG_MACH_LAGER) += board-lager.o
71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 69obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
72obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o
73obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 70obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
74obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 71obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
75endif 72endif
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index de9a23852fc8..57d00ed6ec0c 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -5,7 +5,6 @@ loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
6loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 6loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 7loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
8loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
9loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 8loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
10loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 9loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
11loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 10loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
deleted file mode 100644
index 451ba624ce6e..000000000000
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * Koelsch board support - Reference DT implementation
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/of_platform.h>
20
21#include <asm/mach/arch.h>
22
23#include "common.h"
24#include "r8a7791.h"
25#include "rcar-gen2.h"
26
27static const char * const koelsch_boards_compat_dt[] __initconst = {
28 "renesas,koelsch",
29 "renesas,koelsch-reference",
30 NULL,
31};
32
33DT_MACHINE_START(KOELSCH_DT, "koelsch")
34 .smp = smp_ops(r8a7791_smp_ops),
35 .init_early = shmobile_init_delay,
36 .init_time = rcar_gen2_timer_init,
37 .init_late = shmobile_init_late,
38 .reserve = rcar_gen2_reserve,
39 .dt_compat = koelsch_boards_compat_dt,
40MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
deleted file mode 100644
index 3a6a2766dc2b..000000000000
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ /dev/null
@@ -1,523 +0,0 @@
1/*
2 * Koelsch board support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
7 * Copyright (C) 2014 Cogent Embedded, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/dma-mapping.h>
20#include <linux/gpio.h>
21#include <linux/gpio_keys.h>
22#include <linux/input.h>
23#include <linux/irq.h>
24#include <linux/kernel.h>
25#include <linux/leds.h>
26#include <linux/mfd/tmio.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/sh_mobile_sdhi.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/partitions.h>
31#include <linux/phy.h>
32#include <linux/pinctrl/machine.h>
33#include <linux/platform_data/gpio-rcar.h>
34#include <linux/platform_data/rcar-du.h>
35#include <linux/platform_device.h>
36#include <linux/regulator/driver.h>
37#include <linux/regulator/fixed.h>
38#include <linux/regulator/gpio-regulator.h>
39#include <linux/regulator/machine.h>
40#include <linux/sh_eth.h>
41#include <linux/spi/flash.h>
42#include <linux/spi/rspi.h>
43#include <linux/spi/spi.h>
44
45#include <asm/mach-types.h>
46#include <asm/mach/arch.h>
47
48#include "common.h"
49#include "irqs.h"
50#include "r8a7791.h"
51#include "rcar-gen2.h"
52
53/* DU */
54static struct rcar_du_encoder_data koelsch_du_encoders[] = {
55 {
56 .type = RCAR_DU_ENCODER_NONE,
57 .output = RCAR_DU_OUTPUT_LVDS0,
58 .connector.lvds.panel = {
59 .width_mm = 210,
60 .height_mm = 158,
61 .mode = {
62 .pixelclock = 65000000,
63 .hactive = 1024,
64 .hfront_porch = 20,
65 .hback_porch = 160,
66 .hsync_len = 136,
67 .vactive = 768,
68 .vfront_porch = 3,
69 .vback_porch = 29,
70 .vsync_len = 6,
71 },
72 },
73 },
74};
75
76static const struct rcar_du_platform_data koelsch_du_pdata __initconst = {
77 .encoders = koelsch_du_encoders,
78 .num_encoders = ARRAY_SIZE(koelsch_du_encoders),
79};
80
81static const struct resource du_resources[] __initconst = {
82 DEFINE_RES_MEM(0xfeb00000, 0x40000),
83 DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
84 DEFINE_RES_IRQ(gic_spi(256)),
85 DEFINE_RES_IRQ(gic_spi(268)),
86};
87
88static void __init koelsch_add_du_device(void)
89{
90 struct platform_device_info info = {
91 .name = "rcar-du-r8a7791",
92 .id = -1,
93 .res = du_resources,
94 .num_res = ARRAY_SIZE(du_resources),
95 .data = &koelsch_du_pdata,
96 .size_data = sizeof(koelsch_du_pdata),
97 .dma_mask = DMA_BIT_MASK(32),
98 };
99
100 platform_device_register_full(&info);
101}
102
103/* Ether */
104static const struct sh_eth_plat_data ether_pdata __initconst = {
105 .phy = 0x1,
106 .phy_irq = irq_pin(0),
107 .edmac_endian = EDMAC_LITTLE_ENDIAN,
108 .phy_interface = PHY_INTERFACE_MODE_RMII,
109 .ether_link_active_low = 1,
110};
111
112static const struct resource ether_resources[] __initconst = {
113 DEFINE_RES_MEM(0xee700000, 0x400),
114 DEFINE_RES_IRQ(gic_spi(162)),
115};
116
117static const struct platform_device_info ether_info __initconst = {
118 .name = "r8a7791-ether",
119 .id = -1,
120 .res = ether_resources,
121 .num_res = ARRAY_SIZE(ether_resources),
122 .data = &ether_pdata,
123 .size_data = sizeof(ether_pdata),
124 .dma_mask = DMA_BIT_MASK(32),
125};
126
127/* LEDS */
128static struct gpio_led koelsch_leds[] = {
129 {
130 .name = "led8",
131 .gpio = RCAR_GP_PIN(2, 21),
132 .default_state = LEDS_GPIO_DEFSTATE_ON,
133 }, {
134 .name = "led7",
135 .gpio = RCAR_GP_PIN(2, 20),
136 .default_state = LEDS_GPIO_DEFSTATE_ON,
137 }, {
138 .name = "led6",
139 .gpio = RCAR_GP_PIN(2, 19),
140 .default_state = LEDS_GPIO_DEFSTATE_ON,
141 },
142};
143
144static const struct gpio_led_platform_data koelsch_leds_pdata __initconst = {
145 .leds = koelsch_leds,
146 .num_leds = ARRAY_SIZE(koelsch_leds),
147};
148
149/* GPIO KEY */
150#define GPIO_KEY(c, g, d, ...) \
151 { .code = c, .gpio = g, .desc = d, .active_low = 1, \
152 .wakeup = 1, .debounce_interval = 20 }
153
154static struct gpio_keys_button gpio_buttons[] = {
155 GPIO_KEY(KEY_4, RCAR_GP_PIN(5, 3), "SW2-pin4"),
156 GPIO_KEY(KEY_3, RCAR_GP_PIN(5, 2), "SW2-pin3"),
157 GPIO_KEY(KEY_2, RCAR_GP_PIN(5, 1), "SW2-pin2"),
158 GPIO_KEY(KEY_1, RCAR_GP_PIN(5, 0), "SW2-pin1"),
159 GPIO_KEY(KEY_G, RCAR_GP_PIN(7, 6), "SW36"),
160 GPIO_KEY(KEY_F, RCAR_GP_PIN(7, 5), "SW35"),
161 GPIO_KEY(KEY_E, RCAR_GP_PIN(7, 4), "SW34"),
162 GPIO_KEY(KEY_D, RCAR_GP_PIN(7, 3), "SW33"),
163 GPIO_KEY(KEY_C, RCAR_GP_PIN(7, 2), "SW32"),
164 GPIO_KEY(KEY_B, RCAR_GP_PIN(7, 1), "SW31"),
165 GPIO_KEY(KEY_A, RCAR_GP_PIN(7, 0), "SW30"),
166};
167
168static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
169 .buttons = gpio_buttons,
170 .nbuttons = ARRAY_SIZE(gpio_buttons),
171};
172
173/* QSPI */
174static const struct resource qspi_resources[] __initconst = {
175 DEFINE_RES_MEM(0xe6b10000, 0x1000),
176 DEFINE_RES_IRQ_NAMED(gic_spi(184), "mux"),
177};
178
179static const struct rspi_plat_data qspi_pdata __initconst = {
180 .num_chipselect = 1,
181};
182
183/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
184static struct mtd_partition spi_flash_part[] = {
185 {
186 .name = "loader",
187 .offset = 0x00000000,
188 .size = 512 * 1024,
189 .mask_flags = MTD_WRITEABLE,
190 },
191 {
192 .name = "bootenv",
193 .offset = MTDPART_OFS_APPEND,
194 .size = 512 * 1024,
195 .mask_flags = MTD_WRITEABLE,
196 },
197 {
198 .name = "data",
199 .offset = MTDPART_OFS_APPEND,
200 .size = MTDPART_SIZ_FULL,
201 },
202};
203
204static const struct flash_platform_data spi_flash_data = {
205 .name = "m25p80",
206 .parts = spi_flash_part,
207 .nr_parts = ARRAY_SIZE(spi_flash_part),
208 .type = "s25fl512s",
209};
210
211static const struct spi_board_info spi_info[] __initconst = {
212 {
213 .modalias = "m25p80",
214 .platform_data = &spi_flash_data,
215 .mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
216 .max_speed_hz = 30000000,
217 .bus_num = 0,
218 .chip_select = 0,
219 },
220};
221
222/* SATA0 */
223static const struct resource sata0_resources[] __initconst = {
224 DEFINE_RES_MEM(0xee300000, 0x2000),
225 DEFINE_RES_IRQ(gic_spi(105)),
226};
227
228static const struct platform_device_info sata0_info __initconst = {
229 .name = "sata-r8a7791",
230 .id = 0,
231 .res = sata0_resources,
232 .num_res = ARRAY_SIZE(sata0_resources),
233 .dma_mask = DMA_BIT_MASK(32),
234};
235
236/* I2C */
237static const struct resource i2c_resources[] __initconst = {
238 /* I2C0 */
239 DEFINE_RES_MEM(0xE6508000, 0x40),
240 DEFINE_RES_IRQ(gic_spi(287)),
241 /* I2C1 */
242 DEFINE_RES_MEM(0xE6518000, 0x40),
243 DEFINE_RES_IRQ(gic_spi(288)),
244 /* I2C2 */
245 DEFINE_RES_MEM(0xE6530000, 0x40),
246 DEFINE_RES_IRQ(gic_spi(286)),
247 /* I2C3 */
248 DEFINE_RES_MEM(0xE6540000, 0x40),
249 DEFINE_RES_IRQ(gic_spi(290)),
250 /* I2C4 */
251 DEFINE_RES_MEM(0xE6520000, 0x40),
252 DEFINE_RES_IRQ(gic_spi(19)),
253 /* I2C5 */
254 DEFINE_RES_MEM(0xE6528000, 0x40),
255 DEFINE_RES_IRQ(gic_spi(20)),
256};
257
258static void __init koelsch_add_i2c(unsigned idx)
259{
260 unsigned res_idx = idx * 2;
261
262 BUG_ON(res_idx >= ARRAY_SIZE(i2c_resources));
263
264 platform_device_register_simple("i2c-rcar_gen2", idx,
265 i2c_resources + res_idx, 2);
266}
267
268#define SDHI_REGULATOR(idx, vdd_pin, vccq_pin) \
269static struct regulator_consumer_supply vcc_sdhi##idx##_consumer = \
270 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi." #idx); \
271 \
272static struct regulator_init_data vcc_sdhi##idx##_init_data = { \
273 .constraints = { \
274 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
275 }, \
276 .consumer_supplies = &vcc_sdhi##idx##_consumer, \
277 .num_consumer_supplies = 1, \
278}; \
279 \
280static const struct fixed_voltage_config vcc_sdhi##idx##_info __initconst = {\
281 .supply_name = "SDHI" #idx "Vcc", \
282 .microvolts = 3300000, \
283 .gpio = vdd_pin, \
284 .enable_high = 1, \
285 .init_data = &vcc_sdhi##idx##_init_data, \
286}; \
287 \
288static struct regulator_consumer_supply vccq_sdhi##idx##_consumer = \
289 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi." #idx); \
290 \
291static struct regulator_init_data vccq_sdhi##idx##_init_data = { \
292 .constraints = { \
293 .input_uV = 3300000, \
294 .min_uV = 1800000, \
295 .max_uV = 3300000, \
296 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | \
297 REGULATOR_CHANGE_STATUS, \
298 }, \
299 .consumer_supplies = &vccq_sdhi##idx##_consumer, \
300 .num_consumer_supplies = 1, \
301}; \
302 \
303static struct gpio vccq_sdhi##idx##_gpio = \
304 { vccq_pin, GPIOF_OUT_INIT_HIGH, "vccq-sdhi" #idx }; \
305 \
306static struct gpio_regulator_state vccq_sdhi##idx##_states[] = { \
307 { .value = 1800000, .gpios = 0 }, \
308 { .value = 3300000, .gpios = 1 }, \
309}; \
310 \
311static const struct gpio_regulator_config vccq_sdhi##idx##_info __initconst = {\
312 .supply_name = "vqmmc", \
313 .gpios = &vccq_sdhi##idx##_gpio, \
314 .nr_gpios = 1, \
315 .states = vccq_sdhi##idx##_states, \
316 .nr_states = ARRAY_SIZE(vccq_sdhi##idx##_states), \
317 .type = REGULATOR_VOLTAGE, \
318 .init_data = &vccq_sdhi##idx##_init_data, \
319};
320
321SDHI_REGULATOR(0, RCAR_GP_PIN(7, 17), RCAR_GP_PIN(2, 12));
322SDHI_REGULATOR(1, RCAR_GP_PIN(7, 18), RCAR_GP_PIN(2, 13));
323SDHI_REGULATOR(2, RCAR_GP_PIN(7, 19), RCAR_GP_PIN(2, 26));
324
325/* SDHI0 */
326static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
327 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
328 MMC_CAP_POWER_OFF_CARD,
329 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
330};
331
332static struct resource sdhi0_resources[] __initdata = {
333 DEFINE_RES_MEM(0xee100000, 0x200),
334 DEFINE_RES_IRQ(gic_spi(165)),
335};
336
337/* SDHI1 */
338static struct sh_mobile_sdhi_info sdhi1_info __initdata = {
339 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
340 MMC_CAP_POWER_OFF_CARD,
341 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
342};
343
344static struct resource sdhi1_resources[] __initdata = {
345 DEFINE_RES_MEM(0xee140000, 0x100),
346 DEFINE_RES_IRQ(gic_spi(167)),
347};
348
349/* SDHI2 */
350static struct sh_mobile_sdhi_info sdhi2_info __initdata = {
351 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
352 MMC_CAP_POWER_OFF_CARD,
353 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
354 TMIO_MMC_WRPROTECT_DISABLE,
355};
356
357static struct resource sdhi2_resources[] __initdata = {
358 DEFINE_RES_MEM(0xee160000, 0x100),
359 DEFINE_RES_IRQ(gic_spi(168)),
360};
361
362static const struct pinctrl_map koelsch_pinctrl_map[] = {
363 /* DU */
364 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
365 "du_rgb666", "du"),
366 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
367 "du_sync", "du"),
368 PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
369 "du_clk_out_0", "du"),
370 /* Ether */
371 PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
372 "eth_link", "eth"),
373 PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
374 "eth_mdio", "eth"),
375 PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
376 "eth_rmii", "eth"),
377 PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
378 "intc_irq0", "intc"),
379 /* QSPI */
380 PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
381 "qspi_ctrl", "qspi"),
382 PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
383 "qspi_data4", "qspi"),
384 /* SCIF0 (CN19: DEBUG SERIAL0) */
385 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
386 "scif0_data_d", "scif0"),
387 /* SCIF1 (CN20: DEBUG SERIAL1) */
388 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7791",
389 "scif1_data_d", "scif1"),
390 /* I2C1 */
391 PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.1", "pfc-r8a7791",
392 "i2c1_e", "i2c1"),
393 /* I2C2 */
394 PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.2", "pfc-r8a7791",
395 "i2c2", "i2c2"),
396 /* I2C4 */
397 PIN_MAP_MUX_GROUP_DEFAULT("i2c-rcar_gen2.4", "pfc-r8a7791",
398 "i2c4_c", "i2c4"),
399 /* SDHI0 */
400 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
401 "sdhi0_data4", "sdhi0"),
402 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
403 "sdhi0_ctrl", "sdhi0"),
404 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
405 "sdhi0_cd", "sdhi0"),
406 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7791",
407 "sdhi0_wp", "sdhi0"),
408 /* SDHI2 */
409 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
410 "sdhi1_data4", "sdhi1"),
411 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
412 "sdhi1_ctrl", "sdhi1"),
413 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
414 "sdhi1_cd", "sdhi1"),
415 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7791",
416 "sdhi1_wp", "sdhi1"),
417 /* SDHI2 */
418 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
419 "sdhi2_data4", "sdhi2"),
420 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
421 "sdhi2_ctrl", "sdhi2"),
422 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-r8a7791",
423 "sdhi2_cd", "sdhi2"),
424};
425
426static void __init koelsch_add_standard_devices(void)
427{
428 r8a7791_clock_init();
429 pinctrl_register_mappings(koelsch_pinctrl_map,
430 ARRAY_SIZE(koelsch_pinctrl_map));
431 r8a7791_pinmux_init();
432 r8a7791_add_standard_devices();
433 platform_device_register_full(&ether_info);
434 platform_device_register_data(NULL, "leds-gpio", -1,
435 &koelsch_leds_pdata,
436 sizeof(koelsch_leds_pdata));
437 platform_device_register_data(NULL, "gpio-keys", -1,
438 &koelsch_keys_pdata,
439 sizeof(koelsch_keys_pdata));
440 platform_device_register_resndata(NULL, "qspi", 0,
441 qspi_resources,
442 ARRAY_SIZE(qspi_resources),
443 &qspi_pdata, sizeof(qspi_pdata));
444 spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
445
446 koelsch_add_du_device();
447
448 platform_device_register_full(&sata0_info);
449
450 koelsch_add_i2c(1);
451 koelsch_add_i2c(2);
452 koelsch_add_i2c(4);
453 koelsch_add_i2c(5);
454
455 platform_device_register_data(NULL, "reg-fixed-voltage", 0,
456 &vcc_sdhi0_info, sizeof(struct fixed_voltage_config));
457 platform_device_register_data(NULL, "reg-fixed-voltage", 1,
458 &vcc_sdhi1_info, sizeof(struct fixed_voltage_config));
459 platform_device_register_data(NULL, "reg-fixed-voltage", 2,
460 &vcc_sdhi2_info, sizeof(struct fixed_voltage_config));
461 platform_device_register_data(NULL, "gpio-regulator", 0,
462 &vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
463 platform_device_register_data(NULL, "gpio-regulator", 1,
464 &vccq_sdhi1_info, sizeof(struct gpio_regulator_config));
465 platform_device_register_data(NULL, "gpio-regulator", 2,
466 &vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
467
468 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 0,
469 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
470 &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
471
472 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 1,
473 sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
474 &sdhi1_info, sizeof(struct sh_mobile_sdhi_info));
475
476 platform_device_register_resndata(NULL, "sh_mobile_sdhi", 2,
477 sdhi2_resources, ARRAY_SIZE(sdhi2_resources),
478 &sdhi2_info, sizeof(struct sh_mobile_sdhi_info));
479
480}
481
482/*
483 * Ether LEDs on the Koelsch board are named LINK and ACTIVE which corresponds
484 * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
485 * 14-15. We have to set them back to 01 from the default 00 value each time
486 * the PHY is reset. It's also important because the PHY's LED0 signal is
487 * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
488 * bounce on and off after each packet, which we apparently want to avoid.
489 */
490static int koelsch_ksz8041_fixup(struct phy_device *phydev)
491{
492 u16 phyctrl1 = phy_read(phydev, 0x1e);
493
494 phyctrl1 &= ~0xc000;
495 phyctrl1 |= 0x4000;
496 return phy_write(phydev, 0x1e, phyctrl1);
497}
498
499static void __init koelsch_init(void)
500{
501 koelsch_add_standard_devices();
502
503 irq_set_irq_type(irq_pin(0), IRQ_TYPE_LEVEL_LOW);
504
505 if (IS_ENABLED(CONFIG_PHYLIB))
506 phy_register_fixup_for_id("r8a7791-ether-ff:01",
507 koelsch_ksz8041_fixup);
508}
509
510static const char * const koelsch_boards_compat_dt[] __initconst = {
511 "renesas,koelsch",
512 NULL,
513};
514
515DT_MACHINE_START(KOELSCH_DT, "koelsch")
516 .smp = smp_ops(r8a7791_smp_ops),
517 .init_early = shmobile_init_delay,
518 .init_time = rcar_gen2_timer_init,
519 .init_machine = koelsch_init,
520 .init_late = shmobile_init_late,
521 .reserve = rcar_gen2_reserve,
522 .dt_compat = koelsch_boards_compat_dt,
523MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
deleted file mode 100644
index 82143ca3bae9..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ /dev/null
@@ -1,338 +0,0 @@
1/*
2 * r8a7791 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/sh_clk.h>
21#include <linux/clkdev.h>
22#include "clock.h"
23#include "common.h"
24#include "rcar-gen2.h"
25
26/*
27 * MD EXTAL PLL0 PLL1 PLL3
28 * 14 13 19 (MHz) *1 *1
29 *---------------------------------------------------
30 * 0 0 0 15 x 1 x172/2 x208/2 x106
31 * 0 0 1 15 x 1 x172/2 x208/2 x88
32 * 0 1 0 20 x 1 x130/2 x156/2 x80
33 * 0 1 1 20 x 1 x130/2 x156/2 x66
34 * 1 0 0 26 / 2 x200/2 x240/2 x122
35 * 1 0 1 26 / 2 x200/2 x240/2 x102
36 * 1 1 0 30 / 2 x172/2 x208/2 x106
37 * 1 1 1 30 / 2 x172/2 x208/2 x88
38 *
39 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
40 * see "p1 / 2" on R8A7791_CLOCK_ROOT() below
41 */
42
43#define CPG_BASE 0xe6150000
44#define CPG_LEN 0x1000
45
46#define SMSTPCR0 0xE6150130
47#define SMSTPCR1 0xE6150134
48#define SMSTPCR2 0xe6150138
49#define SMSTPCR3 0xE615013C
50#define SMSTPCR5 0xE6150144
51#define SMSTPCR7 0xe615014c
52#define SMSTPCR8 0xE6150990
53#define SMSTPCR9 0xE6150994
54#define SMSTPCR10 0xE6150998
55#define SMSTPCR11 0xE615099C
56
57#define MSTPSR1 IOMEM(0xe6150038)
58#define MSTPSR2 IOMEM(0xe6150040)
59#define MSTPSR3 IOMEM(0xe6150048)
60#define MSTPSR5 IOMEM(0xe615003c)
61#define MSTPSR7 IOMEM(0xe61501c4)
62#define MSTPSR8 IOMEM(0xe61509a0)
63#define MSTPSR9 IOMEM(0xe61509a4)
64#define MSTPSR11 IOMEM(0xe61509ac)
65
66#define SDCKCR 0xE6150074
67#define SD1CKCR 0xE6150078
68#define SD2CKCR 0xE615026c
69#define MMC0CKCR 0xE6150240
70#define MMC1CKCR 0xE6150244
71#define SSPCKCR 0xE6150248
72#define SSPRSCKCR 0xE615024C
73
74static struct clk_mapping cpg_mapping = {
75 .phys = CPG_BASE,
76 .len = CPG_LEN,
77};
78
79static struct clk extal_clk = {
80 /* .rate will be updated on r8a7791_clock_init() */
81 .mapping = &cpg_mapping,
82};
83
84static struct sh_clk_ops followparent_clk_ops = {
85 .recalc = followparent_recalc,
86};
87
88static struct clk main_clk = {
89 /* .parent will be set r8a73a4_clock_init */
90 .ops = &followparent_clk_ops,
91};
92
93/*
94 * clock ratio of these clock will be updated
95 * on r8a7791_clock_init()
96 */
97SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
98SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
99SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
100
101/* fixed ratio clock */
102SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
103SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
104
105SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
106SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
107SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
108SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
109SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
110SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
111SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
112SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
113
114static struct clk *main_clks[] = {
115 &extal_clk,
116 &extal_div2_clk,
117 &main_clk,
118 &pll1_clk,
119 &pll1_div2_clk,
120 &pll3_clk,
121 &hp_clk,
122 &p_clk,
123 &qspi_clk,
124 &rclk_clk,
125 &mp_clk,
126 &cp_clk,
127 &zg_clk,
128 &zx_clk,
129 &zs_clk,
130};
131
132/* SDHI (DIV4) clock */
133static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
134
135static struct clk_div_mult_table div4_div_mult_table = {
136 .divisors = divisors,
137 .nr_divisors = ARRAY_SIZE(divisors),
138};
139
140static struct clk_div4_table div4_table = {
141 .div_mult_table = &div4_div_mult_table,
142};
143
144enum {
145 DIV4_SDH, DIV4_SD0,
146 DIV4_NR
147};
148
149static struct clk div4_clks[DIV4_NR] = {
150 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
151 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
152};
153
154/* DIV6 clocks */
155enum {
156 DIV6_SD1, DIV6_SD2,
157 DIV6_NR
158};
159
160static struct clk div6_clks[DIV6_NR] = {
161 [DIV6_SD1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
162 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
163};
164
165/* MSTP */
166enum {
167 MSTP1108, MSTP1107, MSTP1106,
168 MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
169 MSTP917,
170 MSTP815, MSTP814,
171 MSTP813,
172 MSTP811, MSTP810, MSTP809,
173 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
174 MSTP719, MSTP718, MSTP715, MSTP714,
175 MSTP522,
176 MSTP314, MSTP312, MSTP311,
177 MSTP216, MSTP207, MSTP206,
178 MSTP204, MSTP203, MSTP202,
179 MSTP124,
180 MSTP_NR
181};
182
183static struct clk mstp_clks[MSTP_NR] = {
184 [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
185 [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
186 [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
187 [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
188 [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
189 [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
190 [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
191 [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
192 [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
193 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
194 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
195 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
196 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
197 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
198 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
199 [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
200 [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
201 [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
202 [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
203 [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
204 [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
205 [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
206 [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
207 [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
208 [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
209 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
210 [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
211 [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
212 [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
213 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
214 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
215 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
216 [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
217 [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
218 [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
219 [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
220};
221
222static struct clk_lookup lookups[] = {
223
224 /* main clocks */
225 CLKDEV_CON_ID("extal", &extal_clk),
226 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
227 CLKDEV_CON_ID("main", &main_clk),
228 CLKDEV_CON_ID("pll1", &pll1_clk),
229 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
230 CLKDEV_CON_ID("pll3", &pll3_clk),
231 CLKDEV_CON_ID("zg", &zg_clk),
232 CLKDEV_CON_ID("zs", &zs_clk),
233 CLKDEV_CON_ID("hp", &hp_clk),
234 CLKDEV_CON_ID("p", &p_clk),
235 CLKDEV_CON_ID("qspi", &qspi_clk),
236 CLKDEV_CON_ID("rclk", &rclk_clk),
237 CLKDEV_CON_ID("mp", &mp_clk),
238 CLKDEV_CON_ID("cp", &cp_clk),
239 CLKDEV_CON_ID("peripheral_clk", &hp_clk),
240
241 /* MSTP */
242 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
243 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
244 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
245 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
246 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
247 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
248 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
249 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
250 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
251 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
252 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
253 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
254 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
255 CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
256 CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
257 CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1106]), /* SCIFA3 */
258 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1107]), /* SCIFA4 */
259 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1108]), /* SCIFA5 */
260 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
261 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
262 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
263 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
264 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
265 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
266 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
267 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
268 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
269 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
270 CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
271 CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
272 CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
273 CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
274 CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
275 CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
276 CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
277 CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
278};
279
280#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
281 extal_clk.rate = e * 1000 * 1000; \
282 main_clk.parent = m; \
283 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
284 if (mode & MD(19)) \
285 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
286 else \
287 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
288
289
290void __init r8a7791_clock_init(void)
291{
292 u32 mode = rcar_gen2_read_mode_pins();
293 int k, ret = 0;
294
295 switch (mode & (MD(14) | MD(13))) {
296 case 0:
297 R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
298 break;
299 case MD(13):
300 R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
301 break;
302 case MD(14):
303 R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
304 break;
305 case MD(13) | MD(14):
306 R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
307 break;
308 }
309
310 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
311 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
312 else
313 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
314
315 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
316 ret = clk_register(main_clks[k]);
317
318 if (!ret)
319 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
320
321 if (!ret)
322 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
323
324 if (!ret)
325 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
326
327 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
328
329 if (!ret)
330 shmobile_clk_init();
331 else
332 goto epanic;
333
334 return;
335
336epanic:
337 panic("failed to setup r8a7791 clocks\n");
338}
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 1f81ad747153..34f056fc3756 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -15,36 +15,12 @@
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 */ 17 */
18
19#include <linux/export.h>
18#include <linux/kernel.h> 20#include <linux/kernel.h>
19#include <linux/init.h> 21#include <linux/init.h>
20
21#ifdef CONFIG_COMMON_CLK
22#include <linux/clk.h>
23#include <linux/clkdev.h>
24#include "clock.h"
25
26void __init shmobile_clk_workaround(const struct clk_name *clks,
27 int nr_clks, bool enable)
28{
29 const struct clk_name *clkn;
30 struct clk *clk;
31 unsigned int i;
32
33 for (i = 0; i < nr_clks; ++i) {
34 clkn = clks + i;
35 clk = clk_get(NULL, clkn->clk);
36 if (!IS_ERR(clk)) {
37 clk_register_clkdev(clk, clkn->con_id, clkn->dev_id);
38 if (enable)
39 clk_prepare_enable(clk);
40 clk_put(clk);
41 }
42 }
43}
44
45#else /* CONFIG_COMMON_CLK */
46#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
47#include <linux/export.h> 23
48#include "clock.h" 24#include "clock.h"
49#include "common.h" 25#include "common.h"
50 26
@@ -80,5 +56,3 @@ void __clk_put(struct clk *clk)
80{ 56{
81} 57}
82EXPORT_SYMBOL(__clk_put); 58EXPORT_SYMBOL(__clk_put);
83
84#endif /* CONFIG_COMMON_CLK */
diff --git a/arch/arm/mach-shmobile/clock.h b/arch/arm/mach-shmobile/clock.h
index 31b6417463e6..cf3552ea1019 100644
--- a/arch/arm/mach-shmobile/clock.h
+++ b/arch/arm/mach-shmobile/clock.h
@@ -1,19 +1,6 @@
1#ifndef CLOCK_H 1#ifndef CLOCK_H
2#define CLOCK_H 2#define CLOCK_H
3 3
4#ifdef CONFIG_COMMON_CLK
5/* temporary clock configuration helper for platform devices */
6
7struct clk_name {
8 const char *clk;
9 const char *con_id;
10 const char *dev_id;
11};
12
13void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks,
14 bool enable);
15
16#else /* CONFIG_COMMON_CLK */
17/* legacy clock implementation */ 4/* legacy clock implementation */
18 5
19struct clk; 6struct clk;
@@ -52,5 +39,4 @@ do { \
52 (p)->div = d; \ 39 (p)->div = d; \
53} while (0) 40} while (0)
54 41
55#endif /* CONFIG_COMMON_CLK */
56#endif 42#endif
diff --git a/arch/arm/mach-shmobile/r8a7791.h b/arch/arm/mach-shmobile/r8a7791.h
index c1bf7abefa5a..6cf11eb69d10 100644
--- a/arch/arm/mach-shmobile/r8a7791.h
+++ b/arch/arm/mach-shmobile/r8a7791.h
@@ -1,9 +1,6 @@
1#ifndef __ASM_R8A7791_H__ 1#ifndef __ASM_R8A7791_H__
2#define __ASM_R8A7791_H__ 2#define __ASM_R8A7791_H__
3 3
4void r8a7791_add_standard_devices(void);
5void r8a7791_clock_init(void);
6void r8a7791_pinmux_init(void);
7void r8a7791_pm_init(void); 4void r8a7791_pm_init(void);
8extern struct smp_operations r8a7791_smp_ops; 5extern struct smp_operations r8a7791_smp_ops;
9 6
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d930925f8f1a..ef8eb3af586d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -15,192 +15,14 @@
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 */ 16 */
17 17
18#include <linux/irq.h> 18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/of_platform.h>
21#include <linux/platform_data/gpio-rcar.h>
22#include <linux/platform_data/irq-renesas-irqc.h>
23#include <linux/serial_sci.h>
24#include <linux/sh_timer.h>
25 19
26#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
27 21
28#include "common.h" 22#include "common.h"
29#include "irqs.h"
30#include "r8a7791.h" 23#include "r8a7791.h"
31#include "rcar-gen2.h" 24#include "rcar-gen2.h"
32 25
33static const struct resource pfc_resources[] __initconst = {
34 DEFINE_RES_MEM(0xe6060000, 0x250),
35};
36
37#define r8a7791_register_pfc() \
38 platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
39 ARRAY_SIZE(pfc_resources))
40
41#define R8A7791_GPIO(idx, base, nr) \
42static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
43 DEFINE_RES_MEM((base), 0x50), \
44 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
45}; \
46 \
47static const struct gpio_rcar_config \
48r8a7791_gpio##idx##_platform_data __initconst = { \
49 .gpio_base = 32 * (idx), \
50 .irq_base = 0, \
51 .number_of_pins = (nr), \
52 .pctl_name = "pfc-r8a7791", \
53 .has_both_edge_trigger = 1, \
54}; \
55
56R8A7791_GPIO(0, 0xe6050000, 32);
57R8A7791_GPIO(1, 0xe6051000, 32);
58R8A7791_GPIO(2, 0xe6052000, 32);
59R8A7791_GPIO(3, 0xe6053000, 32);
60R8A7791_GPIO(4, 0xe6054000, 32);
61R8A7791_GPIO(5, 0xe6055000, 32);
62R8A7791_GPIO(6, 0xe6055400, 32);
63R8A7791_GPIO(7, 0xe6055800, 26);
64
65#define r8a7791_register_gpio(idx) \
66 platform_device_register_resndata(NULL, "gpio_rcar", idx, \
67 r8a7791_gpio##idx##_resources, \
68 ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
69 &r8a7791_gpio##idx##_platform_data, \
70 sizeof(r8a7791_gpio##idx##_platform_data))
71
72void __init r8a7791_pinmux_init(void)
73{
74 r8a7791_register_pfc();
75 r8a7791_register_gpio(0);
76 r8a7791_register_gpio(1);
77 r8a7791_register_gpio(2);
78 r8a7791_register_gpio(3);
79 r8a7791_register_gpio(4);
80 r8a7791_register_gpio(5);
81 r8a7791_register_gpio(6);
82 r8a7791_register_gpio(7);
83}
84
85#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
86static struct plat_sci_port scif##index##_platform_data = { \
87 .type = scif_type, \
88 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
89 .scscr = SCSCR_RE | SCSCR_TE, \
90}; \
91 \
92static struct resource scif##index##_resources[] = { \
93 DEFINE_RES_MEM(baseaddr, 0x100), \
94 DEFINE_RES_IRQ(irq), \
95}
96
97#define R8A7791_SCIF(index, baseaddr, irq) \
98 __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
99
100#define R8A7791_SCIFA(index, baseaddr, irq) \
101 __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
102
103#define R8A7791_SCIFB(index, baseaddr, irq) \
104 __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
105
106R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
107R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
108R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
109R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
110R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
111R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
112R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
113R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
114R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
115R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
116R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
117R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
118R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
119R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
120R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
121
122#define r8a7791_register_scif(index) \
123 platform_device_register_resndata(NULL, "sh-sci", index, \
124 scif##index##_resources, \
125 ARRAY_SIZE(scif##index##_resources), \
126 &scif##index##_platform_data, \
127 sizeof(scif##index##_platform_data))
128
129static struct sh_timer_config cmt0_platform_data = {
130 .channels_mask = 0x60,
131};
132
133static struct resource cmt0_resources[] = {
134 DEFINE_RES_MEM(0xffca0000, 0x1004),
135 DEFINE_RES_IRQ(gic_spi(142)),
136};
137
138#define r8a7791_register_cmt(idx) \
139 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
140 idx, cmt##idx##_resources, \
141 ARRAY_SIZE(cmt##idx##_resources), \
142 &cmt##idx##_platform_data, \
143 sizeof(struct sh_timer_config))
144
145static struct renesas_irqc_config irqc0_data = {
146 .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
147};
148
149static struct resource irqc0_resources[] = {
150 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
151 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
152 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
153 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
154 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
155 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
156 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
157 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
158 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
159 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
160 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
161};
162
163#define r8a7791_register_irqc(idx) \
164 platform_device_register_resndata(NULL, "renesas_irqc", \
165 idx, irqc##idx##_resources, \
166 ARRAY_SIZE(irqc##idx##_resources), \
167 &irqc##idx##_data, \
168 sizeof(struct renesas_irqc_config))
169
170static const struct resource thermal_resources[] __initconst = {
171 DEFINE_RES_MEM(0xe61f0000, 0x14),
172 DEFINE_RES_MEM(0xe61f0100, 0x38),
173 DEFINE_RES_IRQ(gic_spi(69)),
174};
175
176#define r8a7791_register_thermal() \
177 platform_device_register_simple("rcar_thermal", -1, \
178 thermal_resources, \
179 ARRAY_SIZE(thermal_resources))
180
181void __init r8a7791_add_standard_devices(void)
182{
183 r8a7791_register_scif(0);
184 r8a7791_register_scif(1);
185 r8a7791_register_scif(2);
186 r8a7791_register_scif(3);
187 r8a7791_register_scif(4);
188 r8a7791_register_scif(5);
189 r8a7791_register_scif(6);
190 r8a7791_register_scif(7);
191 r8a7791_register_scif(8);
192 r8a7791_register_scif(9);
193 r8a7791_register_scif(10);
194 r8a7791_register_scif(11);
195 r8a7791_register_scif(12);
196 r8a7791_register_scif(13);
197 r8a7791_register_scif(14);
198 r8a7791_register_cmt(0);
199 r8a7791_register_irqc(0);
200 r8a7791_register_thermal();
201}
202
203#ifdef CONFIG_USE_OF
204static const char *r8a7791_boards_compat_dt[] __initdata = { 26static const char *r8a7791_boards_compat_dt[] __initdata = {
205 "renesas,r8a7791", 27 "renesas,r8a7791",
206 NULL, 28 NULL,
@@ -214,4 +36,3 @@ DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
214 .reserve = rcar_gen2_reserve, 36 .reserve = rcar_gen2_reserve,
215 .dt_compat = r8a7791_boards_compat_dt, 37 .dt_compat = r8a7791_boards_compat_dt,
216MACHINE_END 38MACHINE_END
217#endif /* CONFIG_USE_OF */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 06:41:28 -0500