Merge branch 'renesas-sh73a0' into renesas-kzm9g

* renesas-sh73a0:
  ARM: shmobile: use common DMAEngine definitions on sh73a0
  ARM: shmobile: sh73a0: add DMAEngine support for MPDMAC
  ARM: shmobile: sh73a0: add USB clock support
  ARM: shmobile: add common DMAEngine definitions
  ARM: shmobile: add common extra gpio functions

5 files changed, 247 insertions, 36 deletions

diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index ad6f9ade7402..37ba0140b427 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -475,9 +475,9 @@ static struct clk *late_main_clks[] = {
 
 enum { MSTP001,
         MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
-        MSTP219, MSTP218,
+        MSTP219, MSTP218, MSTP217,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-        MSTP331, MSTP329, MSTP328, MSTP325, MSTP323,
+        MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
         MSTP314, MSTP313, MSTP312, MSTP311,
         MSTP303, MSTP302, MSTP301, MSTP300,
         MSTP411, MSTP410, MSTP403,
@@ -498,6 +498,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
+        [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
         [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
         [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
         [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
@@ -510,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/
         [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
         [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */
         [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
@@ -554,6 +556,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
+        CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
@@ -566,6 +569,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/include/mach/dma-register.h
new file mode 100644
index 000000000000..97c40bd9b94f
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/dma-register.h
@@ -0,0 +1,84 @@
+/*
+ * SH-ARM CPU-specific DMA definitions, used by both DMA drivers
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp
+ *
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DMA_REGISTER_H
+#define DMA_REGISTER_H
+
+/*
+ *              Direct Memory Access Controller
+ */
+
+/* Transmit sizes and respective CHCR register values */
+enum {
+        XMIT_SZ_8BIT            = 0,
+        XMIT_SZ_16BIT           = 1,
+        XMIT_SZ_32BIT           = 2,
+        XMIT_SZ_64BIT           = 7,
+        XMIT_SZ_128BIT          = 3,
+        XMIT_SZ_256BIT          = 4,
+        XMIT_SZ_512BIT          = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+static const unsigned int dma_ts_shift[] = {
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_64BIT]         = 3,
+        [XMIT_SZ_128BIT]        = 4,
+        [XMIT_SZ_256BIT]        = 5,
+        [XMIT_SZ_512BIT]        = 6,
+};
+
+#define TS_LOW_BIT      0x3 /* --xx */
+#define TS_HI_BIT       0xc /* xx-- */
+
+#define TS_LOW_SHIFT    (3)
+#define TS_HI_SHIFT     (20 - 2)        /* 2 bits for shifted low TS */
+
+#define TS_INDEX2VAL(i) \
+        ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
+         (((i) & TS_HI_BIT)  << TS_HI_SHIFT))
+
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+
+
+/*
+ *              USB High-Speed DMAC
+ */
+/* Transmit sizes and respective CHCR register values */
+enum {
+        USBTS_XMIT_SZ_8BYTE             = 0,
+        USBTS_XMIT_SZ_16BYTE            = 1,
+        USBTS_XMIT_SZ_32BYTE            = 2,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+static const unsigned int dma_usbts_shift[] = {
+        [USBTS_XMIT_SZ_8BYTE]   = 3,
+        [USBTS_XMIT_SZ_16BYTE]  = 4,
+        [USBTS_XMIT_SZ_32BYTE]  = 5,
+};
+
+#define USBTS_LOW_BIT   0x3 /* --xx */
+#define USBTS_HI_BIT    0x0 /* ---- */
+
+#define USBTS_LOW_SHIFT 6
+#define USBTS_HI_SHIFT  0
+
+#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
+
+#endif /* DMA_REGISTER_H */
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index de795b42232a..844507d937cb 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/sh_pfc.h>
+#include <linux/io.h>
 
 #ifdef CONFIG_GPIOLIB
 
@@ -27,4 +28,35 @@ static inline int irq_to_gpio(unsigned int irq)
 
 #endif /* CONFIG_GPIOLIB */
 
+/*
+ * FIXME !!
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static inline void __init gpio_direction_none(u32 addr)
+{
+        __raw_writeb(0x00, addr);
+}
+
+static inline void __init gpio_request_pullup(u32 addr)
+{
+        u8 data = __raw_readb(addr);
+
+        data &= 0x0F;
+        data |= 0xC0;
+        __raw_writeb(data, addr);
+}
+
+static inline void __init gpio_request_pulldown(u32 addr)
+{
+        u8 data = __raw_readb(addr);
+
+        data &= 0x0F;
+        data |= 0xA0;
+
+        __raw_writeb(data, addr);
+}
+
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 398e2c10913b..fe950f25d793 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -516,6 +516,13 @@ enum {
         SHDMA_SLAVE_SDHI2_RX,
         SHDMA_SLAVE_MMCIF_TX,
         SHDMA_SLAVE_MMCIF_RX,
+        SHDMA_SLAVE_FSI2A_TX,
+        SHDMA_SLAVE_FSI2A_RX,
+        SHDMA_SLAVE_FSI2B_TX,
+        SHDMA_SLAVE_FSI2B_RX,
+        SHDMA_SLAVE_FSI2C_TX,
+        SHDMA_SLAVE_FSI2C_RX,
+        SHDMA_SLAVE_FSI2D_RX,
 };
 
 /*
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 04a0dfe75493..d230af656fc9 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -30,6 +30,7 @@
 #include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/sh73a0.h>
@@ -415,32 +416,6 @@ static struct platform_device i2c4_device = {
         .num_resources  = ARRAY_SIZE(i2c4_resources),
 };
 
-/* Transmit sizes and respective CHCR register values */
-enum {
-        XMIT_SZ_8BIT            = 0,
-        XMIT_SZ_16BIT           = 1,
-        XMIT_SZ_32BIT           = 2,
-        XMIT_SZ_64BIT           = 7,
-        XMIT_SZ_128BIT          = 3,
-        XMIT_SZ_256BIT          = 4,
-        XMIT_SZ_512BIT          = 5,
-};
-
-/* log2(size / 8) - used to calculate number of transfers */
-#define TS_SHIFT {                      \
-        [XMIT_SZ_8BIT]          = 0,    \
-        [XMIT_SZ_16BIT]         = 1,    \
-        [XMIT_SZ_32BIT]         = 2,    \
-        [XMIT_SZ_64BIT]         = 3,    \
-        [XMIT_SZ_128BIT]        = 4,    \
-        [XMIT_SZ_256BIT]        = 5,    \
-        [XMIT_SZ_512BIT]        = 6,    \
-}
-
-#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
-#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
-#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
-
 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
         {
                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
@@ -604,19 +579,17 @@ static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
         DMAE_CHANNEL(0x8980),
 };
 
-static const unsigned int ts_shift[] = TS_SHIFT;
-
 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
         .slave          = sh73a0_dmae_slaves,
         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
         .channel        = sh73a0_dmae_channels,
         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
-        .ts_low_shift   = 3,
-        .ts_low_mask    = 0x18,
-        .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
-        .ts_high_mask   = 0x00300000,
-        .ts_shift       = ts_shift,
-        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
         .dmaor_init     = DMAOR_DME,
 };
 
@@ -651,6 +624,116 @@ static struct platform_device dma0_device = {
         },
 };
 
+/* MPDMAC */
+static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_FSI2A_RX,
+                .addr           = 0xec230020,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd6, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2A_TX,
+                .addr           = 0xec230024,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd5, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2C_RX,
+                .addr           = 0xec230060,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xda, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2C_TX,
+                .addr           = 0xec230064,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd9, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2B_RX,
+                .addr           = 0xec240020,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x8e, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2B_TX,
+                .addr           = 0xec240024,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x8d, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2D_RX,
+                .addr           =  0xec240060,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x9a, /* CHECK ME */
+        },
+};
+
+#define MPDMA_CHANNEL(a, b, c)                  \
+{                                               \
+        .offset         = a,                    \
+        .dmars          = b,                    \
+        .dmars_bit      = c,                    \
+        .chclr_offset   = (0x220 - 0x20) + a    \
+}
+
+static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
+        MPDMA_CHANNEL(0x00, 0, 0),
+        MPDMA_CHANNEL(0x10, 0, 8),
+        MPDMA_CHANNEL(0x20, 4, 0),
+        MPDMA_CHANNEL(0x30, 4, 8),
+        MPDMA_CHANNEL(0x50, 8, 0),
+        MPDMA_CHANNEL(0x70, 8, 8),
+};
+
+static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
+        .slave          = sh73a0_mpdma_slaves,
+        .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
+        .channel        = sh73a0_mpdma_channels,
+        .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chclr_present  = 1,
+};
+
+/* Resource order important! */
+static struct resource sh73a0_mpdma_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xec618020,
+                .end    = 0xec61828f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xec619000,
+                .end    = 0xec61900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "error_irq",
+                .start  = gic_spi(181),
+                .end    = gic_spi(181),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = gic_spi(175),
+                .end    = gic_spi(180),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mpdma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh73a0_mpdma_resources,
+        .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
+        .dev            = {
+                .platform_data  = &sh73a0_mpdma_platform_data,
+        },
+};
+
 static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -673,6 +756,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &i2c3_device,
         &i2c4_device,
         &dma0_device,
+        &mpdma0_device,
 };
 
 #define SRCR2          0xe61580b0