diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2013-08-02 02:39:56 -0400 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2013-08-06 05:07:13 -0400 |
commit | 5b3859d7b2c10419e1cc7ce6c456995e757f4390 (patch) | |
tree | bc7589d62d1ca916fc80c2c94fef0bde6ed2776d /arch/arm/mach-shmobile/setup-r8a7779.c | |
parent | 70e3f3d4f40fe5ecdb351acf33db06df077fb0c1 (diff) |
ARM: shmobile: r8a7779: move r8a7779_init_irq_xxx() to setup
This patch moves r8a7779_init_irq_xxx() to setup code,
and remove intc-r8a7779.
Now, r8a7779_init_irq_extpin() uses
platform_device_register_resndata() instead of
platform_device_register()
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/setup-r8a7779.c')
-rw-r--r-- | arch/arm/mach-shmobile/setup-r8a7779.c | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index f0b6c7dea2f0..6a9933395434 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c | |||
@@ -22,8 +22,11 @@ | |||
22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
25 | #include <linux/irqchip.h> | ||
26 | #include <linux/irqchip/arm-gic.h> | ||
25 | #include <linux/of_platform.h> | 27 | #include <linux/of_platform.h> |
26 | #include <linux/platform_data/gpio-rcar.h> | 28 | #include <linux/platform_data/gpio-rcar.h> |
29 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> | ||
27 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
28 | #include <linux/delay.h> | 31 | #include <linux/delay.h> |
29 | #include <linux/input.h> | 32 | #include <linux/input.h> |
@@ -67,6 +70,60 @@ void __init r8a7779_map_io(void) | |||
67 | iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); | 70 | iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); |
68 | } | 71 | } |
69 | 72 | ||
73 | /* IRQ */ | ||
74 | #define INT2SMSKCR0 IOMEM(0xfe7822a0) | ||
75 | #define INT2SMSKCR1 IOMEM(0xfe7822a4) | ||
76 | #define INT2SMSKCR2 IOMEM(0xfe7822a8) | ||
77 | #define INT2SMSKCR3 IOMEM(0xfe7822ac) | ||
78 | #define INT2SMSKCR4 IOMEM(0xfe7822b0) | ||
79 | |||
80 | #define INT2NTSR0 IOMEM(0xfe700060) | ||
81 | #define INT2NTSR1 IOMEM(0xfe700064) | ||
82 | |||
83 | static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { | ||
84 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ | ||
85 | .sense_bitfield_width = 2, | ||
86 | }; | ||
87 | |||
88 | static struct resource irqpin0_resources[] __initdata = { | ||
89 | DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ | ||
90 | DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ | ||
91 | DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ | ||
92 | DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ | ||
93 | DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ | ||
94 | DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ | ||
95 | DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ | ||
96 | DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ | ||
97 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ | ||
98 | }; | ||
99 | |||
100 | void __init r8a7779_init_irq_extpin(int irlm) | ||
101 | { | ||
102 | void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); | ||
103 | u32 tmp; | ||
104 | |||
105 | if (!icr0) { | ||
106 | pr_warn("r8a7779: unable to setup external irq pin mode\n"); | ||
107 | return; | ||
108 | } | ||
109 | |||
110 | tmp = ioread32(icr0); | ||
111 | if (irlm) | ||
112 | tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ | ||
113 | else | ||
114 | tmp &= ~(1 << 23); /* IRL mode - not supported */ | ||
115 | tmp |= (1 << 21); /* LVLMODE = 1 */ | ||
116 | iowrite32(tmp, icr0); | ||
117 | iounmap(icr0); | ||
118 | |||
119 | if (irlm) | ||
120 | platform_device_register_resndata( | ||
121 | &platform_bus, "renesas_intc_irqpin", -1, | ||
122 | irqpin0_resources, ARRAY_SIZE(irqpin0_resources), | ||
123 | &irqpin0_platform_data, sizeof(irqpin0_platform_data)); | ||
124 | } | ||
125 | |||
126 | /* PFC/GPIO */ | ||
70 | static struct resource r8a7779_pfc_resources[] = { | 127 | static struct resource r8a7779_pfc_resources[] = { |
71 | DEFINE_RES_MEM(0xfffc0000, 0x023c), | 128 | DEFINE_RES_MEM(0xfffc0000, 0x023c), |
72 | }; | 129 | }; |
@@ -641,6 +698,29 @@ void __init r8a7779_init_late(void) | |||
641 | } | 698 | } |
642 | 699 | ||
643 | #ifdef CONFIG_USE_OF | 700 | #ifdef CONFIG_USE_OF |
701 | static int r8a7779_set_wake(struct irq_data *data, unsigned int on) | ||
702 | { | ||
703 | return 0; /* always allow wakeup */ | ||
704 | } | ||
705 | |||
706 | void __init r8a7779_init_irq_dt(void) | ||
707 | { | ||
708 | gic_arch_extn.irq_set_wake = r8a7779_set_wake; | ||
709 | |||
710 | irqchip_init(); | ||
711 | |||
712 | /* route all interrupts to ARM */ | ||
713 | __raw_writel(0xffffffff, INT2NTSR0); | ||
714 | __raw_writel(0x3fffffff, INT2NTSR1); | ||
715 | |||
716 | /* unmask all known interrupts in INTCS2 */ | ||
717 | __raw_writel(0xfffffff0, INT2SMSKCR0); | ||
718 | __raw_writel(0xfff7ffff, INT2SMSKCR1); | ||
719 | __raw_writel(0xfffbffdf, INT2SMSKCR2); | ||
720 | __raw_writel(0xbffffffc, INT2SMSKCR3); | ||
721 | __raw_writel(0x003fee3f, INT2SMSKCR4); | ||
722 | } | ||
723 | |||
644 | void __init r8a7779_init_delay(void) | 724 | void __init r8a7779_init_delay(void) |
645 | { | 725 | { |
646 | shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ | 726 | shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ |