diff options
author | Magnus Damm <damm@opensource.se> | 2014-01-15 02:43:08 -0500 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2014-02-23 18:55:46 -0500 |
commit | a6557eb795edcf7832b5278a11842c4ca302f4af (patch) | |
tree | f46f65b333815c8fe013575496bb229b57161668 /arch/arm/mach-shmobile/pm-r8a7779.c | |
parent | 4a51856b42672cfcb7d6fbab22dcf2caba2be5ab (diff) |
ARM: shmobile: Break out R-Car SYSC PM code
Break out the R-Car SYSC power management code from
the r8a7779 SoC code. With this new shared R-Car SYSC
code base it is possible to hook in Generation 2 SoCs
as well.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile/pm-r8a7779.c')
-rw-r--r-- | arch/arm/mach-shmobile/pm-r8a7779.c | 131 |
1 files changed, 7 insertions, 124 deletions
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c index d50a8e9b94a4..d6fe189b2df6 100644 --- a/arch/arm/mach-shmobile/pm-r8a7779.c +++ b/arch/arm/mach-shmobile/pm-r8a7779.c | |||
@@ -20,132 +20,22 @@ | |||
20 | #include <linux/console.h> | 20 | #include <linux/console.h> |
21 | #include <asm/io.h> | 21 | #include <asm/io.h> |
22 | #include <mach/common.h> | 22 | #include <mach/common.h> |
23 | #include <mach/pm-rcar.h> | ||
23 | #include <mach/r8a7779.h> | 24 | #include <mach/r8a7779.h> |
24 | 25 | ||
25 | static void __iomem *r8a7779_sysc_base; | ||
26 | |||
27 | /* SYSC */ | 26 | /* SYSC */ |
28 | #define SYSCSR 0x00 | ||
29 | #define SYSCISR 0x04 | ||
30 | #define SYSCISCR 0x08 | ||
31 | #define SYSCIER 0x0c | 27 | #define SYSCIER 0x0c |
32 | #define SYSCIMR 0x10 | 28 | #define SYSCIMR 0x10 |
33 | #define PWRSR0 0x40 | ||
34 | #define PWRSR1 0x80 | ||
35 | #define PWRSR2 0xc0 | ||
36 | #define PWRSR3 0x100 | ||
37 | #define PWRSR4 0x140 | ||
38 | |||
39 | #define PWRSR_OFFS 0x00 | ||
40 | #define PWROFFCR_OFFS 0x04 | ||
41 | #define PWRONCR_OFFS 0x0c | ||
42 | #define PWRER_OFFS 0x14 | ||
43 | |||
44 | #define SYSCSR_RETRIES 100 | ||
45 | #define SYSCSR_DELAY_US 1 | ||
46 | |||
47 | #define SYSCISR_RETRIES 1000 | ||
48 | #define SYSCISR_DELAY_US 1 | ||
49 | 29 | ||
50 | #if defined(CONFIG_PM) || defined(CONFIG_SMP) | 30 | #if defined(CONFIG_PM) || defined(CONFIG_SMP) |
51 | 31 | ||
52 | static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */ | ||
53 | |||
54 | static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch, | ||
55 | int sr_bit, int reg_offs) | ||
56 | { | ||
57 | int k; | ||
58 | |||
59 | for (k = 0; k < SYSCSR_RETRIES; k++) { | ||
60 | if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit)) | ||
61 | break; | ||
62 | udelay(SYSCSR_DELAY_US); | ||
63 | } | ||
64 | |||
65 | if (k == SYSCSR_RETRIES) | ||
66 | return -EAGAIN; | ||
67 | |||
68 | iowrite32(1 << r8a7779_ch->chan_bit, | ||
69 | r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs); | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | |||
74 | static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch) | ||
75 | { | ||
76 | return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS); | ||
77 | } | ||
78 | |||
79 | static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch) | ||
80 | { | ||
81 | return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS); | ||
82 | } | ||
83 | |||
84 | static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch, | ||
85 | int (*on_off_fn)(struct r8a7779_pm_ch *)) | ||
86 | { | ||
87 | unsigned int isr_mask = 1 << r8a7779_ch->isr_bit; | ||
88 | unsigned int chan_mask = 1 << r8a7779_ch->chan_bit; | ||
89 | unsigned int status; | ||
90 | unsigned long flags; | ||
91 | int ret = 0; | ||
92 | int k; | ||
93 | |||
94 | spin_lock_irqsave(&r8a7779_sysc_lock, flags); | ||
95 | |||
96 | iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); | ||
97 | |||
98 | do { | ||
99 | ret = on_off_fn(r8a7779_ch); | ||
100 | if (ret) | ||
101 | goto out; | ||
102 | |||
103 | status = ioread32(r8a7779_sysc_base + | ||
104 | r8a7779_ch->chan_offs + PWRER_OFFS); | ||
105 | } while (status & chan_mask); | ||
106 | |||
107 | for (k = 0; k < SYSCISR_RETRIES; k++) { | ||
108 | if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask) | ||
109 | break; | ||
110 | udelay(SYSCISR_DELAY_US); | ||
111 | } | ||
112 | |||
113 | if (k == SYSCISR_RETRIES) | ||
114 | ret = -EIO; | ||
115 | |||
116 | iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR); | ||
117 | |||
118 | out: | ||
119 | spin_unlock_irqrestore(&r8a7779_sysc_lock, flags); | ||
120 | |||
121 | pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n", | ||
122 | r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0), | ||
123 | ioread32(r8a7779_sysc_base + PWRSR1), | ||
124 | ioread32(r8a7779_sysc_base + PWRSR2), | ||
125 | ioread32(r8a7779_sysc_base + PWRSR3), | ||
126 | ioread32(r8a7779_sysc_base + PWRSR4), ret); | ||
127 | return ret; | ||
128 | } | ||
129 | |||
130 | int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch) | ||
131 | { | ||
132 | return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off); | ||
133 | } | ||
134 | |||
135 | int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch) | ||
136 | { | ||
137 | return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on); | ||
138 | } | ||
139 | |||
140 | static void __init r8a7779_sysc_init(void) | 32 | static void __init r8a7779_sysc_init(void) |
141 | { | 33 | { |
142 | r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE); | 34 | void __iomem *base = rcar_sysc_init(0xffd85000); |
143 | if (!r8a7779_sysc_base) | ||
144 | panic("unable to ioremap r8a7779 SYSC hardware block\n"); | ||
145 | 35 | ||
146 | /* enable all interrupt sources, but do not use interrupt handler */ | 36 | /* enable all interrupt sources, but do not use interrupt handler */ |
147 | iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER); | 37 | iowrite32(0x0131000e, base + SYSCIER); |
148 | iowrite32(0, r8a7779_sysc_base + SYSCIMR); | 38 | iowrite32(0, base + SYSCIMR); |
149 | } | 39 | } |
150 | 40 | ||
151 | #else /* CONFIG_PM || CONFIG_SMP */ | 41 | #else /* CONFIG_PM || CONFIG_SMP */ |
@@ -158,24 +48,17 @@ static inline void r8a7779_sysc_init(void) {} | |||
158 | 48 | ||
159 | static int pd_power_down(struct generic_pm_domain *genpd) | 49 | static int pd_power_down(struct generic_pm_domain *genpd) |
160 | { | 50 | { |
161 | return r8a7779_sysc_power_down(to_r8a7779_ch(genpd)); | 51 | return rcar_sysc_power_down(to_r8a7779_ch(genpd)); |
162 | } | 52 | } |
163 | 53 | ||
164 | static int pd_power_up(struct generic_pm_domain *genpd) | 54 | static int pd_power_up(struct generic_pm_domain *genpd) |
165 | { | 55 | { |
166 | return r8a7779_sysc_power_up(to_r8a7779_ch(genpd)); | 56 | return rcar_sysc_power_up(to_r8a7779_ch(genpd)); |
167 | } | 57 | } |
168 | 58 | ||
169 | static bool pd_is_off(struct generic_pm_domain *genpd) | 59 | static bool pd_is_off(struct generic_pm_domain *genpd) |
170 | { | 60 | { |
171 | struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd); | 61 | return rcar_sysc_power_is_off(to_r8a7779_ch(genpd)); |
172 | unsigned int st; | ||
173 | |||
174 | st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS); | ||
175 | if (st & (1 << r8a7779_ch->chan_bit)) | ||
176 | return true; | ||
177 | |||
178 | return false; | ||
179 | } | 62 | } |
180 | 63 | ||
181 | static bool pd_active_wakeup(struct device *dev) | 64 | static bool pd_active_wakeup(struct device *dev) |