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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-21 18:27:22 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-21 18:27:22 -0500 |
commit | bab588fcfb6335c767d811a8955979f5440328e0 (patch) | |
tree | 2a862ddf47a82be885a8e7945a17cc3ff7a658b9 /arch/arm/mach-shmobile/headsmp.S | |
parent | 3298a3511f1e73255a8dc023efd909e569eea037 (diff) | |
parent | 9cb0d1babfcb1b4ac248c09425f7d5de1e771133 (diff) |
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
Diffstat (limited to 'arch/arm/mach-shmobile/headsmp.S')
-rw-r--r-- | arch/arm/mach-shmobile/headsmp.S | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index b202c1272526..96001fd49b6c 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S | |||
@@ -16,54 +16,6 @@ | |||
16 | 16 | ||
17 | __CPUINIT | 17 | __CPUINIT |
18 | 18 | ||
19 | /* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! | ||
20 | * | ||
21 | * The secondary kernel init calls v7_flush_dcache_all before it enables | ||
22 | * the L1; however, the L1 comes out of reset in an undefined state, so | ||
23 | * the clean + invalidate performed by v7_flush_dcache_all causes a bunch | ||
24 | * of cache lines with uninitialized data and uninitialized tags to get | ||
25 | * written out to memory, which does really unpleasant things to the main | ||
26 | * processor. We fix this by performing an invalidate, rather than a | ||
27 | * clean + invalidate, before jumping into the kernel. | ||
28 | * | ||
29 | * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs | ||
30 | * to be called for both secondary cores startup and primary core resume | ||
31 | * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. | ||
32 | */ | ||
33 | ENTRY(v7_invalidate_l1) | ||
34 | mov r0, #0 | ||
35 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
36 | mcr p15, 2, r0, c0, c0, 0 | ||
37 | mrc p15, 1, r0, c0, c0, 0 | ||
38 | |||
39 | ldr r1, =0x7fff | ||
40 | and r2, r1, r0, lsr #13 | ||
41 | |||
42 | ldr r1, =0x3ff | ||
43 | |||
44 | and r3, r1, r0, lsr #3 @ NumWays - 1 | ||
45 | add r2, r2, #1 @ NumSets | ||
46 | |||
47 | and r0, r0, #0x7 | ||
48 | add r0, r0, #4 @ SetShift | ||
49 | |||
50 | clz r1, r3 @ WayShift | ||
51 | add r4, r3, #1 @ NumWays | ||
52 | 1: sub r2, r2, #1 @ NumSets-- | ||
53 | mov r3, r4 @ Temp = NumWays | ||
54 | 2: subs r3, r3, #1 @ Temp-- | ||
55 | mov r5, r3, lsl r1 | ||
56 | mov r6, r2, lsl r0 | ||
57 | orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) | ||
58 | mcr p15, 0, r5, c7, c6, 2 | ||
59 | bgt 2b | ||
60 | cmp r2, #0 | ||
61 | bgt 1b | ||
62 | dsb | ||
63 | isb | ||
64 | mov pc, lr | ||
65 | ENDPROC(v7_invalidate_l1) | ||
66 | |||
67 | ENTRY(shmobile_invalidate_start) | 19 | ENTRY(shmobile_invalidate_start) |
68 | bl v7_invalidate_l1 | 20 | bl v7_invalidate_l1 |
69 | b secondary_startup | 21 | b secondary_startup |