Merge tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2

From Simon Horman <horms+renesas@verge.net.au>:

Renesas ARM r8a7779 SoC update for v3.10

Update to the r8a7779 SoC:
* Add SH Ethernet support
* Add comment describing clock ratios

This pull request is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10

* tag 'renesas-soc-r8a7779-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: R8A7779: add Ether support
  ARM: shmobile: r8a7779: add each clocks ratio on comment area

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 22 insertions, 1 deletions

diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 7d86bfbb5b06..31d5cd4d9787 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -26,6 +26,25 @@
 #include <mach/clock.h>
 #include <mach/common.h>
 
+/*
+ *              MD1 = 1                 MD1 = 0
+ *              (PLLA = 1500)           (PLLA = 1600)
+ *              (MHz)                   (MHz)
+ *------------------------------------------------+--------------------
+ * clkz         1000   (2/3)            800   (1/2)
+ * clkzs         250   (1/6)            200   (1/8)
+ * clki          750   (1/2)            800   (1/2)
+ * clks          250   (1/6)            200   (1/8)
+ * clks1         125   (1/12)           100   (1/16)
+ * clks3         187.5 (1/8)            200   (1/8)
+ * clks4          93.7 (1/16)           100   (1/16)
+ * clkp           62.5 (1/24)            50   (1/32)
+ * clkg           62.5 (1/24)            66.6 (1/24)
+ * clkb, CLKOUT
+ * (MD2 = 0)      62.5 (1/24)            66.6 (1/24)
+ * (MD2 = 1)      41.6 (1/36)            50   (1/32)
+*/
+
 #define MD(nr)  BIT(nr)
 
 #define FRQMR           IOMEM(0xffc80014)
@@ -93,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP115,
+        MSTP115, MSTP114,
         MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -107,6 +126,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
         [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
+        [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
         [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
         [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  1, 0), /* USB2 */
         [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  0, 0), /* USB0/1 */
@@ -143,6 +163,7 @@ static struct clk_lookup lookups[] = {
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
         CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
+        CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
         CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
         CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
         CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */