ARM: mach-shmobile: sh73a0 INTCS support

Add INTCS support for the sh73a0 processor.

The interrupts on the sh73a0 processor are managed
through controllers such as GIC, INTCS and INTCA.

The ARM cores use the GIC as primary interrupt
controller and the INTCS and INTCA are hanging off
the GIC as cascaded interrupt controllers.

Peripherals connected both to the GIC and the INTC
controllers should if possible only use the GIC.

If no GIC connection is available then INTCS and
INTCA may be used instead.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 2 insertions, 3 deletions

diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index d4c82bd42524..85f9269d83ca 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -179,12 +179,11 @@ static void __init ag5evm_map_io(void)
 
 void __init ag5evm_init_irq(void)
 {
+        sh73a0_init_irq();
+
         /* setup PINT: enable PINTA2 as active low */
         __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
         __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
-
-        gic_dist_init(0, __io(0xf0001000), 29);
-        gic_cpu_init(0, __io(0xf0000100));
 }
 
 static void __init ag5evm_init(void)