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authorBjorn Helgaas <bhelgaas@google.com>2011-10-28 18:26:16 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2012-01-06 15:10:56 -0500
commit37d15909ff6bf6e97e1d4447efa7f1a19e7a508e (patch)
tree03d1be5fc753995295a6812e4bed485be73d2512 /arch/arm/mach-sa1100/pci-nanoengine.c
parenta2f33da11ab9efba25d41e959de6338a9078fb36 (diff)
arm/PCI: convert to pci_scan_root_bus() for correct root bus resources
Convert from pci_scan_bus() to pci_scan_root_bus() and remove root bus resource fixups. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. CC: Russell King <linux@arm.linux.org.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'arch/arm/mach-sa1100/pci-nanoengine.c')
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index dd39fee59549..0d01ca788922 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -131,7 +131,8 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
131 131
132struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) 132struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
133{ 133{
134 return pci_scan_bus(sys->busnr, &pci_nano_ops, sys); 134 return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys,
135 &sys->resources);
135} 136}
136 137
137static struct resource pci_io_ports = { 138static struct resource pci_io_ports = {
@@ -226,7 +227,7 @@ static struct resource pci_prefetchable_memory = {
226 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, 227 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
227}; 228};
228 229
229static int __init pci_nanoengine_setup_resources(struct resource **resource) 230static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
230{ 231{
231 if (request_resource(&ioport_resource, &pci_io_ports)) { 232 if (request_resource(&ioport_resource, &pci_io_ports)) {
232 printk(KERN_ERR "PCI: unable to allocate io port region\n"); 233 printk(KERN_ERR "PCI: unable to allocate io port region\n");
@@ -243,9 +244,9 @@ static int __init pci_nanoengine_setup_resources(struct resource **resource)
243 printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); 244 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
244 return -EBUSY; 245 return -EBUSY;
245 } 246 }
246 resource[0] = &pci_io_ports; 247 pci_add_resource(&sys->resources, &pci_io_ports);
247 resource[1] = &pci_non_prefetchable_memory; 248 pci_add_resource(&sys->resources, &pci_non_prefetchable_memory);
248 resource[2] = &pci_prefetchable_memory; 249 pci_add_resource(&sys->resources, &pci_prefetchable_memory);
249 250
250 return 1; 251 return 1;
251} 252}
@@ -260,7 +261,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
260 if (nr == 0) { 261 if (nr == 0) {
261 sys->mem_offset = NANO_PCI_MEM_RW_PHYS; 262 sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
262 sys->io_offset = 0x400; 263 sys->io_offset = 0x400;
263 ret = pci_nanoengine_setup_resources(sys->resource); 264 ret = pci_nanoengine_setup_resources(sys);
264 /* Enable alternate memory bus master mode, see 265 /* Enable alternate memory bus master mode, see
265 * "Intel StrongARM SA1110 Developer's Manual", 266 * "Intel StrongARM SA1110 Developer's Manual",
266 * section 10.8, "Alternate Memory Bus Master Mode". */ 267 * section 10.8, "Alternate Memory Bus Master Mode". */