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authorDmitry Eremin-Solenikov <dbaryshkov@gmail.com>2015-01-14 20:29:16 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-01-29 10:24:46 -0500
commit83508093f448e929bf55d07dd08246d22b03d753 (patch)
tree60a1ecb382a012bb5626b556f7c2aa848f7038d0 /arch/arm/mach-sa1100/include/mach
parent7a8ca0a0c480fedf91bdbadf8b90edd5374ce18b (diff)
ARM: 8278/1: sa1100: split irq handling for low GPIOs
Low GPIO pins use an interrupt in SC interrupts space. However it's possible to handle them as if all the GPIO interrupts are instead tied to single GPIO handler, which later decodes GEDR register and chain-calls next IRQ handler. So split first 11 interrupts into system part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of system controller interrupts and real GPIO interrupts (IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then decodes and calls next handler. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach')
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h73
1 files changed, 42 insertions, 31 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index de0983494c7e..734e30e406a3 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -8,17 +8,17 @@
8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. 8 * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs.
9 */ 9 */
10 10
11#define IRQ_GPIO0 1 11#define IRQ_GPIO0_SC 1
12#define IRQ_GPIO1 2 12#define IRQ_GPIO1_SC 2
13#define IRQ_GPIO2 3 13#define IRQ_GPIO2_SC 3
14#define IRQ_GPIO3 4 14#define IRQ_GPIO3_SC 4
15#define IRQ_GPIO4 5 15#define IRQ_GPIO4_SC 5
16#define IRQ_GPIO5 6 16#define IRQ_GPIO5_SC 6
17#define IRQ_GPIO6 7 17#define IRQ_GPIO6_SC 7
18#define IRQ_GPIO7 8 18#define IRQ_GPIO7_SC 8
19#define IRQ_GPIO8 9 19#define IRQ_GPIO8_SC 9
20#define IRQ_GPIO9 10 20#define IRQ_GPIO9_SC 10
21#define IRQ_GPIO10 11 21#define IRQ_GPIO10_SC 11
22#define IRQ_GPIO11_27 12 22#define IRQ_GPIO11_27 12
23#define IRQ_LCD 13 /* LCD controller */ 23#define IRQ_LCD 13 /* LCD controller */
24#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */ 24#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */
@@ -41,32 +41,43 @@
41#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */ 41#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */
42#define IRQ_RTCAlrm 32 /* RTC Alarm */ 42#define IRQ_RTCAlrm 32 /* RTC Alarm */
43 43
44#define IRQ_GPIO11 33 44#define IRQ_GPIO0 33
45#define IRQ_GPIO12 34 45#define IRQ_GPIO1 34
46#define IRQ_GPIO13 35 46#define IRQ_GPIO2 35
47#define IRQ_GPIO14 36 47#define IRQ_GPIO3 36
48#define IRQ_GPIO15 37 48#define IRQ_GPIO4 37
49#define IRQ_GPIO16 38 49#define IRQ_GPIO5 38
50#define IRQ_GPIO17 39 50#define IRQ_GPIO6 39
51#define IRQ_GPIO18 40 51#define IRQ_GPIO7 40
52#define IRQ_GPIO19 41 52#define IRQ_GPIO8 41
53#define IRQ_GPIO20 42 53#define IRQ_GPIO9 42
54#define IRQ_GPIO21 43 54#define IRQ_GPIO10 43
55#define IRQ_GPIO22 44 55#define IRQ_GPIO11 44
56#define IRQ_GPIO23 45 56#define IRQ_GPIO12 45
57#define IRQ_GPIO24 46 57#define IRQ_GPIO13 46
58#define IRQ_GPIO25 47 58#define IRQ_GPIO14 47
59#define IRQ_GPIO26 48 59#define IRQ_GPIO15 48
60#define IRQ_GPIO27 49 60#define IRQ_GPIO16 49
61#define IRQ_GPIO17 50
62#define IRQ_GPIO18 51
63#define IRQ_GPIO19 52
64#define IRQ_GPIO20 53
65#define IRQ_GPIO21 54
66#define IRQ_GPIO22 55
67#define IRQ_GPIO23 56
68#define IRQ_GPIO24 57
69#define IRQ_GPIO25 58
70#define IRQ_GPIO26 59
71#define IRQ_GPIO27 60
61 72
62/* 73/*
63 * The next 16 interrupts are for board specific purposes. Since 74 * The next 16 interrupts are for board specific purposes. Since
64 * the kernel can only run on one machine at a time, we can re-use 75 * the kernel can only run on one machine at a time, we can re-use
65 * these. If you need more, increase IRQ_BOARD_END, but keep it 76 * these. If you need more, increase IRQ_BOARD_END, but keep it
66 * within sensible limits. IRQs 49 to 64 are available. 77 * within sensible limits. IRQs 61 to 76 are available.
67 */ 78 */
68#define IRQ_BOARD_START 50 79#define IRQ_BOARD_START 61
69#define IRQ_BOARD_END 66 80#define IRQ_BOARD_END 77
70 81
71/* 82/*
72 * Figure out the MAX IRQ number. 83 * Figure out the MAX IRQ number.