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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-25 15:38:42 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-25 15:38:42 -0400
commitae4c42e4e4d76d003f8ca551fe1aef93ff9a4b21 (patch)
tree2bff2e4f4456077e7d7c589c8c28824f12dfa21c /arch/arm/mach-s5pv210
parentdd58ecba48edf14be1a5f70120fcd3002277a74a (diff)
parentab2a0e0d135490729e384c1826d118f92e88cae8 (diff)
Merge branch 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (133 commits) ARM: EXYNOS4: Change devname for FIMD clkdev ARM: S3C64XX: Cleanup mach/regs-fb.h from mach-s3c64xx ARM: S5PV210: Cleanup mach/regs-fb.h from mach-s5pv210 ARM: S5PC100: Cleanup mach/regs-fb.h from mach-s5pc100 ARM: S3C24XX: Use generic s3c_set_platdata for devices ARM: S3C64XX: Use generic s3c_set_platdata for OneNAND ARM: SAMSUNG: Use generic s3c_set_platdata for NAND ARM: SAMSUNG: Use generic s3c_set_platdata for USB OHCI ARM: SAMSUNG: Use generic s3c_set_platdata for HWMON ARM: SAMSUNG: Use generic s3c_set_platdata for FB ARM: SAMSUNG: Use generic s3c_set_platdata for TS ARM: S3C64XX: Add PWM backlight support on SMDK6410 ARM: S5P64X0: Add PWM backlight support on SMDK6450 ARM: S5P64X0: Add PWM backlight support on SMDK6440 ARM: S5PC100: Add PWM backlight support on SMDKC100 ARM: S5PV210: Add PWM backlight support on SMDKV210 ARM: EXYNOS4: Add PWM backlight support on SMDKC210 ARM: EXYNOS4: Add PWM backlight support on SMDKV310 ARM: SAMSUNG: Create a common infrastructure for PWM backlight support clocksource: convert 32-bit down counting clocksource on S5PV210/S5P64X0 ... Fix up trivial conflict in arch/arm/mach-imx/mach-scb9328.c
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r--arch/arm/mach-s5pv210/Kconfig1
-rw-r--r--arch/arm/mach-s5pv210/clock.c167
-rw-r--r--arch/arm/mach-s5pv210/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-fb.h21
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c2
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c2
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c56
-rw-r--r--arch/arm/mach-s5pv210/setup-fb-24bpp.c1
8 files changed, 65 insertions, 192 deletions
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 37b5a97594a5..79bb3a0314ef 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -134,6 +134,7 @@ config MACH_SMDKV210
134 select S3C_DEV_RTC 134 select S3C_DEV_RTC
135 select S3C_DEV_WDT 135 select S3C_DEV_WDT
136 select SAMSUNG_DEV_ADC 136 select SAMSUNG_DEV_ADC
137 select SAMSUNG_DEV_BACKLIGHT
137 select SAMSUNG_DEV_IDE 138 select SAMSUNG_DEV_IDE
138 select SAMSUNG_DEV_KEYPAD 139 select SAMSUNG_DEV_KEYPAD
139 select SAMSUNG_DEV_PWM 140 select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d599499cefe..ae72f87eab15 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
36static struct clksrc_clk clk_mout_apll = { 36static struct clksrc_clk clk_mout_apll = {
37 .clk = { 37 .clk = {
38 .name = "mout_apll", 38 .name = "mout_apll",
39 .id = -1,
40 }, 39 },
41 .sources = &clk_src_apll, 40 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
45static struct clksrc_clk clk_mout_epll = { 44static struct clksrc_clk clk_mout_epll = {
46 .clk = { 45 .clk = {
47 .name = "mout_epll", 46 .name = "mout_epll",
48 .id = -1,
49 }, 47 },
50 .sources = &clk_src_epll, 48 .sources = &clk_src_epll,
51 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, 49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
54static struct clksrc_clk clk_mout_mpll = { 52static struct clksrc_clk clk_mout_mpll = {
55 .clk = { 53 .clk = {
56 .name = "mout_mpll", 54 .name = "mout_mpll",
57 .id = -1,
58 }, 55 },
59 .sources = &clk_src_mpll, 56 .sources = &clk_src_mpll,
60 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
73static struct clksrc_clk clk_armclk = { 70static struct clksrc_clk clk_armclk = {
74 .clk = { 71 .clk = {
75 .name = "armclk", 72 .name = "armclk",
76 .id = -1,
77 }, 73 },
78 .sources = &clkset_armclk, 74 .sources = &clkset_armclk,
79 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, 75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
83static struct clksrc_clk clk_hclk_msys = { 79static struct clksrc_clk clk_hclk_msys = {
84 .clk = { 80 .clk = {
85 .name = "hclk_msys", 81 .name = "hclk_msys",
86 .id = -1,
87 .parent = &clk_armclk.clk, 82 .parent = &clk_armclk.clk,
88 }, 83 },
89 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
92static struct clksrc_clk clk_pclk_msys = { 87static struct clksrc_clk clk_pclk_msys = {
93 .clk = { 88 .clk = {
94 .name = "pclk_msys", 89 .name = "pclk_msys",
95 .id = -1,
96 .parent = &clk_hclk_msys.clk, 90 .parent = &clk_hclk_msys.clk,
97 }, 91 },
98 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
101static struct clksrc_clk clk_sclk_a2m = { 95static struct clksrc_clk clk_sclk_a2m = {
102 .clk = { 96 .clk = {
103 .name = "sclk_a2m", 97 .name = "sclk_a2m",
104 .id = -1,
105 .parent = &clk_mout_apll.clk, 98 .parent = &clk_mout_apll.clk,
106 }, 99 },
107 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
120static struct clksrc_clk clk_hclk_dsys = { 113static struct clksrc_clk clk_hclk_dsys = {
121 .clk = { 114 .clk = {
122 .name = "hclk_dsys", 115 .name = "hclk_dsys",
123 .id = -1,
124 }, 116 },
125 .sources = &clkset_hclk_sys, 117 .sources = &clkset_hclk_sys,
126 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, 118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
130static struct clksrc_clk clk_pclk_dsys = { 122static struct clksrc_clk clk_pclk_dsys = {
131 .clk = { 123 .clk = {
132 .name = "pclk_dsys", 124 .name = "pclk_dsys",
133 .id = -1,
134 .parent = &clk_hclk_dsys.clk, 125 .parent = &clk_hclk_dsys.clk,
135 }, 126 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
139static struct clksrc_clk clk_hclk_psys = { 130static struct clksrc_clk clk_hclk_psys = {
140 .clk = { 131 .clk = {
141 .name = "hclk_psys", 132 .name = "hclk_psys",
142 .id = -1,
143 }, 133 },
144 .sources = &clkset_hclk_sys, 134 .sources = &clkset_hclk_sys,
145 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, 135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
149static struct clksrc_clk clk_pclk_psys = { 139static struct clksrc_clk clk_pclk_psys = {
150 .clk = { 140 .clk = {
151 .name = "pclk_psys", 141 .name = "pclk_psys",
152 .id = -1,
153 .parent = &clk_hclk_psys.clk, 142 .parent = &clk_hclk_psys.clk,
154 }, 143 },
155 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187 176
188static struct clk clk_sclk_hdmi27m = { 177static struct clk clk_sclk_hdmi27m = {
189 .name = "sclk_hdmi27m", 178 .name = "sclk_hdmi27m",
190 .id = -1,
191 .rate = 27000000, 179 .rate = 27000000,
192}; 180};
193 181
194static struct clk clk_sclk_hdmiphy = { 182static struct clk clk_sclk_hdmiphy = {
195 .name = "sclk_hdmiphy", 183 .name = "sclk_hdmiphy",
196 .id = -1,
197}; 184};
198 185
199static struct clk clk_sclk_usbphy0 = { 186static struct clk clk_sclk_usbphy0 = {
200 .name = "sclk_usbphy0", 187 .name = "sclk_usbphy0",
201 .id = -1,
202}; 188};
203 189
204static struct clk clk_sclk_usbphy1 = { 190static struct clk clk_sclk_usbphy1 = {
205 .name = "sclk_usbphy1", 191 .name = "sclk_usbphy1",
206 .id = -1,
207}; 192};
208 193
209static struct clk clk_pcmcdclk0 = { 194static struct clk clk_pcmcdclk0 = {
210 .name = "pcmcdclk", 195 .name = "pcmcdclk",
211 .id = -1,
212}; 196};
213 197
214static struct clk clk_pcmcdclk1 = { 198static struct clk clk_pcmcdclk1 = {
215 .name = "pcmcdclk", 199 .name = "pcmcdclk",
216 .id = -1,
217}; 200};
218 201
219static struct clk clk_pcmcdclk2 = { 202static struct clk clk_pcmcdclk2 = {
220 .name = "pcmcdclk", 203 .name = "pcmcdclk",
221 .id = -1,
222}; 204};
223 205
224static struct clk *clkset_vpllsrc_list[] = { 206static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
234static struct clksrc_clk clk_vpllsrc = { 216static struct clksrc_clk clk_vpllsrc = {
235 .clk = { 217 .clk = {
236 .name = "vpll_src", 218 .name = "vpll_src",
237 .id = -1,
238 .enable = s5pv210_clk_mask0_ctrl, 219 .enable = s5pv210_clk_mask0_ctrl,
239 .ctrlbit = (1 << 7), 220 .ctrlbit = (1 << 7),
240 }, 221 },
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
255static struct clksrc_clk clk_sclk_vpll = { 236static struct clksrc_clk clk_sclk_vpll = {
256 .clk = { 237 .clk = {
257 .name = "sclk_vpll", 238 .name = "sclk_vpll",
258 .id = -1,
259 }, 239 },
260 .sources = &clkset_sclk_vpll, 240 .sources = &clkset_sclk_vpll,
261 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, 241 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
276static struct clksrc_clk clk_mout_dmc0 = { 256static struct clksrc_clk clk_mout_dmc0 = {
277 .clk = { 257 .clk = {
278 .name = "mout_dmc0", 258 .name = "mout_dmc0",
279 .id = -1,
280 }, 259 },
281 .sources = &clkset_moutdmc0src, 260 .sources = &clkset_moutdmc0src,
282 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 261 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
285static struct clksrc_clk clk_sclk_dmc0 = { 264static struct clksrc_clk clk_sclk_dmc0 = {
286 .clk = { 265 .clk = {
287 .name = "sclk_dmc0", 266 .name = "sclk_dmc0",
288 .id = -1,
289 .parent = &clk_mout_dmc0.clk, 267 .parent = &clk_mout_dmc0.clk,
290 }, 268 },
291 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, 269 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = {
312static struct clk init_clocks_off[] = { 290static struct clk init_clocks_off[] = {
313 { 291 {
314 .name = "pdma", 292 .name = "pdma",
315 .id = 0, 293 .devname = "s3c-pl330.0",
316 .parent = &clk_hclk_psys.clk, 294 .parent = &clk_hclk_psys.clk,
317 .enable = s5pv210_clk_ip0_ctrl, 295 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 3), 296 .ctrlbit = (1 << 3),
319 }, { 297 }, {
320 .name = "pdma", 298 .name = "pdma",
321 .id = 1, 299 .devname = "s3c-pl330.1",
322 .parent = &clk_hclk_psys.clk, 300 .parent = &clk_hclk_psys.clk,
323 .enable = s5pv210_clk_ip0_ctrl, 301 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 4), 302 .ctrlbit = (1 << 4),
325 }, { 303 }, {
326 .name = "rot", 304 .name = "rot",
327 .id = -1,
328 .parent = &clk_hclk_dsys.clk, 305 .parent = &clk_hclk_dsys.clk,
329 .enable = s5pv210_clk_ip0_ctrl, 306 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1<<29), 307 .ctrlbit = (1<<29),
331 }, { 308 }, {
332 .name = "fimc", 309 .name = "fimc",
333 .id = 0, 310 .devname = "s5pv210-fimc.0",
334 .parent = &clk_hclk_dsys.clk, 311 .parent = &clk_hclk_dsys.clk,
335 .enable = s5pv210_clk_ip0_ctrl, 312 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 24), 313 .ctrlbit = (1 << 24),
337 }, { 314 }, {
338 .name = "fimc", 315 .name = "fimc",
339 .id = 1, 316 .devname = "s5pv210-fimc.1",
340 .parent = &clk_hclk_dsys.clk, 317 .parent = &clk_hclk_dsys.clk,
341 .enable = s5pv210_clk_ip0_ctrl, 318 .enable = s5pv210_clk_ip0_ctrl,
342 .ctrlbit = (1 << 25), 319 .ctrlbit = (1 << 25),
343 }, { 320 }, {
344 .name = "fimc", 321 .name = "fimc",
345 .id = 2, 322 .devname = "s5pv210-fimc.2",
346 .parent = &clk_hclk_dsys.clk, 323 .parent = &clk_hclk_dsys.clk,
347 .enable = s5pv210_clk_ip0_ctrl, 324 .enable = s5pv210_clk_ip0_ctrl,
348 .ctrlbit = (1 << 26), 325 .ctrlbit = (1 << 26),
349 }, { 326 }, {
350 .name = "otg", 327 .name = "otg",
351 .id = -1,
352 .parent = &clk_hclk_psys.clk, 328 .parent = &clk_hclk_psys.clk,
353 .enable = s5pv210_clk_ip1_ctrl, 329 .enable = s5pv210_clk_ip1_ctrl,
354 .ctrlbit = (1<<16), 330 .ctrlbit = (1<<16),
355 }, { 331 }, {
356 .name = "usb-host", 332 .name = "usb-host",
357 .id = -1,
358 .parent = &clk_hclk_psys.clk, 333 .parent = &clk_hclk_psys.clk,
359 .enable = s5pv210_clk_ip1_ctrl, 334 .enable = s5pv210_clk_ip1_ctrl,
360 .ctrlbit = (1<<17), 335 .ctrlbit = (1<<17),
361 }, { 336 }, {
362 .name = "lcd", 337 .name = "lcd",
363 .id = -1,
364 .parent = &clk_hclk_dsys.clk, 338 .parent = &clk_hclk_dsys.clk,
365 .enable = s5pv210_clk_ip1_ctrl, 339 .enable = s5pv210_clk_ip1_ctrl,
366 .ctrlbit = (1<<0), 340 .ctrlbit = (1<<0),
367 }, { 341 }, {
368 .name = "cfcon", 342 .name = "cfcon",
369 .id = 0,
370 .parent = &clk_hclk_psys.clk, 343 .parent = &clk_hclk_psys.clk,
371 .enable = s5pv210_clk_ip1_ctrl, 344 .enable = s5pv210_clk_ip1_ctrl,
372 .ctrlbit = (1<<25), 345 .ctrlbit = (1<<25),
373 }, { 346 }, {
374 .name = "hsmmc", 347 .name = "hsmmc",
375 .id = 0, 348 .devname = "s3c-sdhci.0",
376 .parent = &clk_hclk_psys.clk, 349 .parent = &clk_hclk_psys.clk,
377 .enable = s5pv210_clk_ip2_ctrl, 350 .enable = s5pv210_clk_ip2_ctrl,
378 .ctrlbit = (1<<16), 351 .ctrlbit = (1<<16),
379 }, { 352 }, {
380 .name = "hsmmc", 353 .name = "hsmmc",
381 .id = 1, 354 .devname = "s3c-sdhci.1",
382 .parent = &clk_hclk_psys.clk, 355 .parent = &clk_hclk_psys.clk,
383 .enable = s5pv210_clk_ip2_ctrl, 356 .enable = s5pv210_clk_ip2_ctrl,
384 .ctrlbit = (1<<17), 357 .ctrlbit = (1<<17),
385 }, { 358 }, {
386 .name = "hsmmc", 359 .name = "hsmmc",
387 .id = 2, 360 .devname = "s3c-sdhci.2",
388 .parent = &clk_hclk_psys.clk, 361 .parent = &clk_hclk_psys.clk,
389 .enable = s5pv210_clk_ip2_ctrl, 362 .enable = s5pv210_clk_ip2_ctrl,
390 .ctrlbit = (1<<18), 363 .ctrlbit = (1<<18),
391 }, { 364 }, {
392 .name = "hsmmc", 365 .name = "hsmmc",
393 .id = 3, 366 .devname = "s3c-sdhci.3",
394 .parent = &clk_hclk_psys.clk, 367 .parent = &clk_hclk_psys.clk,
395 .enable = s5pv210_clk_ip2_ctrl, 368 .enable = s5pv210_clk_ip2_ctrl,
396 .ctrlbit = (1<<19), 369 .ctrlbit = (1<<19),
397 }, { 370 }, {
398 .name = "systimer", 371 .name = "systimer",
399 .id = -1,
400 .parent = &clk_pclk_psys.clk, 372 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl, 373 .enable = s5pv210_clk_ip3_ctrl,
402 .ctrlbit = (1<<16), 374 .ctrlbit = (1<<16),
403 }, { 375 }, {
404 .name = "watchdog", 376 .name = "watchdog",
405 .id = -1,
406 .parent = &clk_pclk_psys.clk, 377 .parent = &clk_pclk_psys.clk,
407 .enable = s5pv210_clk_ip3_ctrl, 378 .enable = s5pv210_clk_ip3_ctrl,
408 .ctrlbit = (1<<22), 379 .ctrlbit = (1<<22),
409 }, { 380 }, {
410 .name = "rtc", 381 .name = "rtc",
411 .id = -1,
412 .parent = &clk_pclk_psys.clk, 382 .parent = &clk_pclk_psys.clk,
413 .enable = s5pv210_clk_ip3_ctrl, 383 .enable = s5pv210_clk_ip3_ctrl,
414 .ctrlbit = (1<<15), 384 .ctrlbit = (1<<15),
415 }, { 385 }, {
416 .name = "i2c", 386 .name = "i2c",
417 .id = 0, 387 .devname = "s3c2440-i2c.0",
418 .parent = &clk_pclk_psys.clk, 388 .parent = &clk_pclk_psys.clk,
419 .enable = s5pv210_clk_ip3_ctrl, 389 .enable = s5pv210_clk_ip3_ctrl,
420 .ctrlbit = (1<<7), 390 .ctrlbit = (1<<7),
421 }, { 391 }, {
422 .name = "i2c", 392 .name = "i2c",
423 .id = 1, 393 .devname = "s3c2440-i2c.1",
424 .parent = &clk_pclk_psys.clk, 394 .parent = &clk_pclk_psys.clk,
425 .enable = s5pv210_clk_ip3_ctrl, 395 .enable = s5pv210_clk_ip3_ctrl,
426 .ctrlbit = (1 << 10), 396 .ctrlbit = (1 << 10),
427 }, { 397 }, {
428 .name = "i2c", 398 .name = "i2c",
429 .id = 2, 399 .devname = "s3c2440-i2c.2",
430 .parent = &clk_pclk_psys.clk, 400 .parent = &clk_pclk_psys.clk,
431 .enable = s5pv210_clk_ip3_ctrl, 401 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<9), 402 .ctrlbit = (1<<9),
433 }, { 403 }, {
434 .name = "spi", 404 .name = "spi",
435 .id = 0, 405 .devname = "s3c64xx-spi.0",
436 .parent = &clk_pclk_psys.clk, 406 .parent = &clk_pclk_psys.clk,
437 .enable = s5pv210_clk_ip3_ctrl, 407 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<12), 408 .ctrlbit = (1<<12),
439 }, { 409 }, {
440 .name = "spi", 410 .name = "spi",
441 .id = 1, 411 .devname = "s3c64xx-spi.1",
442 .parent = &clk_pclk_psys.clk, 412 .parent = &clk_pclk_psys.clk,
443 .enable = s5pv210_clk_ip3_ctrl, 413 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<13), 414 .ctrlbit = (1<<13),
445 }, { 415 }, {
446 .name = "spi", 416 .name = "spi",
447 .id = 2, 417 .devname = "s3c64xx-spi.2",
448 .parent = &clk_pclk_psys.clk, 418 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl, 419 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<14), 420 .ctrlbit = (1<<14),
451 }, { 421 }, {
452 .name = "timers", 422 .name = "timers",
453 .id = -1,
454 .parent = &clk_pclk_psys.clk, 423 .parent = &clk_pclk_psys.clk,
455 .enable = s5pv210_clk_ip3_ctrl, 424 .enable = s5pv210_clk_ip3_ctrl,
456 .ctrlbit = (1<<23), 425 .ctrlbit = (1<<23),
457 }, { 426 }, {
458 .name = "adc", 427 .name = "adc",
459 .id = -1,
460 .parent = &clk_pclk_psys.clk, 428 .parent = &clk_pclk_psys.clk,
461 .enable = s5pv210_clk_ip3_ctrl, 429 .enable = s5pv210_clk_ip3_ctrl,
462 .ctrlbit = (1<<24), 430 .ctrlbit = (1<<24),
463 }, { 431 }, {
464 .name = "keypad", 432 .name = "keypad",
465 .id = -1,
466 .parent = &clk_pclk_psys.clk, 433 .parent = &clk_pclk_psys.clk,
467 .enable = s5pv210_clk_ip3_ctrl, 434 .enable = s5pv210_clk_ip3_ctrl,
468 .ctrlbit = (1<<21), 435 .ctrlbit = (1<<21),
469 }, { 436 }, {
470 .name = "iis", 437 .name = "iis",
471 .id = 0, 438 .devname = "samsung-i2s.0",
472 .parent = &clk_p, 439 .parent = &clk_p,
473 .enable = s5pv210_clk_ip3_ctrl, 440 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1<<4), 441 .ctrlbit = (1<<4),
475 }, { 442 }, {
476 .name = "iis", 443 .name = "iis",
477 .id = 1, 444 .devname = "samsung-i2s.1",
478 .parent = &clk_p, 445 .parent = &clk_p,
479 .enable = s5pv210_clk_ip3_ctrl, 446 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 5), 447 .ctrlbit = (1 << 5),
481 }, { 448 }, {
482 .name = "iis", 449 .name = "iis",
483 .id = 2, 450 .devname = "samsung-i2s.2",
484 .parent = &clk_p, 451 .parent = &clk_p,
485 .enable = s5pv210_clk_ip3_ctrl, 452 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 6), 453 .ctrlbit = (1 << 6),
487 }, { 454 }, {
488 .name = "spdif", 455 .name = "spdif",
489 .id = -1,
490 .parent = &clk_p, 456 .parent = &clk_p,
491 .enable = s5pv210_clk_ip3_ctrl, 457 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 0), 458 .ctrlbit = (1 << 0),
@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = {
496static struct clk init_clocks[] = { 462static struct clk init_clocks[] = {
497 { 463 {
498 .name = "hclk_imem", 464 .name = "hclk_imem",
499 .id = -1,
500 .parent = &clk_hclk_msys.clk, 465 .parent = &clk_hclk_msys.clk,
501 .ctrlbit = (1 << 5), 466 .ctrlbit = (1 << 5),
502 .enable = s5pv210_clk_ip0_ctrl, 467 .enable = s5pv210_clk_ip0_ctrl,
503 .ops = &clk_hclk_imem_ops, 468 .ops = &clk_hclk_imem_ops,
504 }, { 469 }, {
505 .name = "uart", 470 .name = "uart",
506 .id = 0, 471 .devname = "s5pv210-uart.0",
507 .parent = &clk_pclk_psys.clk, 472 .parent = &clk_pclk_psys.clk,
508 .enable = s5pv210_clk_ip3_ctrl, 473 .enable = s5pv210_clk_ip3_ctrl,
509 .ctrlbit = (1 << 17), 474 .ctrlbit = (1 << 17),
510 }, { 475 }, {
511 .name = "uart", 476 .name = "uart",
512 .id = 1, 477 .devname = "s5pv210-uart.1",
513 .parent = &clk_pclk_psys.clk, 478 .parent = &clk_pclk_psys.clk,
514 .enable = s5pv210_clk_ip3_ctrl, 479 .enable = s5pv210_clk_ip3_ctrl,
515 .ctrlbit = (1 << 18), 480 .ctrlbit = (1 << 18),
516 }, { 481 }, {
517 .name = "uart", 482 .name = "uart",
518 .id = 2, 483 .devname = "s5pv210-uart.2",
519 .parent = &clk_pclk_psys.clk, 484 .parent = &clk_pclk_psys.clk,
520 .enable = s5pv210_clk_ip3_ctrl, 485 .enable = s5pv210_clk_ip3_ctrl,
521 .ctrlbit = (1 << 19), 486 .ctrlbit = (1 << 19),
522 }, { 487 }, {
523 .name = "uart", 488 .name = "uart",
524 .id = 3, 489 .devname = "s5pv210-uart.3",
525 .parent = &clk_pclk_psys.clk, 490 .parent = &clk_pclk_psys.clk,
526 .enable = s5pv210_clk_ip3_ctrl, 491 .enable = s5pv210_clk_ip3_ctrl,
527 .ctrlbit = (1 << 20), 492 .ctrlbit = (1 << 20),
528 }, { 493 }, {
529 .name = "sromc", 494 .name = "sromc",
530 .id = -1,
531 .parent = &clk_hclk_psys.clk, 495 .parent = &clk_hclk_psys.clk,
532 .enable = s5pv210_clk_ip1_ctrl, 496 .enable = s5pv210_clk_ip1_ctrl,
533 .ctrlbit = (1 << 26), 497 .ctrlbit = (1 << 26),
@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = {
579static struct clksrc_clk clk_sclk_dac = { 543static struct clksrc_clk clk_sclk_dac = {
580 .clk = { 544 .clk = {
581 .name = "sclk_dac", 545 .name = "sclk_dac",
582 .id = -1,
583 .enable = s5pv210_clk_mask0_ctrl, 546 .enable = s5pv210_clk_mask0_ctrl,
584 .ctrlbit = (1 << 2), 547 .ctrlbit = (1 << 2),
585 }, 548 },
@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = {
590static struct clksrc_clk clk_sclk_pixel = { 553static struct clksrc_clk clk_sclk_pixel = {
591 .clk = { 554 .clk = {
592 .name = "sclk_pixel", 555 .name = "sclk_pixel",
593 .id = -1,
594 .parent = &clk_sclk_vpll.clk, 556 .parent = &clk_sclk_vpll.clk,
595 }, 557 },
596 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, 558 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
609static struct clksrc_clk clk_sclk_hdmi = { 571static struct clksrc_clk clk_sclk_hdmi = {
610 .clk = { 572 .clk = {
611 .name = "sclk_hdmi", 573 .name = "sclk_hdmi",
612 .id = -1,
613 .enable = s5pv210_clk_mask0_ctrl, 574 .enable = s5pv210_clk_mask0_ctrl,
614 .ctrlbit = (1 << 0), 575 .ctrlbit = (1 << 0),
615 }, 576 },
@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
647static struct clksrc_clk clk_sclk_audio0 = { 608static struct clksrc_clk clk_sclk_audio0 = {
648 .clk = { 609 .clk = {
649 .name = "sclk_audio", 610 .name = "sclk_audio",
650 .id = 0, 611 .devname = "soc-audio.0",
651 .enable = s5pv210_clk_mask0_ctrl, 612 .enable = s5pv210_clk_mask0_ctrl,
652 .ctrlbit = (1 << 24), 613 .ctrlbit = (1 << 24),
653 }, 614 },
@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
676static struct clksrc_clk clk_sclk_audio1 = { 637static struct clksrc_clk clk_sclk_audio1 = {
677 .clk = { 638 .clk = {
678 .name = "sclk_audio", 639 .name = "sclk_audio",
679 .id = 1, 640 .devname = "soc-audio.1",
680 .enable = s5pv210_clk_mask0_ctrl, 641 .enable = s5pv210_clk_mask0_ctrl,
681 .ctrlbit = (1 << 25), 642 .ctrlbit = (1 << 25),
682 }, 643 },
@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
705static struct clksrc_clk clk_sclk_audio2 = { 666static struct clksrc_clk clk_sclk_audio2 = {
706 .clk = { 667 .clk = {
707 .name = "sclk_audio", 668 .name = "sclk_audio",
708 .id = 2, 669 .devname = "soc-audio.2",
709 .enable = s5pv210_clk_mask0_ctrl, 670 .enable = s5pv210_clk_mask0_ctrl,
710 .ctrlbit = (1 << 26), 671 .ctrlbit = (1 << 26),
711 }, 672 },
@@ -725,48 +686,12 @@ static struct clksrc_sources clkset_sclk_spdif = {
725 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), 686 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
726}; 687};
727 688
728static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
729{
730 struct clk *pclk;
731 int ret;
732
733 pclk = clk_get_parent(clk);
734 if (IS_ERR(pclk))
735 return -EINVAL;
736
737 ret = pclk->ops->set_rate(pclk, rate);
738 clk_put(pclk);
739
740 return ret;
741}
742
743static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
744{
745 struct clk *pclk;
746 int rate;
747
748 pclk = clk_get_parent(clk);
749 if (IS_ERR(pclk))
750 return -EINVAL;
751
752 rate = pclk->ops->get_rate(clk);
753 clk_put(pclk);
754
755 return rate;
756}
757
758static struct clk_ops s5pv210_sclk_spdif_ops = {
759 .set_rate = s5pv210_spdif_set_rate,
760 .get_rate = s5pv210_spdif_get_rate,
761};
762
763static struct clksrc_clk clk_sclk_spdif = { 689static struct clksrc_clk clk_sclk_spdif = {
764 .clk = { 690 .clk = {
765 .name = "sclk_spdif", 691 .name = "sclk_spdif",
766 .id = -1,
767 .enable = s5pv210_clk_mask0_ctrl, 692 .enable = s5pv210_clk_mask0_ctrl,
768 .ctrlbit = (1 << 27), 693 .ctrlbit = (1 << 27),
769 .ops = &s5pv210_sclk_spdif_ops, 694 .ops = &s5p_sclk_spdif_ops,
770 }, 695 },
771 .sources = &clkset_sclk_spdif, 696 .sources = &clkset_sclk_spdif,
772 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, 697 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
@@ -793,7 +718,6 @@ static struct clksrc_clk clksrcs[] = {
793 { 718 {
794 .clk = { 719 .clk = {
795 .name = "sclk_dmc", 720 .name = "sclk_dmc",
796 .id = -1,
797 }, 721 },
798 .sources = &clkset_group1, 722 .sources = &clkset_group1,
799 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, 723 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +725,6 @@ static struct clksrc_clk clksrcs[] = {
801 }, { 725 }, {
802 .clk = { 726 .clk = {
803 .name = "sclk_onenand", 727 .name = "sclk_onenand",
804 .id = -1,
805 }, 728 },
806 .sources = &clkset_sclk_onenand, 729 .sources = &clkset_sclk_onenand,
807 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, 730 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +732,7 @@ static struct clksrc_clk clksrcs[] = {
809 }, { 732 }, {
810 .clk = { 733 .clk = {
811 .name = "uclk1", 734 .name = "uclk1",
812 .id = 0, 735 .devname = "s5pv210-uart.0",
813 .enable = s5pv210_clk_mask0_ctrl, 736 .enable = s5pv210_clk_mask0_ctrl,
814 .ctrlbit = (1 << 12), 737 .ctrlbit = (1 << 12),
815 }, 738 },
@@ -819,7 +742,7 @@ static struct clksrc_clk clksrcs[] = {
819 }, { 742 }, {
820 .clk = { 743 .clk = {
821 .name = "uclk1", 744 .name = "uclk1",
822 .id = 1, 745 .devname = "s5pv210-uart.1",
823 .enable = s5pv210_clk_mask0_ctrl, 746 .enable = s5pv210_clk_mask0_ctrl,
824 .ctrlbit = (1 << 13), 747 .ctrlbit = (1 << 13),
825 }, 748 },
@@ -829,7 +752,7 @@ static struct clksrc_clk clksrcs[] = {
829 }, { 752 }, {
830 .clk = { 753 .clk = {
831 .name = "uclk1", 754 .name = "uclk1",
832 .id = 2, 755 .devname = "s5pv210-uart.2",
833 .enable = s5pv210_clk_mask0_ctrl, 756 .enable = s5pv210_clk_mask0_ctrl,
834 .ctrlbit = (1 << 14), 757 .ctrlbit = (1 << 14),
835 }, 758 },
@@ -839,7 +762,7 @@ static struct clksrc_clk clksrcs[] = {
839 }, { 762 }, {
840 .clk = { 763 .clk = {
841 .name = "uclk1", 764 .name = "uclk1",
842 .id = 3, 765 .devname = "s5pv210-uart.3",
843 .enable = s5pv210_clk_mask0_ctrl, 766 .enable = s5pv210_clk_mask0_ctrl,
844 .ctrlbit = (1 << 15), 767 .ctrlbit = (1 << 15),
845 }, 768 },
@@ -849,7 +772,6 @@ static struct clksrc_clk clksrcs[] = {
849 }, { 772 }, {
850 .clk = { 773 .clk = {
851 .name = "sclk_mixer", 774 .name = "sclk_mixer",
852 .id = -1,
853 .enable = s5pv210_clk_mask0_ctrl, 775 .enable = s5pv210_clk_mask0_ctrl,
854 .ctrlbit = (1 << 1), 776 .ctrlbit = (1 << 1),
855 }, 777 },
@@ -858,7 +780,7 @@ static struct clksrc_clk clksrcs[] = {
858 }, { 780 }, {
859 .clk = { 781 .clk = {
860 .name = "sclk_fimc", 782 .name = "sclk_fimc",
861 .id = 0, 783 .devname = "s5pv210-fimc.0",
862 .enable = s5pv210_clk_mask1_ctrl, 784 .enable = s5pv210_clk_mask1_ctrl,
863 .ctrlbit = (1 << 2), 785 .ctrlbit = (1 << 2),
864 }, 786 },
@@ -868,7 +790,7 @@ static struct clksrc_clk clksrcs[] = {
868 }, { 790 }, {
869 .clk = { 791 .clk = {
870 .name = "sclk_fimc", 792 .name = "sclk_fimc",
871 .id = 1, 793 .devname = "s5pv210-fimc.1",
872 .enable = s5pv210_clk_mask1_ctrl, 794 .enable = s5pv210_clk_mask1_ctrl,
873 .ctrlbit = (1 << 3), 795 .ctrlbit = (1 << 3),
874 }, 796 },
@@ -878,7 +800,7 @@ static struct clksrc_clk clksrcs[] = {
878 }, { 800 }, {
879 .clk = { 801 .clk = {
880 .name = "sclk_fimc", 802 .name = "sclk_fimc",
881 .id = 2, 803 .devname = "s5pv210-fimc.2",
882 .enable = s5pv210_clk_mask1_ctrl, 804 .enable = s5pv210_clk_mask1_ctrl,
883 .ctrlbit = (1 << 4), 805 .ctrlbit = (1 << 4),
884 }, 806 },
@@ -888,7 +810,7 @@ static struct clksrc_clk clksrcs[] = {
888 }, { 810 }, {
889 .clk = { 811 .clk = {
890 .name = "sclk_cam", 812 .name = "sclk_cam",
891 .id = 0, 813 .devname = "s5pv210-fimc.0",
892 .enable = s5pv210_clk_mask0_ctrl, 814 .enable = s5pv210_clk_mask0_ctrl,
893 .ctrlbit = (1 << 3), 815 .ctrlbit = (1 << 3),
894 }, 816 },
@@ -898,7 +820,7 @@ static struct clksrc_clk clksrcs[] = {
898 }, { 820 }, {
899 .clk = { 821 .clk = {
900 .name = "sclk_cam", 822 .name = "sclk_cam",
901 .id = 1, 823 .devname = "s5pv210-fimc.1",
902 .enable = s5pv210_clk_mask0_ctrl, 824 .enable = s5pv210_clk_mask0_ctrl,
903 .ctrlbit = (1 << 4), 825 .ctrlbit = (1 << 4),
904 }, 826 },
@@ -908,7 +830,6 @@ static struct clksrc_clk clksrcs[] = {
908 }, { 830 }, {
909 .clk = { 831 .clk = {
910 .name = "sclk_fimd", 832 .name = "sclk_fimd",
911 .id = -1,
912 .enable = s5pv210_clk_mask0_ctrl, 833 .enable = s5pv210_clk_mask0_ctrl,
913 .ctrlbit = (1 << 5), 834 .ctrlbit = (1 << 5),
914 }, 835 },
@@ -918,7 +839,7 @@ static struct clksrc_clk clksrcs[] = {
918 }, { 839 }, {
919 .clk = { 840 .clk = {
920 .name = "sclk_mmc", 841 .name = "sclk_mmc",
921 .id = 0, 842 .devname = "s3c-sdhci.0",
922 .enable = s5pv210_clk_mask0_ctrl, 843 .enable = s5pv210_clk_mask0_ctrl,
923 .ctrlbit = (1 << 8), 844 .ctrlbit = (1 << 8),
924 }, 845 },
@@ -928,7 +849,7 @@ static struct clksrc_clk clksrcs[] = {
928 }, { 849 }, {
929 .clk = { 850 .clk = {
930 .name = "sclk_mmc", 851 .name = "sclk_mmc",
931 .id = 1, 852 .devname = "s3c-sdhci.1",
932 .enable = s5pv210_clk_mask0_ctrl, 853 .enable = s5pv210_clk_mask0_ctrl,
933 .ctrlbit = (1 << 9), 854 .ctrlbit = (1 << 9),
934 }, 855 },
@@ -938,7 +859,7 @@ static struct clksrc_clk clksrcs[] = {
938 }, { 859 }, {
939 .clk = { 860 .clk = {
940 .name = "sclk_mmc", 861 .name = "sclk_mmc",
941 .id = 2, 862 .devname = "s3c-sdhci.2",
942 .enable = s5pv210_clk_mask0_ctrl, 863 .enable = s5pv210_clk_mask0_ctrl,
943 .ctrlbit = (1 << 10), 864 .ctrlbit = (1 << 10),
944 }, 865 },
@@ -948,7 +869,7 @@ static struct clksrc_clk clksrcs[] = {
948 }, { 869 }, {
949 .clk = { 870 .clk = {
950 .name = "sclk_mmc", 871 .name = "sclk_mmc",
951 .id = 3, 872 .devname = "s3c-sdhci.3",
952 .enable = s5pv210_clk_mask0_ctrl, 873 .enable = s5pv210_clk_mask0_ctrl,
953 .ctrlbit = (1 << 11), 874 .ctrlbit = (1 << 11),
954 }, 875 },
@@ -958,7 +879,6 @@ static struct clksrc_clk clksrcs[] = {
958 }, { 879 }, {
959 .clk = { 880 .clk = {
960 .name = "sclk_mfc", 881 .name = "sclk_mfc",
961 .id = -1,
962 .enable = s5pv210_clk_ip0_ctrl, 882 .enable = s5pv210_clk_ip0_ctrl,
963 .ctrlbit = (1 << 16), 883 .ctrlbit = (1 << 16),
964 }, 884 },
@@ -968,7 +888,6 @@ static struct clksrc_clk clksrcs[] = {
968 }, { 888 }, {
969 .clk = { 889 .clk = {
970 .name = "sclk_g2d", 890 .name = "sclk_g2d",
971 .id = -1,
972 .enable = s5pv210_clk_ip0_ctrl, 891 .enable = s5pv210_clk_ip0_ctrl,
973 .ctrlbit = (1 << 12), 892 .ctrlbit = (1 << 12),
974 }, 893 },
@@ -978,7 +897,6 @@ static struct clksrc_clk clksrcs[] = {
978 }, { 897 }, {
979 .clk = { 898 .clk = {
980 .name = "sclk_g3d", 899 .name = "sclk_g3d",
981 .id = -1,
982 .enable = s5pv210_clk_ip0_ctrl, 900 .enable = s5pv210_clk_ip0_ctrl,
983 .ctrlbit = (1 << 8), 901 .ctrlbit = (1 << 8),
984 }, 902 },
@@ -988,7 +906,6 @@ static struct clksrc_clk clksrcs[] = {
988 }, { 906 }, {
989 .clk = { 907 .clk = {
990 .name = "sclk_csis", 908 .name = "sclk_csis",
991 .id = -1,
992 .enable = s5pv210_clk_mask0_ctrl, 909 .enable = s5pv210_clk_mask0_ctrl,
993 .ctrlbit = (1 << 6), 910 .ctrlbit = (1 << 6),
994 }, 911 },
@@ -998,7 +915,7 @@ static struct clksrc_clk clksrcs[] = {
998 }, { 915 }, {
999 .clk = { 916 .clk = {
1000 .name = "sclk_spi", 917 .name = "sclk_spi",
1001 .id = 0, 918 .devname = "s3c64xx-spi.0",
1002 .enable = s5pv210_clk_mask0_ctrl, 919 .enable = s5pv210_clk_mask0_ctrl,
1003 .ctrlbit = (1 << 16), 920 .ctrlbit = (1 << 16),
1004 }, 921 },
@@ -1008,7 +925,7 @@ static struct clksrc_clk clksrcs[] = {
1008 }, { 925 }, {
1009 .clk = { 926 .clk = {
1010 .name = "sclk_spi", 927 .name = "sclk_spi",
1011 .id = 1, 928 .devname = "s3c64xx-spi.1",
1012 .enable = s5pv210_clk_mask0_ctrl, 929 .enable = s5pv210_clk_mask0_ctrl,
1013 .ctrlbit = (1 << 17), 930 .ctrlbit = (1 << 17),
1014 }, 931 },
@@ -1018,7 +935,6 @@ static struct clksrc_clk clksrcs[] = {
1018 }, { 935 }, {
1019 .clk = { 936 .clk = {
1020 .name = "sclk_pwi", 937 .name = "sclk_pwi",
1021 .id = -1,
1022 .enable = s5pv210_clk_mask0_ctrl, 938 .enable = s5pv210_clk_mask0_ctrl,
1023 .ctrlbit = (1 << 29), 939 .ctrlbit = (1 << 29),
1024 }, 940 },
@@ -1028,7 +944,6 @@ static struct clksrc_clk clksrcs[] = {
1028 }, { 944 }, {
1029 .clk = { 945 .clk = {
1030 .name = "sclk_pwm", 946 .name = "sclk_pwm",
1031 .id = -1,
1032 .enable = s5pv210_clk_mask0_ctrl, 947 .enable = s5pv210_clk_mask0_ctrl,
1033 .ctrlbit = (1 << 19), 948 .ctrlbit = (1 << 19),
1034 }, 949 },
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h
deleted file mode 100644
index 60d992989bdc..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
3 *
4 * Dummy framebuffer to allow build for the moment.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_ARCH_MACH_REGS_FB_H
12#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
13
14#include <plat/regs-fb-v4.h>
15
16static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
17{
18 return 0x2400 + (window * 256 *4 ) + reg;
19}
20
21#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 4e1d8ff5ae59..509627f25111 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/map.h> 30#include <mach/map.h>
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <mach/regs-fb.h>
33 32
34#include <plat/gpio-cfg.h> 33#include <plat/gpio-cfg.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
@@ -40,6 +39,7 @@
40#include <plat/fimc-core.h> 39#include <plat/fimc-core.h>
41#include <plat/sdhci.h> 40#include <plat/sdhci.h>
42#include <plat/s5p-time.h> 41#include <plat/s5p-time.h>
42#include <plat/regs-fb-v4.h>
43 43
44/* Following are default values for UCON, ULCON and UFCON UART registers */ 44/* Following are default values for UCON, ULCON and UFCON UART registers */
45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 45#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 31d5aa769753..e0c4d06b9db6 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -34,7 +34,6 @@
34 34
35#include <mach/map.h> 35#include <mach/map.h>
36#include <mach/regs-clock.h> 36#include <mach/regs-clock.h>
37#include <mach/regs-fb.h>
38 37
39#include <plat/gpio-cfg.h> 38#include <plat/gpio-cfg.h>
40#include <plat/regs-serial.h> 39#include <plat/regs-serial.h>
@@ -47,6 +46,7 @@
47#include <plat/sdhci.h> 46#include <plat/sdhci.h>
48#include <plat/clock.h> 47#include <plat/clock.h>
49#include <plat/s5p-time.h> 48#include <plat/s5p-time.h>
49#include <plat/regs-fb-v4.h>
50 50
51/* Following are default values for UCON, ULCON and UFCON UART registers */ 51/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 52#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index c6a9e86c2d5c..ef20f922249d 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -29,7 +29,6 @@
29 29
30#include <mach/map.h> 30#include <mach/map.h>
31#include <mach/regs-clock.h> 31#include <mach/regs-clock.h>
32#include <mach/regs-fb.h>
33 32
34#include <plat/regs-serial.h> 33#include <plat/regs-serial.h>
35#include <plat/regs-srom.h> 34#include <plat/regs-srom.h>
@@ -45,6 +44,8 @@
45#include <plat/pm.h> 44#include <plat/pm.h>
46#include <plat/fb.h> 45#include <plat/fb.h>
47#include <plat/s5p-time.h> 46#include <plat/s5p-time.h>
47#include <plat/backlight.h>
48#include <plat/regs-fb-v4.h>
48 49
49/* Following are default values for UCON, ULCON and UFCON UART registers */ 50/* Following are default values for UCON, ULCON and UFCON UART registers */
50#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 51#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -210,45 +211,6 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
210 .setup_gpio = s5pv210_fb_gpio_setup_24bpp, 211 .setup_gpio = s5pv210_fb_gpio_setup_24bpp,
211}; 212};
212 213
213static int smdkv210_backlight_init(struct device *dev)
214{
215 int ret;
216
217 ret = gpio_request(S5PV210_GPD0(3), "Backlight");
218 if (ret) {
219 printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
220 return ret;
221 }
222
223 /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
224 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
225
226 return 0;
227}
228
229static void smdkv210_backlight_exit(struct device *dev)
230{
231 s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
232 gpio_free(S5PV210_GPD0(3));
233}
234
235static struct platform_pwm_backlight_data smdkv210_backlight_data = {
236 .pwm_id = 3,
237 .max_brightness = 255,
238 .dft_brightness = 255,
239 .pwm_period_ns = 78770,
240 .init = smdkv210_backlight_init,
241 .exit = smdkv210_backlight_exit,
242};
243
244static struct platform_device smdkv210_backlight_device = {
245 .name = "pwm-backlight",
246 .dev = {
247 .parent = &s3c_device_timer[3].dev,
248 .platform_data = &smdkv210_backlight_data,
249 },
250};
251
252static struct platform_device *smdkv210_devices[] __initdata = { 214static struct platform_device *smdkv210_devices[] __initdata = {
253 &s3c_device_adc, 215 &s3c_device_adc,
254 &s3c_device_cfcon, 216 &s3c_device_cfcon,
@@ -270,8 +232,6 @@ static struct platform_device *smdkv210_devices[] __initdata = {
270 &samsung_device_keypad, 232 &samsung_device_keypad,
271 &smdkv210_dm9000, 233 &smdkv210_dm9000,
272 &smdkv210_lcd_lte480wv, 234 &smdkv210_lcd_lte480wv,
273 &s3c_device_timer[3],
274 &smdkv210_backlight_device,
275}; 235};
276 236
277static void __init smdkv210_dm9000_init(void) 237static void __init smdkv210_dm9000_init(void)
@@ -310,6 +270,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
310 .oversampling_shift = 2, 270 .oversampling_shift = 2,
311}; 271};
312 272
273/* LCD Backlight data */
274static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
275 .no = S5PV210_GPD0(3),
276 .func = S3C_GPIO_SFN(2),
277};
278
279static struct platform_pwm_backlight_data smdkv210_bl_data = {
280 .pwm_id = 3,
281};
282
313static void __init smdkv210_map_io(void) 283static void __init smdkv210_map_io(void)
314{ 284{
315 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 285 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -341,6 +311,8 @@ static void __init smdkv210_machine_init(void)
341 311
342 s3c_fb_set_platdata(&smdkv210_lcd0_pdata); 312 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
343 313
314 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
315
344 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); 316 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
345} 317}
346 318
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index e932ebfac56d..55103c8220b3 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -15,7 +15,6 @@
15#include <linux/fb.h> 15#include <linux/fb.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17 17
18#include <mach/regs-fb.h>
19#include <mach/map.h> 18#include <mach/map.h>
20#include <plat/fb.h> 19#include <plat/fb.h>
21#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 23:57:41 -0500