diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 07:20:08 -0400 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 07:20:08 -0400 |
commit | 86f82da586098f16d92b5637808c323f5455e935 (patch) | |
tree | 6397eb5550172b89d383254c7e4bca87ae4a8659 /arch/arm/mach-s5pv210 | |
parent | db3c94a7edc6b29f8d52ba5884dec6a15feeadad (diff) | |
parent | e90a0f3c460406d6a5a698016bc525c3e6968cb6 (diff) |
Merge branch 'next-samsung-cleanup-2' into next-samsung-devel-2
Conflicts:
arch/arm/plat-s5p/include/plat/pll.h
Diffstat (limited to 'arch/arm/mach-s5pv210')
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/clkdev.h | 7 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/include/mach/pwm-clock.h | 70 | ||||
-rw-r--r-- | arch/arm/mach-s5pv210/setup-sdhci.c | 41 |
3 files changed, 0 insertions, 118 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/clkdev.h +++ /dev/null | |||
@@ -1,7 +0,0 @@ | |||
1 | #ifndef __MACH_CLKDEV_H__ | ||
2 | #define __MACH_CLKDEV_H__ | ||
3 | |||
4 | #define __clk_get(clk) ({ 1; }) | ||
5 | #define __clk_put(clk) do {} while (0) | ||
6 | |||
7 | #endif | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h deleted file mode 100644 index f8a9f1b330e0..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h +++ /dev/null | |||
@@ -1,70 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Copyright 2008 Openmoko, Inc. | ||
7 | * Copyright 2008 Simtec Electronics | ||
8 | * Ben Dooks <ben@simtec.co.uk> | ||
9 | * http://armlinux.simtec.co.uk/ | ||
10 | * | ||
11 | * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h | ||
12 | * | ||
13 | * S5PV210 - pwm clock and timer support | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License version 2 as | ||
17 | * published by the Free Software Foundation. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ASM_ARCH_PWMCLK_H | ||
21 | #define __ASM_ARCH_PWMCLK_H __FILE__ | ||
22 | |||
23 | /** | ||
24 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
25 | * @tcfg: The timer TCFG1 register bits shifted down to 0. | ||
26 | * | ||
27 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
28 | * any of the TDIV clocks. | ||
29 | */ | ||
30 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
31 | { | ||
32 | return tcfg == S3C64XX_TCFG1_MUX_TCLK; | ||
33 | } | ||
34 | |||
35 | /** | ||
36 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
37 | * @tcfg1: The tcfg1 setting, shifted down. | ||
38 | * | ||
39 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
40 | * caller has already checked to see if this is not a TCLK source. | ||
41 | */ | ||
42 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
43 | { | ||
44 | return 1 << tcfg1; | ||
45 | } | ||
46 | |||
47 | /** | ||
48 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
49 | * | ||
50 | * Return true if we have a /1 in the tdiv setting. | ||
51 | */ | ||
52 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
53 | { | ||
54 | return 1; | ||
55 | } | ||
56 | |||
57 | /** | ||
58 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
59 | * @div: The divisor to calculate the bit information for. | ||
60 | * | ||
61 | * Turn a divisor into the necessary bit field for TCFG1. | ||
62 | */ | ||
63 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
64 | { | ||
65 | return ilog2(div); | ||
66 | } | ||
67 | |||
68 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK | ||
69 | |||
70 | #endif /* __ASM_ARCH_PWMCLK_H */ | ||
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index a83b6c909f6b..6b8ccc4d35fd 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c | |||
@@ -10,17 +10,7 @@ | |||
10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | 13 | #include <linux/types.h> |
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <linux/mmc/card.h> | ||
20 | #include <linux/mmc/host.h> | ||
21 | |||
22 | #include <plat/regs-sdhci.h> | ||
23 | #include <plat/sdhci.h> | ||
24 | 14 | ||
25 | /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ | 15 | /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ |
26 | 16 | ||
@@ -30,34 +20,3 @@ char *s5pv210_hsmmc_clksrcs[4] = { | |||
30 | [2] = "sclk_mmc", /* mmc_bus */ | 20 | [2] = "sclk_mmc", /* mmc_bus */ |
31 | /* [3] = NULL, - reserved */ | 21 | /* [3] = NULL, - reserved */ |
32 | }; | 22 | }; |
33 | |||
34 | void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, | ||
35 | void __iomem *r, | ||
36 | struct mmc_ios *ios, | ||
37 | struct mmc_card *card) | ||
38 | { | ||
39 | u32 ctrl2, ctrl3; | ||
40 | |||
41 | /* don't need to alter anything according to card-type */ | ||
42 | |||
43 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); | ||
44 | |||
45 | ctrl2 = readl(r + S3C_SDHCI_CONTROL2); | ||
46 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | ||
47 | ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | ||
48 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | ||
49 | S3C_SDHCI_CTRL2_ENFBCLKRX | | ||
50 | S3C_SDHCI_CTRL2_DFCNT_NONE | | ||
51 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | ||
52 | |||
53 | if (ios->clock < 25 * 1000000) | ||
54 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | | ||
55 | S3C_SDHCI_CTRL3_FCSEL2 | | ||
56 | S3C_SDHCI_CTRL3_FCSEL1 | | ||
57 | S3C_SDHCI_CTRL3_FCSEL0); | ||
58 | else | ||
59 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | ||
60 | |||
61 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); | ||
62 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); | ||
63 | } | ||