ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names

Add support for lookup of sdhci-s3c controller clocks using generic names
for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
[kgene.kim@samsung.com: fixed trailing whitespace]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

1 files changed, 103 insertions, 64 deletions

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 43a045d354ec..dc4586b2b322 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip1_ctrl,
                 .ctrlbit        = (1<<25),
         }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<16),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<17),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<18),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<19),
-        }, {
                 .name           = "systimer",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
         },
 };
 
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<16),
+};
+
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<17),
+};
+
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<18),
+};
+
+static struct clk clk_hsmmc3 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.3",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<19),
+};
+
 static struct clk *clkset_uart_list[] = {
         [6] = &clk_mout_mpll.clk,
         [7] = &clk_mout_epll.clk,
@@ -866,46 +874,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 9),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 10),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.3",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 11),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
                         .name           = "sclk_mfc",
                         .devname        = "s5p-mfc",
                         .enable         = s5pv210_clk_ip0_ctrl,
@@ -1030,11 +998,70 @@ static struct clksrc_clk clk_sclk_uart3	= {
         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 9),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 10),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc3 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 11),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
 static struct clksrc_clk *clksrc_cdev[] = {
         &clk_sclk_uart0,
         &clk_sclk_uart1,
         &clk_sclk_uart2,
         &clk_sclk_uart3,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_mmc3,
+};
+
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_hsmmc3,
 };
 
 /* Clock initialisation code */
@@ -1282,6 +1309,14 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
         CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
         CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
         CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
 };
 
 void __init s5pv210_register_clocks(void)
@@ -1306,6 +1341,10 @@ void __init s5pv210_register_clocks(void)
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
 
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
+
         s3c24xx_register_clock(&dummy_apb_pclk);
         s3c_pwmclk_init();
 }