diff options
author | Seungwhan Youn <sw.youn@samsung.com> | 2010-10-13 21:39:08 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-25 03:05:56 -0400 |
commit | d4b34c6c849d67b7afaa90d55dc7fab981c72950 (patch) | |
tree | c6b5c6bfe622832865a98fecec1159cb350bc18a /arch/arm/mach-s5pc100/clock.c | |
parent | 900fa0196c564895bfa2eb412d2a83421d3f3444 (diff) |
ARM: S5P: Reduce duplicated EPLL control codes
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other
H/W blocks. Until now, to control EPLL, each of SoCs make their own functions
in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and
'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move
these duplicated codes to common EPLL functions that use platform wide.
Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
Acked-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100/clock.c')
-rw-r--r-- | arch/arm/mach-s5pc100/clock.c | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 306ae743ad72..42c2636ca3ac 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c | |||
@@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = { | |||
273 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, | 273 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, |
274 | }; | 274 | }; |
275 | 275 | ||
276 | static int s5pc100_epll_enable(struct clk *clk, int enable) | ||
277 | { | ||
278 | unsigned int ctrlbit = clk->ctrlbit; | ||
279 | unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; | ||
280 | |||
281 | if (enable) | ||
282 | __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); | ||
283 | else | ||
284 | __raw_writel(epll_con, S5P_EPLL_CON); | ||
285 | |||
286 | return 0; | ||
287 | } | ||
288 | |||
289 | static unsigned long s5pc100_epll_get_rate(struct clk *clk) | ||
290 | { | ||
291 | return clk->rate; | ||
292 | } | ||
293 | |||
294 | static u32 epll_div[][4] = { | 276 | static u32 epll_div[][4] = { |
295 | { 32750000, 131, 3, 4 }, | 277 | { 32750000, 131, 3, 4 }, |
296 | { 32768000, 131, 3, 4 }, | 278 | { 32768000, 131, 3, 4 }, |
@@ -347,7 +329,7 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) | |||
347 | } | 329 | } |
348 | 330 | ||
349 | static struct clk_ops s5pc100_epll_ops = { | 331 | static struct clk_ops s5pc100_epll_ops = { |
350 | .get_rate = s5pc100_epll_get_rate, | 332 | .get_rate = s5p_epll_get_rate, |
351 | .set_rate = s5pc100_epll_set_rate, | 333 | .set_rate = s5pc100_epll_set_rate, |
352 | }; | 334 | }; |
353 | 335 | ||
@@ -1261,7 +1243,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) | |||
1261 | unsigned int ptr; | 1243 | unsigned int ptr; |
1262 | 1244 | ||
1263 | /* Set S5PC100 functions for clk_fout_epll */ | 1245 | /* Set S5PC100 functions for clk_fout_epll */ |
1264 | clk_fout_epll.enable = s5pc100_epll_enable; | 1246 | clk_fout_epll.enable = s5p_epll_enable; |
1265 | clk_fout_epll.ops = &s5pc100_epll_ops; | 1247 | clk_fout_epll.ops = &s5pc100_epll_ops; |
1266 | 1248 | ||
1267 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | 1249 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); |