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authorAjay Kumar <ajaykumar.rs@samsung.com>2011-09-26 18:46:45 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-10-04 06:00:39 -0400
commitd93f5eefd456bde3dd14eac7b909f3ba4e55cdbb (patch)
tree545f44e07d55f8b809716bafe24b50bcc32d01b1 /arch/arm/mach-s5p64x0/include/mach
parentc0735c85d1b9e2a1954deb3b3c8d5061f70464e5 (diff)
ARM: S5P64X0: Add register base and IRQ for Framebuffer
This patch adds: -- Framebuffer related register mappings and bit fields. -- IRQ number being used. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p64x0/include/mach')
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h3
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 5837a36ece8d..53982db9d259 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -87,6 +87,10 @@
87 87
88#define IRQ_I2S0 IRQ_I2SV40 88#define IRQ_I2S0 IRQ_I2SV40
89 89
90#define IRQ_LCD_FIFO IRQ_DISPCON0
91#define IRQ_LCD_VSYNC IRQ_DISPCON1
92#define IRQ_LCD_SYSTEM IRQ_DISPCON2
93
90/* S5P6450 EINT feature will be added */ 94/* S5P6450 EINT feature will be added */
91 95
92/* 96/*
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c91257c7ca..c5ef50c26291 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -47,6 +47,8 @@
47 47
48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
49 49
50#define S5P64X0_PA_FB 0xEE000000
51
50#define S5P64X0_PA_I2S 0xF2000000 52#define S5P64X0_PA_I2S 0xF2000000
51#define S5P6450_PA_I2S1 0xF2800000 53#define S5P6450_PA_I2S1 0xF2800000
52#define S5P6450_PA_I2S2 0xF2900000 54#define S5P6450_PA_I2S2 0xF2900000
@@ -64,6 +66,7 @@
64#define S3C_PA_IIC1 S5P6440_PA_IIC1 66#define S3C_PA_IIC1 S5P6440_PA_IIC1
65#define S3C_PA_RTC S5P64X0_PA_RTC 67#define S3C_PA_RTC S5P64X0_PA_RTC
66#define S3C_PA_WDT S5P64X0_PA_WDT 68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB
67 70
68#define S5P_PA_CHIPID S5P64X0_PA_CHIPID 71#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
69#define S5P_PA_SROMC S5P64X0_PA_SROMC 72#define S5P_PA_SROMC S5P64X0_PA_SROMC