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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/arm/mach-s5p6442
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/arm/mach-s5p6442')
-rw-r--r--arch/arm/mach-s5p6442/Kconfig26
-rw-r--r--arch/arm/mach-s5p6442/Makefile24
-rw-r--r--arch/arm/mach-s5p6442/Makefile.boot2
-rw-r--r--arch/arm/mach-s5p6442/clock.c402
-rw-r--r--arch/arm/mach-s5p6442/cpu.c122
-rw-r--r--arch/arm/mach-s5p6442/dev-audio.c197
-rw-r--r--arch/arm/mach-s5p6442/dev-spi.c123
-rw-r--r--arch/arm/mach-s5p6442/dma.c105
-rw-r--r--arch/arm/mach-s5p6442/include/mach/debug-macro.S36
-rw-r--r--arch/arm/mach-s5p6442/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5p6442/include/mach/entry-macro.S48
-rw-r--r--arch/arm/mach-s5p6442/include/mach/gpio.h123
-rw-r--r--arch/arm/mach-s5p6442/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5p6442/include/mach/io.h17
-rw-r--r--arch/arm/mach-s5p6442/include/mach/irqs.h87
-rw-r--r--arch/arm/mach-s5p6442/include/mach/map.h74
-rw-r--r--arch/arm/mach-s5p6442/include/mach/memory.h19
-rw-r--r--arch/arm/mach-s5p6442/include/mach/pwm-clock.h70
-rw-r--r--arch/arm/mach-s5p6442/include/mach/regs-clock.h103
-rw-r--r--arch/arm/mach-s5p6442/include/mach/regs-irq.h19
-rw-r--r--arch/arm/mach-s5p6442/include/mach/spi-clocks.h17
-rw-r--r--arch/arm/mach-s5p6442/include/mach/system.h23
-rw-r--r--arch/arm/mach-s5p6442/include/mach/tick.h26
-rw-r--r--arch/arm/mach-s5p6442/include/mach/timex.h24
-rw-r--r--arch/arm/mach-s5p6442/include/mach/uncompress.h24
-rw-r--r--arch/arm/mach-s5p6442/include/mach/vmalloc.h17
-rw-r--r--arch/arm/mach-s5p6442/init.c44
-rw-r--r--arch/arm/mach-s5p6442/mach-smdk6442.c93
-rw-r--r--arch/arm/mach-s5p6442/setup-i2c0.c25
29 files changed, 0 insertions, 1934 deletions
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig
deleted file mode 100644
index 0fda0a5df968..000000000000
--- a/arch/arm/mach-s5p6442/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
1# arch/arm/mach-s5p6442/Kconfig
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the S5P6442
9
10if ARCH_S5P6442
11
12config CPU_S5P6442
13 bool
14 select PLAT_S5P
15 select S3C_PL330_DMA
16 help
17 Enable S5P6442 CPU support
18
19config MACH_SMDK6442
20 bool "SMDK6442"
21 select CPU_S5P6442
22 select S3C_DEV_WDT
23 help
24 Machine support for Samsung SMDK6442
25
26endif
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile
deleted file mode 100644
index 90a3d8373416..000000000000
--- a/arch/arm/mach-s5p6442/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
1# arch/arm/mach-s5p6442/Makefile
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P6442 system
14
15obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o
21
22# device support
23obj-y += dev-audio.o
24obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
diff --git a/arch/arm/mach-s5p6442/Makefile.boot b/arch/arm/mach-s5p6442/Makefile.boot
deleted file mode 100644
index ff90aa13bd67..000000000000
--- a/arch/arm/mach-s5p6442/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
deleted file mode 100644
index dcd20f17212a..000000000000
--- a/arch/arm/mach-s5p6442/clock.c
+++ /dev/null
@@ -1,402 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22
23#include <plat/cpu-freq.h>
24#include <mach/regs-clock.h>
25#include <plat/clock.h>
26#include <plat/cpu.h>
27#include <plat/pll.h>
28#include <plat/s5p-clock.h>
29#include <plat/clock-clksrc.h>
30#include <plat/s5p6442.h>
31
32static struct clksrc_clk clk_mout_apll = {
33 .clk = {
34 .name = "mout_apll",
35 .id = -1,
36 },
37 .sources = &clk_src_apll,
38 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
39};
40
41static struct clksrc_clk clk_mout_mpll = {
42 .clk = {
43 .name = "mout_mpll",
44 .id = -1,
45 },
46 .sources = &clk_src_mpll,
47 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
48};
49
50static struct clksrc_clk clk_mout_epll = {
51 .clk = {
52 .name = "mout_epll",
53 .id = -1,
54 },
55 .sources = &clk_src_epll,
56 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
57};
58
59/* Possible clock sources for ARM Mux */
60static struct clk *clk_src_arm_list[] = {
61 [1] = &clk_mout_apll.clk,
62 [2] = &clk_mout_mpll.clk,
63};
64
65static struct clksrc_sources clk_src_arm = {
66 .sources = clk_src_arm_list,
67 .nr_sources = ARRAY_SIZE(clk_src_arm_list),
68};
69
70static struct clksrc_clk clk_mout_arm = {
71 .clk = {
72 .name = "mout_arm",
73 .id = -1,
74 },
75 .sources = &clk_src_arm,
76 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
77};
78
79static struct clk clk_dout_a2m = {
80 .name = "dout_a2m",
81 .id = -1,
82 .parent = &clk_mout_apll.clk,
83};
84
85/* Possible clock sources for D0 Mux */
86static struct clk *clk_src_d0_list[] = {
87 [1] = &clk_mout_mpll.clk,
88 [2] = &clk_dout_a2m,
89};
90
91static struct clksrc_sources clk_src_d0 = {
92 .sources = clk_src_d0_list,
93 .nr_sources = ARRAY_SIZE(clk_src_d0_list),
94};
95
96static struct clksrc_clk clk_mout_d0 = {
97 .clk = {
98 .name = "mout_d0",
99 .id = -1,
100 },
101 .sources = &clk_src_d0,
102 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
103};
104
105static struct clk clk_dout_apll = {
106 .name = "dout_apll",
107 .id = -1,
108 .parent = &clk_mout_arm.clk,
109};
110
111/* Possible clock sources for D0SYNC Mux */
112static struct clk *clk_src_d0sync_list[] = {
113 [1] = &clk_mout_d0.clk,
114 [2] = &clk_dout_apll,
115};
116
117static struct clksrc_sources clk_src_d0sync = {
118 .sources = clk_src_d0sync_list,
119 .nr_sources = ARRAY_SIZE(clk_src_d0sync_list),
120};
121
122static struct clksrc_clk clk_mout_d0sync = {
123 .clk = {
124 .name = "mout_d0sync",
125 .id = -1,
126 },
127 .sources = &clk_src_d0sync,
128 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
129};
130
131/* Possible clock sources for D1 Mux */
132static struct clk *clk_src_d1_list[] = {
133 [1] = &clk_mout_mpll.clk,
134 [2] = &clk_dout_a2m,
135};
136
137static struct clksrc_sources clk_src_d1 = {
138 .sources = clk_src_d1_list,
139 .nr_sources = ARRAY_SIZE(clk_src_d1_list),
140};
141
142static struct clksrc_clk clk_mout_d1 = {
143 .clk = {
144 .name = "mout_d1",
145 .id = -1,
146 },
147 .sources = &clk_src_d1,
148 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
149};
150
151/* Possible clock sources for D1SYNC Mux */
152static struct clk *clk_src_d1sync_list[] = {
153 [1] = &clk_mout_d1.clk,
154 [2] = &clk_dout_apll,
155};
156
157static struct clksrc_sources clk_src_d1sync = {
158 .sources = clk_src_d1sync_list,
159 .nr_sources = ARRAY_SIZE(clk_src_d1sync_list),
160};
161
162static struct clksrc_clk clk_mout_d1sync = {
163 .clk = {
164 .name = "mout_d1sync",
165 .id = -1,
166 },
167 .sources = &clk_src_d1sync,
168 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
169};
170
171static struct clk clk_hclkd0 = {
172 .name = "hclkd0",
173 .id = -1,
174 .parent = &clk_mout_d0sync.clk,
175};
176
177static struct clk clk_hclkd1 = {
178 .name = "hclkd1",
179 .id = -1,
180 .parent = &clk_mout_d1sync.clk,
181};
182
183static struct clk clk_pclkd0 = {
184 .name = "pclkd0",
185 .id = -1,
186 .parent = &clk_hclkd0,
187};
188
189static struct clk clk_pclkd1 = {
190 .name = "pclkd1",
191 .id = -1,
192 .parent = &clk_hclkd1,
193};
194
195int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
198}
199
200static struct clksrc_clk clksrcs[] = {
201 {
202 .clk = {
203 .name = "dout_a2m",
204 .id = -1,
205 .parent = &clk_mout_apll.clk,
206 },
207 .sources = &clk_src_apll,
208 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
209 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
210 }, {
211 .clk = {
212 .name = "dout_apll",
213 .id = -1,
214 .parent = &clk_mout_arm.clk,
215 },
216 .sources = &clk_src_arm,
217 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
218 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
219 }, {
220 .clk = {
221 .name = "hclkd1",
222 .id = -1,
223 .parent = &clk_mout_d1sync.clk,
224 },
225 .sources = &clk_src_d1sync,
226 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
227 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
228 }, {
229 .clk = {
230 .name = "hclkd0",
231 .id = -1,
232 .parent = &clk_mout_d0sync.clk,
233 },
234 .sources = &clk_src_d0sync,
235 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
236 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
237 }, {
238 .clk = {
239 .name = "pclkd0",
240 .id = -1,
241 .parent = &clk_hclkd0,
242 },
243 .sources = &clk_src_d0sync,
244 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
245 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
246 }, {
247 .clk = {
248 .name = "pclkd1",
249 .id = -1,
250 .parent = &clk_hclkd1,
251 },
252 .sources = &clk_src_d1sync,
253 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
254 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
255 }
256};
257
258/* Clock initialisation code */
259static struct clksrc_clk *init_parents[] = {
260 &clk_mout_apll,
261 &clk_mout_mpll,
262 &clk_mout_epll,
263 &clk_mout_arm,
264 &clk_mout_d0,
265 &clk_mout_d0sync,
266 &clk_mout_d1,
267 &clk_mout_d1sync,
268};
269
270void __init_or_cpufreq s5p6442_setup_clocks(void)
271{
272 struct clk *pclkd0_clk;
273 struct clk *pclkd1_clk;
274
275 unsigned long xtal;
276 unsigned long arm;
277 unsigned long hclkd0 = 0;
278 unsigned long hclkd1 = 0;
279 unsigned long pclkd0 = 0;
280 unsigned long pclkd1 = 0;
281
282 unsigned long apll;
283 unsigned long mpll;
284 unsigned long epll;
285 unsigned int ptr;
286
287 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
288
289 xtal = clk_get_rate(&clk_xtal);
290
291 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
292
293 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
294 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
295 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
296
297 printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
298 apll, mpll, epll);
299
300 clk_fout_apll.rate = apll;
301 clk_fout_mpll.rate = mpll;
302 clk_fout_epll.rate = epll;
303
304 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
305 s3c_set_clksrc(init_parents[ptr], true);
306
307 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
308 s3c_set_clksrc(&clksrcs[ptr], true);
309
310 arm = clk_get_rate(&clk_dout_apll);
311 hclkd0 = clk_get_rate(&clk_hclkd0);
312 hclkd1 = clk_get_rate(&clk_hclkd1);
313
314 pclkd0_clk = clk_get(NULL, "pclkd0");
315 BUG_ON(IS_ERR(pclkd0_clk));
316
317 pclkd0 = clk_get_rate(pclkd0_clk);
318 clk_put(pclkd0_clk);
319
320 pclkd1_clk = clk_get(NULL, "pclkd1");
321 BUG_ON(IS_ERR(pclkd1_clk));
322
323 pclkd1 = clk_get_rate(pclkd1_clk);
324 clk_put(pclkd1_clk);
325
326 printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
327 hclkd0, hclkd1, pclkd0, pclkd1);
328
329 /* For backward compatibility */
330 clk_f.rate = arm;
331 clk_h.rate = hclkd1;
332 clk_p.rate = pclkd1;
333
334 clk_pclkd0.rate = pclkd0;
335 clk_pclkd1.rate = pclkd1;
336}
337
338static struct clk init_clocks[] = {
339 {
340 .name = "systimer",
341 .id = -1,
342 .parent = &clk_pclkd1,
343 .enable = s5p6442_clk_ip3_ctrl,
344 .ctrlbit = (1<<16),
345 }, {
346 .name = "uart",
347 .id = 0,
348 .parent = &clk_pclkd1,
349 .enable = s5p6442_clk_ip3_ctrl,
350 .ctrlbit = (1<<17),
351 }, {
352 .name = "uart",
353 .id = 1,
354 .parent = &clk_pclkd1,
355 .enable = s5p6442_clk_ip3_ctrl,
356 .ctrlbit = (1<<18),
357 }, {
358 .name = "uart",
359 .id = 2,
360 .parent = &clk_pclkd1,
361 .enable = s5p6442_clk_ip3_ctrl,
362 .ctrlbit = (1<<19),
363 }, {
364 .name = "watchdog",
365 .id = -1,
366 .parent = &clk_pclkd1,
367 .enable = s5p6442_clk_ip3_ctrl,
368 .ctrlbit = (1 << 22),
369 }, {
370 .name = "timers",
371 .id = -1,
372 .parent = &clk_pclkd1,
373 .enable = s5p6442_clk_ip3_ctrl,
374 .ctrlbit = (1<<23),
375 },
376};
377
378static struct clk *clks[] __initdata = {
379 &clk_ext,
380 &clk_epll,
381 &clk_mout_apll.clk,
382 &clk_mout_mpll.clk,
383 &clk_mout_epll.clk,
384 &clk_mout_d0.clk,
385 &clk_mout_d0sync.clk,
386 &clk_mout_d1.clk,
387 &clk_mout_d1sync.clk,
388 &clk_hclkd0,
389 &clk_pclkd0,
390 &clk_hclkd1,
391 &clk_pclkd1,
392};
393
394void __init s5p6442_register_clocks(void)
395{
396 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
397
398 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
399 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
400
401 s3c_pwmclk_init();
402}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
deleted file mode 100644
index 70ac681af72b..000000000000
--- a/arch/arm/mach-s5p6442/cpu.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/cpu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/proc-fns.h>
29
30#include <mach/hardware.h>
31#include <mach/map.h>
32#include <asm/irq.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-clock.h>
36
37#include <plat/cpu.h>
38#include <plat/devs.h>
39#include <plat/clock.h>
40#include <plat/s5p6442.h>
41
42/* Initial IO mappings */
43
44static struct map_desc s5p6442_iodesc[] __initdata = {
45 {
46 .virtual = (unsigned long)S5P_VA_SYSTIMER,
47 .pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER),
48 .length = SZ_16K,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = (unsigned long)VA_VIC2,
52 .pfn = __phys_to_pfn(S5P6442_PA_VIC2),
53 .length = SZ_16K,
54 .type = MT_DEVICE,
55 }
56};
57
58static void s5p6442_idle(void)
59{
60 if (!need_resched())
61 cpu_do_idle();
62
63 local_irq_enable();
64}
65
66/* s5p6442_map_io
67 *
68 * register the standard cpu IO areas
69*/
70
71void __init s5p6442_map_io(void)
72{
73 iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc));
74}
75
76void __init s5p6442_init_clocks(int xtal)
77{
78 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
79
80 s3c24xx_register_baseclocks(xtal);
81 s5p_register_clocks(xtal);
82 s5p6442_register_clocks();
83 s5p6442_setup_clocks();
84}
85
86void __init s5p6442_init_irq(void)
87{
88 /* S5P6442 supports 3 VIC */
89 u32 vic[3];
90
91 /* VIC0, VIC1, and VIC2: some interrupt reserved */
92 vic[0] = 0x7fefffff;
93 vic[1] = 0X7f389c81;
94 vic[2] = 0X1bbbcfff;
95
96 s5p_init_irq(vic, ARRAY_SIZE(vic));
97}
98
99struct sysdev_class s5p6442_sysclass = {
100 .name = "s5p6442-core",
101};
102
103static struct sys_device s5p6442_sysdev = {
104 .cls = &s5p6442_sysclass,
105};
106
107static int __init s5p6442_core_init(void)
108{
109 return sysdev_class_register(&s5p6442_sysclass);
110}
111
112core_initcall(s5p6442_core_init);
113
114int __init s5p6442_init(void)
115{
116 printk(KERN_INFO "S5P6442: Initializing architecture\n");
117
118 /* set idle function */
119 pm_idle = s5p6442_idle;
120
121 return sysdev_register(&s5p6442_sysdev);
122}
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c
deleted file mode 100644
index 7a4e34720b7b..000000000000
--- a/arch/arm/mach-s5p6442/dev-audio.c
+++ /dev/null
@@ -1,197 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6442_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case 1:
27 s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2));
28 s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
29 s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
30 s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
31 s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
32 break;
33
34 case -1:
35 s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2));
36 s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
37 s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
38 s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
39 s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
40 break;
41
42 default:
43 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
44 return -EINVAL;
45 }
46
47 return 0;
48}
49
50static struct s3c_audio_pdata s3c_i2s_pdata = {
51 .cfg_gpio = s5p6442_cfg_i2s,
52};
53
54static struct resource s5p6442_iis0_resource[] = {
55 [0] = {
56 .start = S5P6442_PA_I2S0,
57 .end = S5P6442_PA_I2S0 + 0x100 - 1,
58 .flags = IORESOURCE_MEM,
59 },
60 [1] = {
61 .start = DMACH_I2S0_TX,
62 .end = DMACH_I2S0_TX,
63 .flags = IORESOURCE_DMA,
64 },
65 [2] = {
66 .start = DMACH_I2S0_RX,
67 .end = DMACH_I2S0_RX,
68 .flags = IORESOURCE_DMA,
69 },
70};
71
72struct platform_device s5p6442_device_iis0 = {
73 .name = "s3c64xx-iis-v4",
74 .id = -1,
75 .num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
76 .resource = s5p6442_iis0_resource,
77 .dev = {
78 .platform_data = &s3c_i2s_pdata,
79 },
80};
81
82static struct resource s5p6442_iis1_resource[] = {
83 [0] = {
84 .start = S5P6442_PA_I2S1,
85 .end = S5P6442_PA_I2S1 + 0x100 - 1,
86 .flags = IORESOURCE_MEM,
87 },
88 [1] = {
89 .start = DMACH_I2S1_TX,
90 .end = DMACH_I2S1_TX,
91 .flags = IORESOURCE_DMA,
92 },
93 [2] = {
94 .start = DMACH_I2S1_RX,
95 .end = DMACH_I2S1_RX,
96 .flags = IORESOURCE_DMA,
97 },
98};
99
100struct platform_device s5p6442_device_iis1 = {
101 .name = "s3c64xx-iis",
102 .id = 1,
103 .num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
104 .resource = s5p6442_iis1_resource,
105 .dev = {
106 .platform_data = &s3c_i2s_pdata,
107 },
108};
109
110/* PCM Controller platform_devices */
111
112static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
113{
114 switch (pdev->id) {
115 case 0:
116 s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3));
117 s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
118 s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
119 s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
120 s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
121 break;
122
123 case 1:
124 s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3));
125 s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
126 s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
127 s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
128 s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
129 break;
130
131 default:
132 printk(KERN_DEBUG "Invalid PCM Controller number!");
133 return -EINVAL;
134 }
135
136 return 0;
137}
138
139static struct s3c_audio_pdata s3c_pcm_pdata = {
140 .cfg_gpio = s5p6442_pcm_cfg_gpio,
141};
142
143static struct resource s5p6442_pcm0_resource[] = {
144 [0] = {
145 .start = S5P6442_PA_PCM0,
146 .end = S5P6442_PA_PCM0 + 0x100 - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = DMACH_PCM0_TX,
151 .end = DMACH_PCM0_TX,
152 .flags = IORESOURCE_DMA,
153 },
154 [2] = {
155 .start = DMACH_PCM0_RX,
156 .end = DMACH_PCM0_RX,
157 .flags = IORESOURCE_DMA,
158 },
159};
160
161struct platform_device s5p6442_device_pcm0 = {
162 .name = "samsung-pcm",
163 .id = 0,
164 .num_resources = ARRAY_SIZE(s5p6442_pcm0_resource),
165 .resource = s5p6442_pcm0_resource,
166 .dev = {
167 .platform_data = &s3c_pcm_pdata,
168 },
169};
170
171static struct resource s5p6442_pcm1_resource[] = {
172 [0] = {
173 .start = S5P6442_PA_PCM1,
174 .end = S5P6442_PA_PCM1 + 0x100 - 1,
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .start = DMACH_PCM1_TX,
179 .end = DMACH_PCM1_TX,
180 .flags = IORESOURCE_DMA,
181 },
182 [2] = {
183 .start = DMACH_PCM1_RX,
184 .end = DMACH_PCM1_RX,
185 .flags = IORESOURCE_DMA,
186 },
187};
188
189struct platform_device s5p6442_device_pcm1 = {
190 .name = "samsung-pcm",
191 .id = 1,
192 .num_resources = ARRAY_SIZE(s5p6442_pcm1_resource),
193 .resource = s5p6442_pcm1_resource,
194 .dev = {
195 .platform_data = &s3c_pcm_pdata,
196 },
197};
diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c
deleted file mode 100644
index e894651a88bd..000000000000
--- a/arch/arm/mach-s5p6442/dev-spi.c
+++ /dev/null
@@ -1,123 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5P6442_SPI_SRCCLK_PCLK] = "pclk",
25 [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
37{
38 switch (pdev->id) {
39 case 0:
40 s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
41 s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2));
42 s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2));
43 s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
44 s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP);
45 s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP);
46 break;
47
48 default:
49 dev_err(&pdev->dev, "Invalid SPI Controller number!");
50 return -EINVAL;
51 }
52
53 return 0;
54}
55
56static struct resource s5p6442_spi0_resource[] = {
57 [0] = {
58 .start = S5P6442_PA_SPI,
59 .end = S5P6442_PA_SPI + 0x100 - 1,
60 .flags = IORESOURCE_MEM,
61 },
62 [1] = {
63 .start = DMACH_SPI0_TX,
64 .end = DMACH_SPI0_TX,
65 .flags = IORESOURCE_DMA,
66 },
67 [2] = {
68 .start = DMACH_SPI0_RX,
69 .end = DMACH_SPI0_RX,
70 .flags = IORESOURCE_DMA,
71 },
72 [3] = {
73 .start = IRQ_SPI0,
74 .end = IRQ_SPI0,
75 .flags = IORESOURCE_IRQ,
76 },
77};
78
79static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
80 .cfg_gpio = s5p6442_spi_cfg_gpio,
81 .fifo_lvl_mask = 0x1ff,
82 .rx_lvl_offset = 15,
83};
84
85static u64 spi_dmamask = DMA_BIT_MASK(32);
86
87struct platform_device s5p6442_device_spi = {
88 .name = "s3c64xx-spi",
89 .id = 0,
90 .num_resources = ARRAY_SIZE(s5p6442_spi0_resource),
91 .resource = s5p6442_spi0_resource,
92 .dev = {
93 .dma_mask = &spi_dmamask,
94 .coherent_dma_mask = DMA_BIT_MASK(32),
95 .platform_data = &s5p6442_spi0_pdata,
96 },
97};
98
99void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
100{
101 struct s3c64xx_spi_info *pd;
102
103 /* Reject invalid configuration */
104 if (!num_cs || src_clk_nr < 0
105 || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
106 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
107 return;
108 }
109
110 switch (cntrlr) {
111 case 0:
112 pd = &s5p6442_spi0_pdata;
113 break;
114 default:
115 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
116 __func__, cntrlr);
117 return;
118 }
119
120 pd->num_cs = num_cs;
121 pd->src_clk_nr = src_clk_nr;
122 pd->src_clk_name = spi_src_clks[src_clk_nr];
123}
diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c
deleted file mode 100644
index ad4f8704b93d..000000000000
--- a/arch/arm/mach-s5p6442/dma.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h>
27#include <mach/irqs.h>
28
29#include <plat/s3c-pl330-pdata.h>
30
31static u64 dma_dmamask = DMA_BIT_MASK(32);
32
33static struct resource s5p6442_pdma_resource[] = {
34 [0] = {
35 .start = S5P6442_PA_PDMA,
36 .end = S5P6442_PA_PDMA + SZ_4K,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_PDMA,
41 .end = IRQ_PDMA,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
47 .peri = {
48 [0] = DMACH_UART0_RX,
49 [1] = DMACH_UART0_TX,
50 [2] = DMACH_UART1_RX,
51 [3] = DMACH_UART1_TX,
52 [4] = DMACH_UART2_RX,
53 [5] = DMACH_UART2_TX,
54 [6] = DMACH_MAX,
55 [7] = DMACH_MAX,
56 [8] = DMACH_MAX,
57 [9] = DMACH_I2S0_RX,
58 [10] = DMACH_I2S0_TX,
59 [11] = DMACH_I2S0S_TX,
60 [12] = DMACH_I2S1_RX,
61 [13] = DMACH_I2S1_TX,
62 [14] = DMACH_MAX,
63 [15] = DMACH_MAX,
64 [16] = DMACH_SPI0_RX,
65 [17] = DMACH_SPI0_TX,
66 [18] = DMACH_MAX,
67 [19] = DMACH_MAX,
68 [20] = DMACH_PCM0_RX,
69 [21] = DMACH_PCM0_TX,
70 [22] = DMACH_PCM1_RX,
71 [23] = DMACH_PCM1_TX,
72 [24] = DMACH_MAX,
73 [25] = DMACH_MAX,
74 [26] = DMACH_MAX,
75 [27] = DMACH_MSM_REQ0,
76 [28] = DMACH_MSM_REQ1,
77 [29] = DMACH_MSM_REQ2,
78 [30] = DMACH_MSM_REQ3,
79 [31] = DMACH_MAX,
80 },
81};
82
83static struct platform_device s5p6442_device_pdma = {
84 .name = "s3c-pl330",
85 .id = 1,
86 .num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
87 .resource = s5p6442_pdma_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5p6442_pdma_pdata,
92 },
93};
94
95static struct platform_device *s5p6442_dmacs[] __initdata = {
96 &s5p6442_device_pdma,
97};
98
99static int __init s5p6442_dma_init(void)
100{
101 platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
102
103 return 0;
104}
105arch_initcall(s5p6442_dma_init);
diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
deleted file mode 100644
index bb6536147ffb..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/debug-macro.S
+++ /dev/null
@@ -1,36 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16#include <plat/regs-serial.h>
17
18 .macro addruart, rx, rtmp
19 mrc p15, 0, \rx, c1, c0
20 tst \rx, #1
21 ldreq \rx, = S3C_PA_UART
22 ldrne \rx, = S3C_VA_UART
23#if CONFIG_DEBUG_S3C_UART != 0
24 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
25#endif
26 .endm
27
28#define fifo_full fifo_full_s5pv210
29#define fifo_level fifo_level_s5pv210
30
31/* include the reset of the code which will do the work, we're only
32 * compiling for a single cpu processor type so the default of s3c2440
33 * will be fine with us.
34 */
35
36#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6442/include/mach/dma.h b/arch/arm/mach-s5p6442/include/mach/dma.h
deleted file mode 100644
index 81209eb1409b..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/entry-macro.S b/arch/arm/mach-s5p6442/include/mach/entry-macro.S
deleted file mode 100644
index 6d574edbf1ae..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/entry-macro.S
+++ /dev/null
@@ -1,48 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Low-level IRQ helper macros for the Samsung S5P6442
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <asm/hardware/vic.h>
14#include <mach/map.h>
15#include <plat/irqs.h>
16
17 .macro disable_fiq
18 .endm
19
20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =VA_VIC0
22 .endm
23
24 .macro arch_ret_to_user, tmp1, tmp2
25 .endm
26
27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
28
29 @ check the vic0
30 mov \irqnr, # S5P_IRQ_OFFSET + 31
31 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
32 teq \irqstat, #0
33
34 @ otherwise try vic1
35 addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
36 addeq \irqnr, \irqnr, #32
37 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
38 teqeq \irqstat, #0
39
40 @ otherwise try vic2
41 addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
42 addeq \irqnr, \irqnr, #32
43 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
44 teqeq \irqstat, #0
45
46 clzne \irqstat, \irqstat
47 subne \irqnr, \irqnr, \irqstat
48 .endm
diff --git a/arch/arm/mach-s5p6442/include/mach/gpio.h b/arch/arm/mach-s5p6442/include/mach/gpio.h
deleted file mode 100644
index b8715df2fdab..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/gpio.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22#define S5P6442_GPIO_A0_NR (8)
23#define S5P6442_GPIO_A1_NR (2)
24#define S5P6442_GPIO_B_NR (4)
25#define S5P6442_GPIO_C0_NR (5)
26#define S5P6442_GPIO_C1_NR (5)
27#define S5P6442_GPIO_D0_NR (2)
28#define S5P6442_GPIO_D1_NR (6)
29#define S5P6442_GPIO_E0_NR (8)
30#define S5P6442_GPIO_E1_NR (5)
31#define S5P6442_GPIO_F0_NR (8)
32#define S5P6442_GPIO_F1_NR (8)
33#define S5P6442_GPIO_F2_NR (8)
34#define S5P6442_GPIO_F3_NR (6)
35#define S5P6442_GPIO_G0_NR (7)
36#define S5P6442_GPIO_G1_NR (7)
37#define S5P6442_GPIO_G2_NR (7)
38#define S5P6442_GPIO_H0_NR (8)
39#define S5P6442_GPIO_H1_NR (8)
40#define S5P6442_GPIO_H2_NR (8)
41#define S5P6442_GPIO_H3_NR (8)
42#define S5P6442_GPIO_J0_NR (8)
43#define S5P6442_GPIO_J1_NR (6)
44#define S5P6442_GPIO_J2_NR (8)
45#define S5P6442_GPIO_J3_NR (8)
46#define S5P6442_GPIO_J4_NR (5)
47
48/* GPIO bank numbers */
49
50/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
51 * space for debugging purposes so that any accidental
52 * change from one gpio bank to another can be caught.
53*/
54
55#define S5P6442_GPIO_NEXT(__gpio) \
56 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
57
58enum s5p_gpio_number {
59 S5P6442_GPIO_A0_START = 0,
60 S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0),
61 S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1),
62 S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B),
63 S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0),
64 S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1),
65 S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0),
66 S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1),
67 S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0),
68 S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1),
69 S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0),
70 S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1),
71 S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2),
72 S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3),
73 S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0),
74 S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1),
75 S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2),
76 S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0),
77 S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1),
78 S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2),
79 S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3),
80 S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0),
81 S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1),
82 S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2),
83 S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3),
84};
85
86/* S5P6442 GPIO number definitions. */
87#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr))
88#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr))
89#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr))
90#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr))
91#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr))
92#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr))
93#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr))
94#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr))
95#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr))
96#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr))
97#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr))
98#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr))
99#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr))
100#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr))
101#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr))
102#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr))
103#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr))
104#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr))
105#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr))
106#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr))
107#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr))
108#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr))
109#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr))
110#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr))
111#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr))
112
113/* the end of the S5P6442 specific gpios */
114#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1)
115#define S3C_GPIO_END S5P6442_GPIO_END
116
117/* define the number of gpios we need to the one after the GPJ4() range */
118#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \
119 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
120
121#include <asm-generic/gpio.h>
122
123#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/hardware.h b/arch/arm/mach-s5p6442/include/mach/hardware.h
deleted file mode 100644
index 8cd7b67b49d4..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h
deleted file mode 100644
index 5d2195ad0b67..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/io.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s5p6442/include/mach/io.h
2 *
3 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
4 *
5 * Default IO routines for S5P6442
6 */
7
8#ifndef __ASM_ARM_ARCH_IO_H
9#define __ASM_ARM_ARCH_IO_H
10
11/* No current ISA/PCI bus support. */
12#define __io(a) __typesafe_io(a)
13#define __mem_pci(a) (a)
14
15#define IO_SPACE_LIMIT (0xFFFFFFFF)
16
17#endif
diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h
deleted file mode 100644
index 3fbc6c3ad2da..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/irqs.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
20#define IRQ_BATF S5P_IRQ_VIC0(17)
21#define IRQ_MDMA S5P_IRQ_VIC0(18)
22#define IRQ_PDMA S5P_IRQ_VIC0(19)
23#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
24#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
25#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
26#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
27#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
28#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
29#define IRQ_WDT S5P_IRQ_VIC0(27)
30#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
31#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
32#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
33
34/* VIC1 */
35#define IRQ_PMU S5P_IRQ_VIC1(0)
36#define IRQ_ONENAND S5P_IRQ_VIC1(7)
37#define IRQ_UART0 S5P_IRQ_VIC1(10)
38#define IRQ_UART1 S5P_IRQ_VIC1(11)
39#define IRQ_UART2 S5P_IRQ_VIC1(12)
40#define IRQ_SPI0 S5P_IRQ_VIC1(15)
41#define IRQ_IIC S5P_IRQ_VIC1(19)
42#define IRQ_IIC1 S5P_IRQ_VIC1(20)
43#define IRQ_IIC2 S5P_IRQ_VIC1(21)
44#define IRQ_OTG S5P_IRQ_VIC1(24)
45#define IRQ_MSM S5P_IRQ_VIC1(25)
46#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
47#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
48#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
49#define IRQ_COMMRX S5P_IRQ_VIC1(29)
50#define IRQ_COMMTX S5P_IRQ_VIC1(30)
51
52/* VIC2 */
53#define IRQ_LCD0 S5P_IRQ_VIC2(0)
54#define IRQ_LCD1 S5P_IRQ_VIC2(1)
55#define IRQ_LCD2 S5P_IRQ_VIC2(2)
56#define IRQ_LCD3 S5P_IRQ_VIC2(3)
57#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
58#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
59#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
60#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
61#define IRQ_JPEG S5P_IRQ_VIC2(8)
62#define IRQ_3D S5P_IRQ_VIC2(10)
63#define IRQ_Mixer S5P_IRQ_VIC2(11)
64#define IRQ_MFC S5P_IRQ_VIC2(14)
65#define IRQ_TVENC S5P_IRQ_VIC2(15)
66#define IRQ_I2S0 S5P_IRQ_VIC2(16)
67#define IRQ_I2S1 S5P_IRQ_VIC2(17)
68#define IRQ_RP S5P_IRQ_VIC2(19)
69#define IRQ_PCM0 S5P_IRQ_VIC2(20)
70#define IRQ_PCM1 S5P_IRQ_VIC2(21)
71#define IRQ_ADC S5P_IRQ_VIC2(23)
72#define IRQ_PENDN S5P_IRQ_VIC2(24)
73#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
74#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
75#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
76#define IRQ_VIC_END S5P_IRQ_VIC2(31)
77
78#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1)
79
80#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
81#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE)
82
83/* Set the default NR_IRQS */
84
85#define NR_IRQS (IRQ_EINT(31) + 1)
86
87#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
deleted file mode 100644
index 281d256faafb..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/map.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P6442_PA_CHIPID (0xE0000000)
20#define S5P_PA_CHIPID S5P6442_PA_CHIPID
21
22#define S5P6442_PA_SYSCON (0xE0100000)
23#define S5P_PA_SYSCON S5P6442_PA_SYSCON
24
25#define S5P6442_PA_GPIO (0xE0200000)
26#define S5P_PA_GPIO S5P6442_PA_GPIO
27
28#define S5P6442_PA_VIC0 (0xE4000000)
29#define S5P_PA_VIC0 S5P6442_PA_VIC0
30
31#define S5P6442_PA_VIC1 (0xE4100000)
32#define S5P_PA_VIC1 S5P6442_PA_VIC1
33
34#define S5P6442_PA_VIC2 (0xE4200000)
35#define S5P_PA_VIC2 S5P6442_PA_VIC2
36
37#define S5P6442_PA_MDMA 0xE8000000
38#define S5P6442_PA_PDMA 0xE9000000
39
40#define S5P6442_PA_TIMER (0xEA000000)
41#define S5P_PA_TIMER S5P6442_PA_TIMER
42
43#define S5P6442_PA_SYSTIMER (0xEA100000)
44
45#define S5P6442_PA_WATCHDOG (0xEA200000)
46
47#define S5P6442_PA_UART (0xEC000000)
48
49#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0)
50#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400)
51#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800)
52#define S5P_SZ_UART SZ_256
53
54#define S5P6442_PA_IIC0 (0xEC100000)
55
56#define S5P6442_PA_SDRAM (0x20000000)
57#define S5P_PA_SDRAM S5P6442_PA_SDRAM
58
59#define S5P6442_PA_SPI 0xEC300000
60
61/* I2S */
62#define S5P6442_PA_I2S0 0xC0B00000
63#define S5P6442_PA_I2S1 0xF2200000
64
65/* PCM */
66#define S5P6442_PA_PCM0 0xF2400000
67#define S5P6442_PA_PCM1 0xF2500000
68
69/* compatibiltiy defines. */
70#define S3C_PA_WDT S5P6442_PA_WATCHDOG
71#define S3C_PA_UART S5P6442_PA_UART
72#define S3C_PA_IIC S5P6442_PA_IIC0
73
74#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h
deleted file mode 100644
index 9ddd877ba2ea..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/memory.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE SZ_8M
18
19#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
deleted file mode 100644
index 2724b37def31..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
12 *
13 * S5P6442 - pwm clock and timer support
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#ifndef __ASM_ARCH_PWMCLK_H
21#define __ASM_ARCH_PWMCLK_H __FILE__
22
23/**
24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
26 *
27 * Return true if the given configuration from TCFG1 is a TCLK instead
28 * any of the TDIV clocks.
29 */
30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
31{
32 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
33}
34
35/**
36 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
37 * @tcfg1: The tcfg1 setting, shifted down.
38 *
39 * Get the divisor value for the given tcfg1 setting. We assume the
40 * caller has already checked to see if this is not a TCLK source.
41 */
42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
43{
44 return 1 << tcfg1;
45}
46
47/**
48 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
49 *
50 * Return true if we have a /1 in the tdiv setting.
51 */
52static inline unsigned int pwm_tdiv_has_div1(void)
53{
54 return 1;
55}
56
57/**
58 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
59 * @div: The divisor to calculate the bit information for.
60 *
61 * Turn a divisor into the necessary bit field for TCFG1.
62 */
63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
64{
65 return ilog2(div);
66}
67
68#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
69
70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
deleted file mode 100644
index d8360b5d4ece..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h
+++ /dev/null
@@ -1,103 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
23#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
24
25#define S5P_APLL_CON S5P_CLKREG(0x100)
26#define S5P_MPLL_CON S5P_CLKREG(0x108)
27#define S5P_EPLL_CON S5P_CLKREG(0x110)
28#define S5P_VPLL_CON S5P_CLKREG(0x120)
29
30#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
31#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
32#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
33#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
34#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
35#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
36#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
37
38#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
39#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
40
41#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
42#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
43#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
44#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
45#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
46#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
47#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
48
49#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
50
51/* CLK_OUT */
52#define S5P_CLK_OUT_SHIFT (12)
53#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT)
54#define S5P_CLK_OUT S5P_CLKREG(0x500)
55
56#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000)
57#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004)
58
59#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100)
60#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104)
61
62#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
63
64/* Register Bit definition */
65#define S5P_EPLL_EN (1<<31)
66#define S5P_EPLL_MASK 0xffffffff
67#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
68
69/* CLKDIV0 */
70#define S5P_CLKDIV0_APLL_SHIFT (0)
71#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
72#define S5P_CLKDIV0_A2M_SHIFT (4)
73#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
74#define S5P_CLKDIV0_D0CLK_SHIFT (16)
75#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
76#define S5P_CLKDIV0_P0CLK_SHIFT (20)
77#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
78#define S5P_CLKDIV0_D1CLK_SHIFT (24)
79#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
80#define S5P_CLKDIV0_P1CLK_SHIFT (28)
81#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
82
83/* Clock MUX status Registers */
84#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0)
85#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
86#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4)
87#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
88#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8)
89#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
90#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12)
91#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
92#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16)
93#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
94#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20)
95#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
96#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24)
97#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
98#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24)
99#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
100#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28)
101#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
102
103#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-irq.h b/arch/arm/mach-s5p6442/include/mach/regs-irq.h
deleted file mode 100644
index 73782b52a83b..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/regs-irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <asm/hardware/vic.h>
17#include <mach/map.h>
18
19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
deleted file mode 100644
index 7fd88205a97c..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5P6442_PLAT_SPI_CLKS_H
12#define __S5P6442_PLAT_SPI_CLKS_H __FILE__
13
14#define S5P6442_SPI_SRCCLK_PCLK 0
15#define S5P6442_SPI_SRCCLK_SCLK 1
16
17#endif /* __S5P6442_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h
deleted file mode 100644
index c30c1cc1b97e..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/system.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16#include <plat/system-reset.h>
17
18static void arch_idle(void)
19{
20 /* nothing here yet */
21}
22
23#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/tick.h b/arch/arm/mach-s5p6442/include/mach/tick.h
deleted file mode 100644
index e1d4cabf8297..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/tick.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/tick.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/tick.h
7 *
8 * S5P6442 - Timer tick support definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_TICK_H
16#define __ASM_ARCH_TICK_H __FILE__
17
18static inline u32 s3c24xx_ostimer_pending(void)
19{
20 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
21 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
22}
23
24#define TICK_MAX (0xffffffff)
25
26#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/timex.h b/arch/arm/mach-s5p6442/include/mach/timex.h
deleted file mode 100644
index ff8f2fcadeb7..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s5p6442/include/mach/timex.h
2 *
3 * Copyright (c) 2003-2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S5P6442 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
17 * a variable is useless. It seems as long as we make our timers an
18 * exact multiple of HZ, any value that makes a 1->1 correspondence
19 * for the time conversion functions to/from jiffies is acceptable.
20*/
21
22#define CLOCK_TICK_RATE 12000000
23
24#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/uncompress.h b/arch/arm/mach-s5p6442/include/mach/uncompress.h
deleted file mode 100644
index 5ac7cbeeb987..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22}
23
24#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
deleted file mode 100644
index f5c83f02c18e..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s5p6442/include/mach/vmalloc.h
2 *
3 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S5P6442 vmalloc definition
10*/
11
12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H
14
15#define VMALLOC_END 0xE0000000UL
16
17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6442/init.c b/arch/arm/mach-s5p6442/init.c
deleted file mode 100644
index 1874bdb71e1d..000000000000
--- a/arch/arm/mach-s5p6442/init.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/s5p6442-init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15
16#include <plat/cpu.h>
17#include <plat/devs.h>
18#include <plat/s5p6442.h>
19#include <plat/regs-serial.h>
20
21static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = {
22 [0] = {
23 .name = "pclk",
24 .divisor = 1,
25 .min_baud = 0,
26 .max_baud = 0,
27 },
28};
29
30/* uart registration process */
31void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
32{
33 struct s3c2410_uartcfg *tcfg = cfg;
34 u32 ucnt;
35
36 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
37 if (!tcfg->clocks) {
38 tcfg->clocks = s5p6442_serial_clocks;
39 tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks);
40 }
41 }
42
43 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
44}
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
deleted file mode 100644
index 8d8d04272f85..000000000000
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15
16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
18#include <asm/setup.h>
19#include <asm/mach-types.h>
20
21#include <mach/map.h>
22#include <mach/regs-clock.h>
23
24#include <plat/regs-serial.h>
25#include <plat/s5p6442.h>
26#include <plat/devs.h>
27#include <plat/cpu.h>
28
29/* Following are default values for UCON, ULCON and UFCON UART registers */
30#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
31 S3C2410_UCON_RXILEVEL | \
32 S3C2410_UCON_TXIRQMODE | \
33 S3C2410_UCON_RXIRQMODE | \
34 S3C2410_UCON_RXFIFO_TOI | \
35 S3C2443_UCON_RXERR_IRQEN)
36
37#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
38
39#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
40 S5PV210_UFCON_TXTRIG4 | \
41 S5PV210_UFCON_RXTRIG4)
42
43static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
44 [0] = {
45 .hwport = 0,
46 .flags = 0,
47 .ucon = SMDK6442_UCON_DEFAULT,
48 .ulcon = SMDK6442_ULCON_DEFAULT,
49 .ufcon = SMDK6442_UFCON_DEFAULT,
50 },
51 [1] = {
52 .hwport = 1,
53 .flags = 0,
54 .ucon = SMDK6442_UCON_DEFAULT,
55 .ulcon = SMDK6442_ULCON_DEFAULT,
56 .ufcon = SMDK6442_UFCON_DEFAULT,
57 },
58 [2] = {
59 .hwport = 2,
60 .flags = 0,
61 .ucon = SMDK6442_UCON_DEFAULT,
62 .ulcon = SMDK6442_ULCON_DEFAULT,
63 .ufcon = SMDK6442_UFCON_DEFAULT,
64 },
65};
66
67static struct platform_device *smdk6442_devices[] __initdata = {
68 &s5p6442_device_iis0,
69 &s3c_device_wdt,
70};
71
72static void __init smdk6442_map_io(void)
73{
74 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
75 s3c24xx_init_clocks(12000000);
76 s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs));
77}
78
79static void __init smdk6442_machine_init(void)
80{
81 platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
82}
83
84MACHINE_START(SMDK6442, "SMDK6442")
85 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
86 .phys_io = S3C_PA_UART & 0xfff00000,
87 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
88 .boot_params = S5P_PA_SDRAM + 0x100,
89 .init_irq = s5p6442_init_irq,
90 .map_io = smdk6442_map_io,
91 .init_machine = smdk6442_machine_init,
92 .timer = &s3c24xx_timer,
93MACHINE_END
diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c
deleted file mode 100644
index 662695dd7761..000000000000
--- a/arch/arm/mach-s5p6442/setup-i2c0.c
+++ /dev/null
@@ -1,25 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <plat/iic.h>
21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{
24 /* Will be populated later */
25}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 18:43:36 -0400