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authorThomas Abraham <thomas.ab@samsung.com>2010-05-12 20:27:49 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-12 21:42:48 -0400
commit39b7781b16614c65a53f275ff63440ea806230e2 (patch)
tree8d892c3c6961803f6314a4a63bd29663d3f1c64a /arch/arm/mach-s5p6440
parent213907dc1b974019f5eb9c94a1c62b11a515564c (diff)
ARM: S5P6440: Rename clkset_mmc_spi to clkset_group1
The clock source options avaialable in the clkset_mmc_spi are applicable to clocks such as sclk_post, sclk_dispcon and sclk_fimgvg. So this set is renamed as clkset_group1 to indicate that it can be used as clock sources for other clocks and not just for sclk_spi and sclk_mmc clocks. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5p6440')
-rw-r--r--arch/arm/mach-s5p6440/clock.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
index 26b02d43a252..b47f77d9c849 100644
--- a/arch/arm/mach-s5p6440/clock.c
+++ b/arch/arm/mach-s5p6440/clock.c
@@ -595,15 +595,15 @@ static struct clk clk_pcm_cd = {
595 .id = -1, 595 .id = -1,
596}; 596};
597 597
598static struct clk *clkset_spi_mmc_list[] = { 598static struct clk *clkset_group1_list[] = {
599 &clk_mout_epll.clk, 599 &clk_mout_epll.clk,
600 &clk_dout_mpll.clk, 600 &clk_dout_mpll.clk,
601 &clk_fin_epll, 601 &clk_fin_epll,
602}; 602};
603 603
604static struct clksrc_sources clkset_spi_mmc = { 604static struct clksrc_sources clkset_group1 = {
605 .sources = clkset_spi_mmc_list, 605 .sources = clkset_group1_list,
606 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), 606 .nr_sources = ARRAY_SIZE(clkset_group1_list),
607}; 607};
608 608
609static struct clk *clkset_uart_list[] = { 609static struct clk *clkset_uart_list[] = {
@@ -624,7 +624,7 @@ static struct clksrc_clk clksrcs[] = {
624 .ctrlbit = S5P_CLKCON_SCLK0_MMC0, 624 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
625 .enable = s5p6440_sclk_ctrl, 625 .enable = s5p6440_sclk_ctrl,
626 }, 626 },
627 .sources = &clkset_spi_mmc, 627 .sources = &clkset_group1,
628 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, 628 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
629 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, 629 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
630 }, { 630 }, {
@@ -634,7 +634,7 @@ static struct clksrc_clk clksrcs[] = {
634 .ctrlbit = S5P_CLKCON_SCLK0_MMC1, 634 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
635 .enable = s5p6440_sclk_ctrl, 635 .enable = s5p6440_sclk_ctrl,
636 }, 636 },
637 .sources = &clkset_spi_mmc, 637 .sources = &clkset_group1,
638 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, 638 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
639 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, 639 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
640 }, { 640 }, {
@@ -644,7 +644,7 @@ static struct clksrc_clk clksrcs[] = {
644 .ctrlbit = S5P_CLKCON_SCLK0_MMC2, 644 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
645 .enable = s5p6440_sclk_ctrl, 645 .enable = s5p6440_sclk_ctrl,
646 }, 646 },
647 .sources = &clkset_spi_mmc, 647 .sources = &clkset_group1,
648 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, 648 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
649 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, 649 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
650 }, { 650 }, {
@@ -664,7 +664,7 @@ static struct clksrc_clk clksrcs[] = {
664 .ctrlbit = S5P_CLKCON_SCLK0_SPI0, 664 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
665 .enable = s5p6440_sclk_ctrl, 665 .enable = s5p6440_sclk_ctrl,
666 }, 666 },
667 .sources = &clkset_spi_mmc, 667 .sources = &clkset_group1,
668 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, 668 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
669 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 669 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
670 }, { 670 }, {
@@ -674,7 +674,7 @@ static struct clksrc_clk clksrcs[] = {
674 .ctrlbit = S5P_CLKCON_SCLK0_SPI1, 674 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
675 .enable = s5p6440_sclk_ctrl, 675 .enable = s5p6440_sclk_ctrl,
676 }, 676 },
677 .sources = &clkset_spi_mmc, 677 .sources = &clkset_group1,
678 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, 678 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
679 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, 679 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
680 } 680 }