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authorBen Dooks <ben-linux@fluff.org>2011-06-01 05:44:51 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 10:12:22 -0400
commitc17afc0aa69615b4c2250b6476431c4d601890a0 (patch)
tree504bc7090344121647b5ff21d1b7a0cf77b3a0f3 /arch/arm/mach-s3c64xx
parent620917de59eeb934b9f8cf35cc2d95c1ac8ed0fc (diff)
ARM: S3C64XX: Ensure VIC based IRQs can be resumed from
Any interrupts based off either of the onboard VICs cannot be resumed from any more as it seems set_irq_wake() is now checking the error code returned from the low level handlers and not setting the wake-state on the interrupt if this fails. Ensure that we make the interrupts we can resume from available on the VIC and then do a pre-sleep mask of all the VIC interrupts as the wakeup is handled by a seperate block. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pm-core.h2
-rw-r--r--arch/arm/mach-s3c64xx/irq.c12
2 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 1e9f20f0bb7b..4ed0f582d222 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
53 * the IRQ wake controls depending on the CPU we are running on */ 53 * the IRQ wake controls depending on the CPU we are running on */
54 54
55#define s3c_irqwake_eintallow ((1 << 28) - 1) 55#define s3c_irqwake_eintallow ((1 << 28) - 1)
56#define s3c_irqwake_intallow (0) 56#define s3c_irqwake_intallow (~0)
57 57
58static inline void s3c_pm_arch_update_uart(void __iomem *regs, 58static inline void s3c_pm_arch_update_uart(void __iomem *regs,
59 struct pm_uart_save *save) 59 struct pm_uart_save *save)
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 97660c8141ae..75d9a0e49193 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
48 }, 48 },
49}; 49};
50 50
51/* setup the sources the vic should advertise resume for, even though it
52 * is not doing the wake (set_irq_wake needs to be valid) */
53#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
54#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
55 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
56 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
57 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
58 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
51 59
52void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) 60void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
53{ 61{
54 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 62 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
55 63
56 /* initialise the pair of VICs */ 64 /* initialise the pair of VICs */
57 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); 65 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
58 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); 66 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
59 67
60 /* add the timer sub-irqs */ 68 /* add the timer sub-irqs */
61 s3c_init_vic_timer_irq(5, IRQ_TIMER0); 69 s3c_init_vic_timer_irq(5, IRQ_TIMER0);