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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-05 21:18:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-05 21:18:05 -0400
commit7abec10c623d9e0416dab6919a0ea22e6283516b (patch)
tree83aa79c369e99c4fc60eea91ebd399b7689b312e /arch/arm/mach-s3c64xx
parent0de9adf284ec20454ecf37ffd98e7e98ba7292d6 (diff)
parentcfaf8fc5b59527281e9ddc2e0e04e1127936e17f (diff)
Merge branch 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc
* 'next/cleanup3' of git://git.linaro.org/people/arnd/arm-soc: (79 commits) ARM: SAMSUNG: Move fimc plat. device from board files to plat-samsung ARM: SAMSUNG: Cleanup resources by using macro ARM: SAMSUNG: Cleanup plat-samsung/devs.c and devs.h ARM: S5P: To merge devs.c files to one devs.c ARM: S3C64XX: To merge devs.c files to one devs.c ARM: S3C24XX: To merge s3c24xx devs.c files to one devs.c ARM: S5P64X0: Add Power Management support ARM: S5P: Make the sleep code common for S5P series SoCs ARM: S5P: Make the common S5P PM code conditionally compile ARM: SAMSUNG: Move S5P header files to plat-samsung ARM: SAMSUNG: Move S3C24XX header files to plat-samsung ARM: SAMSUNG: Moving each SoC support header files ARM: SAMSUNG: Consolidate plat/pll.h ARM: SAMSUNG: Consolidate plat/pwm-clock.h ARM: SAMSUNG: Cleanup mach/clkdev.h ARM: SAMSUNG: remove sdhci default configuration setup platform helper ARM: EXYNOS4: Add FIMC device on SMDKV310 board ARM: EXYNOS4: Add header file protection macros ARM: EXYNOS4: Add usb ehci device to the SMDKV310 ARM: S3C2443: Add hsspi-clock from pclk and rename S3C2443 hsspi sclk ... Fix up conflicts in - arch/arm/mach-exynos4/{Kconfig,clock.c} ARM_CPU_SUSPEND, various random device tables (gah!) - drivers/gpio/Makefile sa1100 gpio added, samsung gpio drivers merged
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig1
-rw-r--r--arch/arm/mach-s3c64xx/Makefile5
-rw-r--r--arch/arm/mach-s3c64xx/clock.c13
-rw-r--r--arch/arm/mach-s3c64xx/cpu.c4
-rw-r--r--arch/arm/mach-s3c64xx/dev-onenand1.c53
-rw-r--r--arch/arm/mach-s3c64xx/dma.c2
-rw-r--r--arch/arm/mach-s3c64xx/gpiolib.c290
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/crag6410.h23
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pll.h45
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pm-core.h2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pwm-clock.h56
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-sys.h3
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/s3c6400.h36
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/s3c6410.h29
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410-module.c182
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c108
-rw-r--r--arch/arm/mach-s3c64xx/mach-hmt.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-mini6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-ncp.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-real6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq5.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smartq7.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6400.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c2
-rw-r--r--arch/arm/mach-s3c64xx/pm.c4
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c2
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c4
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci.c48
30 files changed, 267 insertions, 668 deletions
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f057b6ae4f90..5552e048c2be 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410
288 select S3C_DEV_RTC 288 select S3C_DEV_RTC
289 select S3C64XX_DEV_SPI 289 select S3C64XX_DEV_SPI
290 select S3C24XX_GPIO_EXTRA128 290 select S3C24XX_GPIO_EXTRA128
291 select I2C
291 help 292 help
292 Machine support for the Wolfson Cragganmore S3C6410 variant. 293 Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 61b4034a0c22..cfc0b9941808 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -13,7 +13,6 @@ obj- :=
13# Core files 13# Core files
14obj-y += cpu.o 14obj-y += cpu.o
15obj-y += clock.o 15obj-y += clock.o
16obj-y += gpiolib.o
17 16
18# Core support for S3C6400 system 17# Core support for S3C6400 system
19 18
@@ -55,12 +54,10 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
55obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o 54obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
56obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o 55obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
57obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o 56obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
58obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o 57obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
59 58
60# device support 59# device support
61 60
62obj-y += dev-uart.o 61obj-y += dev-uart.o
63obj-y += dev-audio.o 62obj-y += dev-audio.o
64obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o 63obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
65obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o
66obj-$(CONFIG_S3C64XX_DEV_ONENAND1) += dev-onenand1.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 8cf39e33579e..39c238d7a3dc 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -25,13 +25,13 @@
25 25
26#include <mach/regs-sys.h> 26#include <mach/regs-sys.h>
27#include <mach/regs-clock.h> 27#include <mach/regs-clock.h>
28#include <mach/pll.h>
29 28
30#include <plat/cpu.h> 29#include <plat/cpu.h>
31#include <plat/devs.h> 30#include <plat/devs.h>
32#include <plat/cpu-freq.h> 31#include <plat/cpu-freq.h>
33#include <plat/clock.h> 32#include <plat/clock.h>
34#include <plat/clock-clksrc.h> 33#include <plat/clock-clksrc.h>
34#include <plat/pll.h>
35 35
36/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call 36/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual. 37 * ext_xtal_mux for want of an actual name from the manual.
@@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
735 /* For now assume the mux always selects the crystal */ 735 /* For now assume the mux always selects the crystal */
736 clk_ext_xtal_mux.parent = xtal_clk; 736 clk_ext_xtal_mux.parent = xtal_clk;
737 737
738 epll = s3c6400_get_epll(xtal); 738 epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
739 __raw_readl(S3C_EPLL_CON1));
739 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); 740 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
740 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); 741 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
741 742
@@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
744 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", 745 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
745 apll, mpll, epll); 746 apll, mpll, epll);
746 747
747 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); 748 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
749 /* Synchronous mode */
750 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
751 else
752 /* Asynchronous mode */
753 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
754
748 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); 755 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
749 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); 756 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
750 757
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index c7047838e112..de085b798aa4 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -34,8 +34,8 @@
34#include <plat/devs.h> 34#include <plat/devs.h>
35#include <plat/clock.h> 35#include <plat/clock.h>
36 36
37#include <mach/s3c6400.h> 37#include <plat/s3c6400.h>
38#include <mach/s3c6410.h> 38#include <plat/s3c6410.h>
39 39
40/* table of supported CPUs */ 40/* table of supported CPUs */
41 41
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c
deleted file mode 100644
index 999f9e17a1e4..000000000000
--- a/arch/arm/mach-s3c64xx/dev-onenand1.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * linux/arch/arm/mach-s3c64xx/dev-onenand1.c
3 *
4 * Copyright (c) 2008-2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * S3C64XX series device definition for OneNAND devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/onenand.h>
18
19#include <mach/irqs.h>
20#include <mach/map.h>
21
22#include <plat/devs.h>
23
24static struct resource s3c64xx_onenand1_resources[] = {
25 [0] = {
26 .start = S3C64XX_PA_ONENAND1,
27 .end = S3C64XX_PA_ONENAND1 + 0x400 - 1,
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .start = S3C64XX_PA_ONENAND1_BUF,
32 .end = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 [2] = {
36 .start = IRQ_ONENAND1,
37 .end = IRQ_ONENAND1,
38 .flags = IORESOURCE_IRQ,
39 },
40};
41
42struct platform_device s3c64xx_device_onenand1 = {
43 .name = "samsung-onenand",
44 .id = 1,
45 .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
46 .resource = s3c64xx_onenand1_resources,
47};
48
49void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
50{
51 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
52 &s3c64xx_device_onenand1);
53}
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 67c97fab62fd..17d62f4f8204 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
740 } 740 }
741 741
742 /* Set all DMA configuration to be DMA, not SDMA */ 742 /* Set all DMA configuration to be DMA, not SDMA */
743 writel(0xffffff, S3C_SYSREG(0x110)); 743 writel(0xffffff, S3C64XX_SDMA_SEL);
744 744
745 /* Register standard DMA controllers */ 745 /* Register standard DMA controllers */
746 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); 746 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
deleted file mode 100644
index 92b09085caaa..000000000000
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ /dev/null
@@ -1,290 +0,0 @@
1/* arch/arm/plat-s3c64xx/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIOlib support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19
20#include <mach/map.h>
21
22#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25#include <mach/regs-gpio.h>
26
27/* GPIO bank summary:
28 *
29 * Bank GPIOs Style SlpCon ExtInt Group
30 * A 8 4Bit Yes 1
31 * B 7 4Bit Yes 1
32 * C 8 4Bit Yes 2
33 * D 5 4Bit Yes 3
34 * E 5 4Bit Yes None
35 * F 16 2Bit Yes 4 [1]
36 * G 7 4Bit Yes 5
37 * H 10 4Bit[2] Yes 6
38 * I 16 2Bit Yes None
39 * J 12 2Bit Yes None
40 * K 16 4Bit[2] No None
41 * L 15 4Bit[2] No None
42 * M 6 4Bit No IRQ_EINT
43 * N 16 2Bit No IRQ_EINT
44 * O 16 2Bit Yes 7
45 * P 15 2Bit Yes 8
46 * Q 9 2Bit Yes 9
47 *
48 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
49 * [2] BANK has two control registers, GPxCON0 and GPxCON1
50 */
51
52static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
53 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
54 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
55 .set_pull = s3c_gpio_setpull_updown,
56 .get_pull = s3c_gpio_getpull_updown,
57};
58
59static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
60 .cfg_eint = 7,
61 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
62 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
63 .set_pull = s3c_gpio_setpull_updown,
64 .get_pull = s3c_gpio_getpull_updown,
65};
66
67static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
68 .cfg_eint = 3,
69 .get_config = s3c_gpio_getcfg_s3c64xx_4bit,
70 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
71 .set_pull = s3c_gpio_setpull_updown,
72 .get_pull = s3c_gpio_getpull_updown,
73};
74
75static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
76{
77 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
78}
79
80static struct s3c_gpio_chip gpio_4bit[] = {
81 {
82 .base = S3C64XX_GPA_BASE,
83 .config = &gpio_4bit_cfg_eint0111,
84 .chip = {
85 .base = S3C64XX_GPA(0),
86 .ngpio = S3C64XX_GPIO_A_NR,
87 .label = "GPA",
88 },
89 }, {
90 .base = S3C64XX_GPB_BASE,
91 .config = &gpio_4bit_cfg_eint0111,
92 .chip = {
93 .base = S3C64XX_GPB(0),
94 .ngpio = S3C64XX_GPIO_B_NR,
95 .label = "GPB",
96 },
97 }, {
98 .base = S3C64XX_GPC_BASE,
99 .config = &gpio_4bit_cfg_eint0111,
100 .chip = {
101 .base = S3C64XX_GPC(0),
102 .ngpio = S3C64XX_GPIO_C_NR,
103 .label = "GPC",
104 },
105 }, {
106 .base = S3C64XX_GPD_BASE,
107 .config = &gpio_4bit_cfg_eint0111,
108 .chip = {
109 .base = S3C64XX_GPD(0),
110 .ngpio = S3C64XX_GPIO_D_NR,
111 .label = "GPD",
112 },
113 }, {
114 .base = S3C64XX_GPE_BASE,
115 .config = &gpio_4bit_cfg_noint,
116 .chip = {
117 .base = S3C64XX_GPE(0),
118 .ngpio = S3C64XX_GPIO_E_NR,
119 .label = "GPE",
120 },
121 }, {
122 .base = S3C64XX_GPG_BASE,
123 .config = &gpio_4bit_cfg_eint0111,
124 .chip = {
125 .base = S3C64XX_GPG(0),
126 .ngpio = S3C64XX_GPIO_G_NR,
127 .label = "GPG",
128 },
129 }, {
130 .base = S3C64XX_GPM_BASE,
131 .config = &gpio_4bit_cfg_eint0011,
132 .chip = {
133 .base = S3C64XX_GPM(0),
134 .ngpio = S3C64XX_GPIO_M_NR,
135 .label = "GPM",
136 .to_irq = s3c64xx_gpio2int_gpm,
137 },
138 },
139};
140
141static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
142{
143 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
144}
145
146static struct s3c_gpio_chip gpio_4bit2[] = {
147 {
148 .base = S3C64XX_GPH_BASE + 0x4,
149 .config = &gpio_4bit_cfg_eint0111,
150 .chip = {
151 .base = S3C64XX_GPH(0),
152 .ngpio = S3C64XX_GPIO_H_NR,
153 .label = "GPH",
154 },
155 }, {
156 .base = S3C64XX_GPK_BASE + 0x4,
157 .config = &gpio_4bit_cfg_noint,
158 .chip = {
159 .base = S3C64XX_GPK(0),
160 .ngpio = S3C64XX_GPIO_K_NR,
161 .label = "GPK",
162 },
163 }, {
164 .base = S3C64XX_GPL_BASE + 0x4,
165 .config = &gpio_4bit_cfg_eint0011,
166 .chip = {
167 .base = S3C64XX_GPL(0),
168 .ngpio = S3C64XX_GPIO_L_NR,
169 .label = "GPL",
170 .to_irq = s3c64xx_gpio2int_gpl,
171 },
172 },
173};
174
175static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
176 .set_config = s3c_gpio_setcfg_s3c24xx,
177 .get_config = s3c_gpio_getcfg_s3c24xx,
178 .set_pull = s3c_gpio_setpull_updown,
179 .get_pull = s3c_gpio_getpull_updown,
180};
181
182static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
183 .cfg_eint = 2,
184 .set_config = s3c_gpio_setcfg_s3c24xx,
185 .get_config = s3c_gpio_getcfg_s3c24xx,
186 .set_pull = s3c_gpio_setpull_updown,
187 .get_pull = s3c_gpio_getpull_updown,
188};
189
190static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
191 .cfg_eint = 3,
192 .set_config = s3c_gpio_setcfg_s3c24xx,
193 .get_config = s3c_gpio_getcfg_s3c24xx,
194 .set_pull = s3c_gpio_setpull_updown,
195 .get_pull = s3c_gpio_getpull_updown,
196};
197
198static struct s3c_gpio_chip gpio_2bit[] = {
199 {
200 .base = S3C64XX_GPF_BASE,
201 .config = &gpio_2bit_cfg_eint11,
202 .chip = {
203 .base = S3C64XX_GPF(0),
204 .ngpio = S3C64XX_GPIO_F_NR,
205 .label = "GPF",
206 },
207 }, {
208 .base = S3C64XX_GPI_BASE,
209 .config = &gpio_2bit_cfg_noint,
210 .chip = {
211 .base = S3C64XX_GPI(0),
212 .ngpio = S3C64XX_GPIO_I_NR,
213 .label = "GPI",
214 },
215 }, {
216 .base = S3C64XX_GPJ_BASE,
217 .config = &gpio_2bit_cfg_noint,
218 .chip = {
219 .base = S3C64XX_GPJ(0),
220 .ngpio = S3C64XX_GPIO_J_NR,
221 .label = "GPJ",
222 },
223 }, {
224 .base = S3C64XX_GPN_BASE,
225 .irq_base = IRQ_EINT(0),
226 .config = &gpio_2bit_cfg_eint10,
227 .chip = {
228 .base = S3C64XX_GPN(0),
229 .ngpio = S3C64XX_GPIO_N_NR,
230 .label = "GPN",
231 .to_irq = samsung_gpiolib_to_irq,
232 },
233 }, {
234 .base = S3C64XX_GPO_BASE,
235 .config = &gpio_2bit_cfg_eint11,
236 .chip = {
237 .base = S3C64XX_GPO(0),
238 .ngpio = S3C64XX_GPIO_O_NR,
239 .label = "GPO",
240 },
241 }, {
242 .base = S3C64XX_GPP_BASE,
243 .config = &gpio_2bit_cfg_eint11,
244 .chip = {
245 .base = S3C64XX_GPP(0),
246 .ngpio = S3C64XX_GPIO_P_NR,
247 .label = "GPP",
248 },
249 }, {
250 .base = S3C64XX_GPQ_BASE,
251 .config = &gpio_2bit_cfg_eint11,
252 .chip = {
253 .base = S3C64XX_GPQ(0),
254 .ngpio = S3C64XX_GPIO_Q_NR,
255 .label = "GPQ",
256 },
257 },
258};
259
260static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
261{
262 chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
263}
264
265static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
266 int nr_chips,
267 void (*fn)(struct s3c_gpio_chip *))
268{
269 for (; nr_chips > 0; nr_chips--, chips++) {
270 if (fn)
271 (fn)(chips);
272 s3c_gpiolib_add(chips);
273 }
274}
275
276static __init int s3c64xx_gpiolib_init(void)
277{
278 s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
279 samsung_gpiolib_add_4bit);
280
281 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
282 samsung_gpiolib_add_4bit2);
283
284 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
285 s3c64xx_gpiolib_add_2bit);
286
287 return 0;
288}
289
290core_initcall(s3c64xx_gpiolib_init);
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
new file mode 100644
index 000000000000..be9074e17dfd
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -0,0 +1,23 @@
1/* Cragganmore 6410 shared definitions
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef MACH_CRAG6410_H
12#define MACH_CRAG6410_H
13
14#include <linux/gpio.h>
15
16#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
17#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
18
19#define PCA935X_GPIO_BASE GPIO_BOARD_START
20#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
21#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
22
23#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
deleted file mode 100644
index 5ef0bb698ee0..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/pll.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/* arch/arm/plat-s3c64xx/include/plat/pll.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX PLL code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
16#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
17#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
18#define S3C6400_PLL_MDIV_SHIFT (16)
19#define S3C6400_PLL_PDIV_SHIFT (8)
20#define S3C6400_PLL_SDIV_SHIFT (0)
21
22#include <asm/div64.h>
23#include <plat/pll6553x.h>
24
25static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
26 u32 pllcon)
27{
28 u32 mdiv, pdiv, sdiv;
29 u64 fvco = baseclk;
30
31 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
32 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
33 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
34
35 fvco *= mdiv;
36 do_div(fvco, (pdiv << sdiv));
37
38 return (unsigned long)fvco;
39}
40
41static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
42{
43 return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
44 __raw_readl(S3C_EPLL_CON1));
45}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 38659bebe4b1..fcf3dcabb694 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void)
104 __raw_writel(0, S3C64XX_SLPEN); 104 __raw_writel(0, S3C64XX_SLPEN);
105} 105}
106 106
107static inline void s3c_pm_saved_gpios(void) 107static inline void samsung_pm_saved_gpios(void)
108{ 108{
109 /* turn on the sleep mode and keep it there, as it seems that during 109 /* turn on the sleep mode and keep it there, as it seems that during
110 * suspend the xCON registers get re-set and thus you can end up with 110 * suspend the xCON registers get re-set and thus you can end up with
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
deleted file mode 100644
index b25bedee0d52..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64xx - pwm clock and timer support
9 */
10
11/**
12 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
13 * @tcfg: The timer TCFG1 register bits shifted down to 0.
14 *
15 * Return true if the given configuration from TCFG1 is a TCLK instead
16 * any of the TDIV clocks.
17 */
18static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
19{
20 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
21}
22
23/**
24 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
25 * @tcfg1: The tcfg1 setting, shifted down.
26 *
27 * Get the divisor value for the given tcfg1 setting. We assume the
28 * caller has already checked to see if this is not a TCLK source.
29 */
30static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
31{
32 return 1 << tcfg1;
33}
34
35/**
36 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
37 *
38 * Return true if we have a /1 in the tdiv setting.
39 */
40static inline unsigned int pwm_tdiv_has_div1(void)
41{
42 return 1;
43}
44
45/**
46 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
47 * @div: The divisor to calculate the bit information for.
48 *
49 * Turn a divisor into the necessary bit field for TCFG1.
50 */
51static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
52{
53 return ilog2(div);
54}
55
56#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
index 69b78d9f83b8..b91e02093289 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
@@ -21,8 +21,11 @@
21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) 21#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) 22#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
23 23
24#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
25
24#define S3C64XX_OTHERS S3C_SYSREG(0x900) 26#define S3C64XX_OTHERS S3C_SYSREG(0x900)
25 27
26#define S3C64XX_OTHERS_USBMASK (1 << 16) 28#define S3C64XX_OTHERS_USBMASK (1 << 16)
29#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
27 30
28#endif /* _PLAT_REGS_SYS_H */ 31#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
deleted file mode 100644
index f86958d05352..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6400 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S3C6400 related SoCs */
16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_setup_clocks(void);
19
20extern void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
21
22#ifdef CONFIG_CPU_S3C6400
23
24extern int s3c6400_init(void);
25extern void s3c6400_init_irq(void);
26extern void s3c6400_map_io(void);
27extern void s3c6400_init_clocks(int xtal);
28
29#define s3c6400_init_uarts s3c6400_common_init_uarts
30
31#else
32#define s3c6400_init_clocks NULL
33#define s3c6400_init_uarts NULL
34#define s3c6400_map_io NULL
35#define s3c6400_init NULL
36#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h b/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
deleted file mode 100644
index 24f1141ffcb7..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6410 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifdef CONFIG_CPU_S3C6410
16
17extern int s3c6410_init(void);
18extern void s3c6410_init_irq(void);
19extern void s3c6410_map_io(void);
20extern void s3c6410_init_clocks(int xtal);
21
22#define s3c6410_init_uarts s3c6400_common_init_uarts
23
24#else
25#define s3c6410_init_clocks NULL
26#define s3c6410_init_uarts NULL
27#define s3c6410_map_io NULL
28#define s3c6410_init NULL
29#endif
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index d164a282bfb4..8eba88e7209e 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -45,7 +45,7 @@
45#include <plat/fb.h> 45#include <plat/fb.h>
46#include <plat/regs-fb-v4.h> 46#include <plat/regs-fb-v4.h>
47 47
48#include <mach/s3c6410.h> 48#include <plat/s3c6410.h>
49#include <plat/clock.h> 49#include <plat/clock.h>
50#include <plat/devs.h> 50#include <plat/devs.h>
51#include <plat/cpu.h> 51#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
new file mode 100644
index 000000000000..66668565ee75
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -0,0 +1,182 @@
1/* Speyside modules for Cragganmore - board data probing
2 *
3 * Copyright 2011 Wolfson Microelectronics plc
4 * Mark Brown <broonie@opensource.wolfsonmicro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/interrupt.h>
13#include <linux/i2c.h>
14
15#include <linux/mfd/wm831x/irq.h>
16#include <linux/mfd/wm831x/gpio.h>
17
18#include <sound/wm8996.h>
19#include <sound/wm8962.h>
20#include <sound/wm9081.h>
21
22#include <mach/crag6410.h>
23
24static struct wm8996_retune_mobile_config wm8996_retune[] = {
25 {
26 .name = "Sub LPF",
27 .rate = 48000,
28 .regs = {
29 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
30 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
31 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
32 },
33 },
34 {
35 .name = "Sub HPF",
36 .rate = 48000,
37 .regs = {
38 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
39 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
40 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
41 },
42 },
43};
44
45static struct wm8996_pdata wm8996_pdata __initdata = {
46 .ldo_ena = S3C64XX_GPN(7),
47 .gpio_base = CODEC_GPIO_BASE,
48 .micdet_def = 1,
49 .inl_mode = WM8996_DIFFERRENTIAL_1,
50 .inr_mode = WM8996_DIFFERRENTIAL_1,
51
52 .irq_flags = IRQF_TRIGGER_RISING,
53
54 .gpio_default = {
55 0x8001, /* GPIO1 == ADCLRCLK1 */
56 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
57 0x0141, /* GPIO3 == HP_SEL */
58 0x0002, /* GPIO4 == IRQ */
59 0x020e, /* GPIO5 == CLKOUT */
60 },
61
62 .retune_mobile_cfgs = wm8996_retune,
63 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
64};
65
66static struct wm8962_pdata wm8962_pdata __initdata = {
67 .gpio_init = {
68 0,
69 WM8962_GPIO_FN_OPCLK,
70 WM8962_GPIO_FN_DMICCLK,
71 0,
72 0x8000 | WM8962_GPIO_FN_DMICDAT,
73 WM8962_GPIO_FN_IRQ, /* Open drain mode */
74 },
75 .irq_active_low = true,
76};
77
78static struct wm9081_pdata wm9081_pdata __initdata = {
79 .irq_high = false,
80 .irq_cmos = false,
81};
82
83static const struct i2c_board_info wm1254_devs[] = {
84 { I2C_BOARD_INFO("wm8996", 0x1a),
85 .platform_data = &wm8996_pdata,
86 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
87 },
88 { I2C_BOARD_INFO("wm9081", 0x6c),
89 .platform_data = &wm9081_pdata, },
90};
91
92static const struct i2c_board_info wm1255_devs[] = {
93 { I2C_BOARD_INFO("wm5100", 0x1a),
94 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
95 },
96 { I2C_BOARD_INFO("wm9081", 0x6c),
97 .platform_data = &wm9081_pdata, },
98};
99
100static const struct i2c_board_info wm1259_devs[] = {
101 { I2C_BOARD_INFO("wm8962", 0x1a),
102 .platform_data = &wm8962_pdata,
103 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
104 },
105};
106
107
108static __devinitdata const struct {
109 u8 id;
110 const char *name;
111 const struct i2c_board_info *i2c_devs;
112 int num_i2c_devs;
113} gf_mods[] = {
114 { .id = 0x01, .name = "1250-EV1 Springbank" },
115 { .id = 0x02, .name = "1251-EV1 Jura" },
116 { .id = 0x03, .name = "1252-EV1 Glenlivet" },
117 { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
118 { .id = 0x21, .name = "1275-EV1 Mortlach" },
119 { .id = 0x25, .name = "1274-EV1 Glencadam" },
120 { .id = 0x31, .name = "1253-EV1 Tomatin", },
121 { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
122 .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
123 { .id = 0x3a, .name = "1259-EV1 Tobermory",
124 .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
125 { .id = 0x3b, .name = "1255-EV1 Kilchoman",
126 .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
127 { .id = 0x3c, .name = "1273-EV1 Longmorn" },
128};
129
130static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
131 const struct i2c_device_id *i2c_id)
132{
133 int ret, i, j, id, rev;
134
135 ret = i2c_smbus_read_byte_data(i2c, 0);
136 if (ret < 0) {
137 dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
138 return ret;
139 }
140
141 id = (ret & 0xfe) >> 2;
142 rev = ret & 0x3;
143 for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
144 if (id == gf_mods[i].id)
145 break;
146
147 if (i < ARRAY_SIZE(gf_mods)) {
148 dev_info(&i2c->dev, "%s revision %d\n",
149 gf_mods[i].name, rev + 1);
150 for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
151 if (!i2c_new_device(i2c->adapter,
152 &(gf_mods[i].i2c_devs[j])))
153 dev_err(&i2c->dev,
154 "Failed to register dev: %d\n", ret);
155 }
156 } else {
157 dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
158 id, rev);
159 }
160
161 return 0;
162}
163
164static const struct i2c_device_id wlf_gf_module_id[] = {
165 { "wlf-gf-module", 0 },
166 { }
167};
168
169static struct i2c_driver wlf_gf_module_driver = {
170 .driver = {
171 .name = "wlf-gf-module",
172 .owner = THIS_MODULE,
173 },
174 .probe = wlf_gf_module_probe,
175 .id_table = wlf_gf_module_id,
176};
177
178static int __init wlf_gf_module_register(void)
179{
180 return i2c_add_driver(&wlf_gf_module_driver);
181}
182module_init(wlf_gf_module_register);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 806580388f30..d04b65448510 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -43,13 +43,14 @@
43#include <mach/hardware.h> 43#include <mach/hardware.h>
44#include <mach/map.h> 44#include <mach/map.h>
45 45
46#include <mach/s3c6410.h>
47#include <mach/regs-sys.h> 46#include <mach/regs-sys.h>
48#include <mach/regs-gpio.h> 47#include <mach/regs-gpio.h>
49#include <mach/regs-modem.h> 48#include <mach/regs-modem.h>
49#include <mach/crag6410.h>
50 50
51#include <mach/regs-gpio-memport.h> 51#include <mach/regs-gpio-memport.h>
52 52
53#include <plat/s3c6410.h>
53#include <plat/regs-serial.h> 54#include <plat/regs-serial.h>
54#include <plat/regs-fb-v4.h> 55#include <plat/regs-fb-v4.h>
55#include <plat/fb.h> 56#include <plat/fb.h>
@@ -65,17 +66,6 @@
65#include <plat/iic.h> 66#include <plat/iic.h>
66#include <plat/pm.h> 67#include <plat/pm.h>
67 68
68#include <sound/wm8996.h>
69#include <sound/wm8962.h>
70#include <sound/wm9081.h>
71
72#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
73#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
74
75#define PCA935X_GPIO_BASE GPIO_BOARD_START
76#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
77#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
78
79/* serial port setup */ 69/* serial port setup */
80 70
81#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 71#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
@@ -287,6 +277,11 @@ static struct platform_device speyside_device = {
287 .id = -1, 277 .id = -1,
288}; 278};
289 279
280static struct platform_device lowland_device = {
281 .name = "lowland",
282 .id = -1,
283};
284
290static struct platform_device speyside_wm8962_device = { 285static struct platform_device speyside_wm8962_device = {
291 .name = "speyside-wm8962", 286 .name = "speyside-wm8962",
292 .id = -1, 287 .id = -1,
@@ -295,6 +290,8 @@ static struct platform_device speyside_wm8962_device = {
295static struct regulator_consumer_supply wallvdd_consumers[] = { 290static struct regulator_consumer_supply wallvdd_consumers[] = {
296 REGULATOR_SUPPLY("SPKVDD1", "1-001a"), 291 REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
297 REGULATOR_SUPPLY("SPKVDD2", "1-001a"), 292 REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
293 REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
294 REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
298}; 295};
299 296
300static struct regulator_init_data wallvdd_data = { 297static struct regulator_init_data wallvdd_data = {
@@ -342,6 +339,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
342 &crag6410_backlight_device, 339 &crag6410_backlight_device,
343 &speyside_device, 340 &speyside_device,
344 &speyside_wm8962_device, 341 &speyside_wm8962_device,
342 &lowland_device,
345 &wallvdd_device, 343 &wallvdd_device,
346}; 344};
347 345
@@ -350,6 +348,12 @@ static struct pca953x_platform_data crag6410_pca_data = {
350 .irq_base = 0, 348 .irq_base = 0,
351}; 349};
352 350
351/* VDDARM is controlled by DVS1 connected to GPK(0) */
352static struct wm831x_buckv_pdata vddarm_pdata = {
353 .dvs_control_src = 1,
354 .dvs_gpio = S3C64XX_GPK(0),
355};
356
353static struct regulator_consumer_supply vddarm_consumers[] __initdata = { 357static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
354 REGULATOR_SUPPLY("vddarm", NULL), 358 REGULATOR_SUPPLY("vddarm", NULL),
355}; 359};
@@ -365,6 +369,7 @@ static struct regulator_init_data vddarm __initdata = {
365 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers), 369 .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
366 .consumer_supplies = vddarm_consumers, 370 .consumer_supplies = vddarm_consumers,
367 .supply_regulator = "WALLVDD", 371 .supply_regulator = "WALLVDD",
372 .driver_data = &vddarm_pdata,
368}; 373};
369 374
370static struct regulator_init_data vddint __initdata = { 375static struct regulator_init_data vddint __initdata = {
@@ -500,6 +505,8 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = {
500 .backup = &banff_backup_pdata, 505 .backup = &banff_backup_pdata,
501 506
502 .gpio_defaults = { 507 .gpio_defaults = {
508 /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
509 [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
503 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/ 510 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
504 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6, 511 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
505 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/ 512 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
@@ -557,8 +564,12 @@ static struct regulator_init_data pvdd_1v2 __initdata = {
557}; 564};
558 565
559static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = { 566static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
567 REGULATOR_SUPPLY("LDOVDD", "1-001a"),
560 REGULATOR_SUPPLY("PLLVDD", "1-001a"), 568 REGULATOR_SUPPLY("PLLVDD", "1-001a"),
561 REGULATOR_SUPPLY("DBVDD", "1-001a"), 569 REGULATOR_SUPPLY("DBVDD", "1-001a"),
570 REGULATOR_SUPPLY("DBVDD1", "1-001a"),
571 REGULATOR_SUPPLY("DBVDD2", "1-001a"),
572 REGULATOR_SUPPLY("DBVDD3", "1-001a"),
562 REGULATOR_SUPPLY("CPVDD", "1-001a"), 573 REGULATOR_SUPPLY("CPVDD", "1-001a"),
563 REGULATOR_SUPPLY("AVDD2", "1-001a"), 574 REGULATOR_SUPPLY("AVDD2", "1-001a"),
564 REGULATOR_SUPPLY("DCVDD", "1-001a"), 575 REGULATOR_SUPPLY("DCVDD", "1-001a"),
@@ -611,81 +622,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
611 .disable_touch = true, 622 .disable_touch = true,
612}; 623};
613 624
614static struct wm8996_retune_mobile_config wm8996_retune[] = {
615 {
616 .name = "Sub LPF",
617 .rate = 48000,
618 .regs = {
619 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
620 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
621 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
622 },
623 },
624 {
625 .name = "Sub HPF",
626 .rate = 48000,
627 .regs = {
628 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
629 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
630 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
631 },
632 },
633};
634
635static struct wm8996_pdata wm8996_pdata __initdata = {
636 .ldo_ena = S3C64XX_GPN(7),
637 .gpio_base = CODEC_GPIO_BASE,
638 .micdet_def = 1,
639 .inl_mode = WM8996_DIFFERRENTIAL_1,
640 .inr_mode = WM8996_DIFFERRENTIAL_1,
641
642 .irq_flags = IRQF_TRIGGER_RISING,
643
644 .gpio_default = {
645 0x8001, /* GPIO1 == ADCLRCLK1 */
646 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
647 0x0141, /* GPIO3 == HP_SEL */
648 0x0002, /* GPIO4 == IRQ */
649 0x020e, /* GPIO5 == CLKOUT */
650 },
651
652 .retune_mobile_cfgs = wm8996_retune,
653 .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
654};
655
656static struct wm8962_pdata wm8962_pdata __initdata = {
657 .gpio_init = {
658 0,
659 WM8962_GPIO_FN_OPCLK,
660 WM8962_GPIO_FN_DMICCLK,
661 0,
662 0x8000 | WM8962_GPIO_FN_DMICDAT,
663 WM8962_GPIO_FN_IRQ, /* Open drain mode */
664 },
665 .irq_active_low = true,
666};
667
668static struct wm9081_pdata wm9081_pdata __initdata = {
669 .irq_high = false,
670 .irq_cmos = false,
671};
672
673static struct i2c_board_info i2c_devs1[] __initdata = { 625static struct i2c_board_info i2c_devs1[] __initdata = {
674 { I2C_BOARD_INFO("wm8311", 0x34), 626 { I2C_BOARD_INFO("wm8311", 0x34),
675 .irq = S3C_EINT(0), 627 .irq = S3C_EINT(0),
676 .platform_data = &glenfarclas_pmic_pdata }, 628 .platform_data = &glenfarclas_pmic_pdata },
677 629
630 { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
631 { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
632 { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
633
678 { I2C_BOARD_INFO("wm1250-ev1", 0x27) }, 634 { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
679 { I2C_BOARD_INFO("wm8996", 0x1a),
680 .platform_data = &wm8996_pdata,
681 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
682 },
683 { I2C_BOARD_INFO("wm9081", 0x6c),
684 .platform_data = &wm9081_pdata, },
685 { I2C_BOARD_INFO("wm8962", 0x1a),
686 .platform_data = &wm8962_pdata,
687 .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
688 },
689}; 635};
690 636
691static void __init crag6410_map_io(void) 637static void __init crag6410_map_io(void)
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 19a0887e1c1e..952f75ff5deb 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -37,7 +37,7 @@
37#include <plat/fb.h> 37#include <plat/fb.h>
38#include <plat/nand.h> 38#include <plat/nand.h>
39 39
40#include <mach/s3c6410.h> 40#include <plat/s3c6410.h>
41#include <plat/clock.h> 41#include <plat/clock.h>
42#include <plat/devs.h> 42#include <plat/devs.h>
43#include <plat/cpu.h> 43#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index fb8969aa412e..1bc85c359498 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -32,8 +32,8 @@
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-modem.h> 33#include <mach/regs-modem.h>
34#include <mach/regs-srom.h> 34#include <mach/regs-srom.h>
35#include <mach/s3c6410.h>
36 35
36#include <plat/s3c6410.h>
37#include <plat/adc.h> 37#include <plat/adc.h>
38#include <plat/cpu.h> 38#include <plat/cpu.h>
39#include <plat/devs.h> 39#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index c30f2e5e0d85..cb13cba98b3d 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -39,7 +39,7 @@
39#include <plat/iic.h> 39#include <plat/iic.h>
40#include <plat/fb.h> 40#include <plat/fb.h>
41 41
42#include <mach/s3c6410.h> 42#include <plat/s3c6410.h>
43#include <plat/clock.h> 43#include <plat/clock.h>
44#include <plat/devs.h> 44#include <plat/devs.h>
45#include <plat/cpu.h> 45#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 93170d4834e7..87281e4b8471 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -33,8 +33,8 @@
33#include <mach/regs-gpio.h> 33#include <mach/regs-gpio.h>
34#include <mach/regs-modem.h> 34#include <mach/regs-modem.h>
35#include <mach/regs-srom.h> 35#include <mach/regs-srom.h>
36#include <mach/s3c6410.h>
37 36
37#include <plat/s3c6410.h>
38#include <plat/adc.h> 38#include <plat/adc.h>
39#include <plat/cpu.h> 39#include <plat/cpu.h>
40#include <plat/devs.h> 40#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index cbb57ded3d95..94c831d88365 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -22,8 +22,8 @@
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <mach/regs-gpio.h> 24#include <mach/regs-gpio.h>
25#include <mach/s3c6410.h>
26 25
26#include <plat/s3c6410.h>
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28#include <plat/devs.h> 28#include <plat/devs.h>
29#include <plat/fb.h> 29#include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 04f914b85fdf..f112547ce80a 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -22,8 +22,8 @@
22 22
23#include <mach/map.h> 23#include <mach/map.h>
24#include <mach/regs-gpio.h> 24#include <mach/regs-gpio.h>
25#include <mach/s3c6410.h>
26 25
26#include <plat/s3c6410.h>
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28#include <plat/devs.h> 28#include <plat/devs.h>
29#include <plat/fb.h> 29#include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 6fd5e95f8f75..73450c2b530a 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -31,7 +31,7 @@
31 31
32#include <plat/regs-serial.h> 32#include <plat/regs-serial.h>
33 33
34#include <mach/s3c6400.h> 34#include <plat/s3c6400.h>
35#include <plat/clock.h> 35#include <plat/clock.h>
36#include <plat/devs.h> 36#include <plat/devs.h>
37#include <plat/cpu.h> 37#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 5f147c33edad..8bc8edd85e5a 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -63,7 +63,7 @@
63#include <plat/fb.h> 63#include <plat/fb.h>
64#include <plat/gpio-cfg.h> 64#include <plat/gpio-cfg.h>
65 65
66#include <mach/s3c6410.h> 66#include <plat/s3c6410.h>
67#include <plat/clock.h> 67#include <plat/clock.h>
68#include <plat/devs.h> 68#include <plat/devs.h>
69#include <plat/cpu.h> 69#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 055e2858b0dd..b375cd5c47cb 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -29,6 +29,7 @@
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30#include <mach/regs-syscon-power.h> 30#include <mach/regs-syscon-power.h>
31#include <mach/regs-gpio-memport.h> 31#include <mach/regs-gpio-memport.h>
32#include <mach/regs-modem.h>
32 33
33#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 34#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
34void s3c_pm_debug_smdkled(u32 set, u32 clear) 35void s3c_pm_debug_smdkled(u32 set, u32 clear)
@@ -85,6 +86,9 @@ static struct sleep_save misc_save[] = {
85 SAVE_ITEM(S3C64XX_MEM0CONSLP0), 86 SAVE_ITEM(S3C64XX_MEM0CONSLP0),
86 SAVE_ITEM(S3C64XX_MEM0CONSLP1), 87 SAVE_ITEM(S3C64XX_MEM0CONSLP1),
87 SAVE_ITEM(S3C64XX_MEM1CONSLP), 88 SAVE_ITEM(S3C64XX_MEM1CONSLP),
89
90 SAVE_ITEM(S3C64XX_SDMA_SEL),
91 SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
88}; 92};
89 93
90void s3c_pm_configure_extint(void) 94void s3c_pm_configure_extint(void)
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 5e93fe3f3f40..7a3bc32df425 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -38,7 +38,7 @@
38#include <plat/sdhci.h> 38#include <plat/sdhci.h>
39#include <plat/iic-core.h> 39#include <plat/iic-core.h>
40#include <plat/onenand-core.h> 40#include <plat/onenand-core.h>
41#include <mach/s3c6400.h> 41#include <plat/s3c6400.h>
42 42
43void __init s3c6400_map_io(void) 43void __init s3c6400_map_io(void)
44{ 44{
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 312aa6b115e8..4117003464ad 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -41,8 +41,8 @@
41#include <plat/adc-core.h> 41#include <plat/adc-core.h>
42#include <plat/iic-core.h> 42#include <plat/iic-core.h>
43#include <plat/onenand-core.h> 43#include <plat/onenand-core.h>
44#include <mach/s3c6400.h> 44#include <plat/s3c6400.h>
45#include <mach/s3c6410.h> 45#include <plat/s3c6410.h>
46 46
47void __init s3c6410_map_io(void) 47void __init s3c6410_map_io(void)
48{ 48{
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
index f344a222bc84..c75a71b21165 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci.c
@@ -12,17 +12,7 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#include <linux/kernel.h>
16#include <linux/types.h> 15#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26 16
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ 17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28 18
@@ -32,41 +22,3 @@ char *s3c64xx_hsmmc_clksrcs[4] = {
32 [2] = "mmc_bus", 22 [2] = "mmc_bus",
33 /* [3] = "48m", - note not successfully used yet */ 23 /* [3] = "48m", - note not successfully used yet */
34}; 24};
35
36void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
46 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
47 S3C_SDHCI_CTRL2_ENFBCLKRX |
48 S3C_SDHCI_CTRL2_DFCNT_NONE |
49 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
50
51 if (ios->clock < 25 * 1000000)
52 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
53 S3C_SDHCI_CTRL3_FCSEL2 |
54 S3C_SDHCI_CTRL3_FCSEL1 |
55 S3C_SDHCI_CTRL3_FCSEL0);
56 else
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
58
59 pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
60 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
61 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
62}
63
64void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
65 void __iomem *r,
66 struct mmc_ios *ios,
67 struct mmc_card *card)
68{
69 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
70
71 s3c6400_setup_sdhci_cfg_card(dev, r, ios, card);
72}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 20:48:40 -0500