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authorBen Dooks <ben-linux@fluff.org>2010-01-25 20:11:04 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-25 20:16:32 -0500
commit431107ea5b680a24a4d01fbd3a178a3eb932f378 (patch)
tree6515a616e8ed60480e169188e630936794be2c77 /arch/arm/mach-s3c64xx
parentab5d97db1c6ced3e95c00d097931471707032b1f (diff)
ARM: S3C64XX: Merge mach-s3c6400 and mach-s3c6410
As per discussions with Russell King on linux-arm-kernel, it appears that both mach-s3c6400 and mach-s3c6410 are so close together that they should simply be merged into mach-s3c64xx. Note, this patch does not eliminate any of the bits that are still common, it is simply a move of the two directories together, any further common code will be eliminated or moved in further patches. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig135
-rw-r--r--arch/arm/mach-s3c64xx/Makefile29
-rw-r--r--arch/arm/mach-s3c64xx/Makefile.boot2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/debug-macro.S39
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/dma.h70
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/entry-macro.S18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/gpio.h96
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/hardware.h16
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/irqs.h16
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h107
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/memory.h18
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/pwm-clock.h56
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-clock.h16
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-fb.h41
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-irq.h20
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/system.h30
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/tick.h29
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/uncompress.h28
-rw-r--r--arch/arm/mach-s3c64xx/mach-anw6410.c245
-rw-r--r--arch/arm/mach-s3c64xx/mach-hmt.c276
-rw-r--r--arch/arm/mach-s3c64xx/mach-ncp.c107
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6400.c96
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c491
-rw-r--r--arch/arm/mach-s3c64xx/s3c6400.c92
-rw-r--r--arch/arm/mach-s3c64xx/s3c6410.c105
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c63
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c68
27 files changed, 2309 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
new file mode 100644
index 000000000000..551bb3faa3ac
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -0,0 +1,135 @@
1# Copyright 2008 Openmoko, Inc.
2# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
3#
4# Licensed under GPLv2
5
6# Configuration options for the S3C6410 CPU
7
8config CPU_S3C6400
9 bool
10 select CPU_S3C6400_INIT
11 select CPU_S3C6400_CLOCK
12 help
13 Enable S3C6400 CPU support
14
15config CPU_S3C6410
16 bool
17 select CPU_S3C6400_INIT
18 select CPU_S3C6400_CLOCK
19 help
20 Enable S3C6410 CPU support
21
22config S3C6400_SETUP_SDHCI
23 bool
24 help
25 Internal configuration for default SDHCI
26 setup for S3C6400.
27
28config S3C6410_SETUP_SDHCI
29 bool
30 select S3C64XX_SETUP_SDHCI_GPIO
31 help
32 Internal helper functions for S3C6410 based SDHCI systems
33
34# S36400 Macchine support
35
36config MACH_SMDK6400
37 bool "SMDK6400"
38 select CPU_S3C6400
39 select S3C_DEV_HSMMC
40 select S3C_DEV_NAND
41 select S3C6400_SETUP_SDHCI
42 help
43 Machine support for the Samsung SMDK6400
44
45# S3C6410 machine support
46
47config MACH_ANW6410
48 bool "A&W6410"
49 select CPU_S3C6410
50 select S3C_DEV_FB
51 select S3C64XX_SETUP_FB_24BPP
52 help
53 Machine support for the A&W6410
54
55config MACH_SMDK6410
56 bool "SMDK6410"
57 select CPU_S3C6410
58 select S3C_DEV_HSMMC
59 select S3C_DEV_HSMMC1
60 select S3C_DEV_I2C1
61 select S3C_DEV_FB
62 select S3C_DEV_USB_HOST
63 select S3C_DEV_USB_HSOTG
64 select S3C6410_SETUP_SDHCI
65 select S3C64XX_SETUP_I2C1
66 select S3C64XX_SETUP_FB_24BPP
67 help
68 Machine support for the Samsung SMDK6410
69
70# At least some of the SMDK6410s were shipped with the card detect
71# for the MMC/SD slots connected to the same input. This means that
72# either the boards need to be altered to have channel0 to an alternate
73# configuration or that only one slot can be used.
74
75choice
76 prompt "SMDK6410 MMC/SD slot setup"
77 depends on MACH_SMDK6410
78
79config SMDK6410_SD_CH0
80 bool "Use channel 0 only"
81 depends on MACH_SMDK6410
82 help
83 Select CON7 (channel 0) as the MMC/SD slot, as
84 at least some SMDK6410 boards come with the
85 resistors fitted so that the card detects for
86 channels 0 and 1 are the same.
87
88config SMDK6410_SD_CH1
89 bool "Use channel 1 only"
90 depends on MACH_SMDK6410
91 help
92 Select CON6 (channel 1) as the MMC/SD slot, as
93 at least some SMDK6410 boards come with the
94 resistors fitted so that the card detects for
95 channels 0 and 1 are the same.
96
97endchoice
98
99config SMDK6410_WM1190_EV1
100 bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
101 depends on MACH_SMDK6410
102 select REGULATOR
103 select REGULATOR_WM8350
104 select S3C24XX_GPIO_EXTRA64
105 select MFD_WM8350_I2C
106 select MFD_WM8350_CONFIG_MODE_0
107 select MFD_WM8350_CONFIG_MODE_3
108 select MFD_WM8352_CONFIG_MODE_0
109 help
110 The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC
111 and audio daughtercard for the Samsung SMDK6410 reference
112 platform. Enabling this option will build support for this
113 module into the kernel. The presence of the module will be
114 detected at runtime so the the resulting kernel can be used
115 with or without the 1190-EV1 fitted.
116
117config MACH_NCP
118 bool "NCP"
119 select CPU_S3C6410
120 select S3C_DEV_I2C1
121 select S3C_DEV_HSMMC1
122 select S3C64XX_SETUP_I2C1
123 help
124 Machine support for the Samsung NCP
125
126config MACH_HMT
127 bool "Airgoo HMT"
128 select CPU_S3C6410
129 select S3C_DEV_FB
130 select S3C_DEV_NAND
131 select S3C_DEV_USB_HOST
132 select S3C64XX_SETUP_FB_24BPP
133 select HAVE_PWM
134 help
135 Machine support for the Airgoo HMT
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
new file mode 100644
index 000000000000..24a3bc33da1e
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -0,0 +1,29 @@
1# arch/arm/mach-s3c64xx/Makefile
2#
3# Copyright 2008 Openmoko, Inc.
4# Copyright 2008 Simtec Electronics
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S3C6400 system
14
15obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
16obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
17
18# setup support
19
20obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci-s3c6400.o
21obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci-s3c6410.o
22
23# Machine support
24
25obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
26obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
27obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
28obj-$(CONFIG_MACH_NCP) += mach-ncp.o
29obj-$(CONFIG_MACH_HMT) += mach-hmt.o
diff --git a/arch/arm/mach-s3c64xx/Makefile.boot b/arch/arm/mach-s3c64xx/Makefile.boot
new file mode 100644
index 000000000000..ba41fdc0a586
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/Makefile.boot
@@ -0,0 +1,2 @@
1 zreladdr-y := 0x50008000
2params_phys-y := 0x50000100
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b18ac5266dfc
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
1/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16#include <plat/regs-serial.h>
17
18 /* note, for the boot process to work we have to keep the UART
19 * virtual address aligned to an 1MiB boundary for the L1
20 * mapping the head code makes. We keep the UART virtual address
21 * aligned and add in the offset when we load the value here.
22 */
23
24 .macro addruart, rx
25 mrc p15, 0, \rx, c1, c0
26 tst \rx, #1
27 ldreq \rx, = S3C_PA_UART
28 ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
29#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
31#endif
32 .endm
33
34/* include the reset of the code which will do the work, we're only
35 * compiling for a single cpu processor type so the default of s3c2440
36 * will be fine with us.
37 */
38
39#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
new file mode 100644
index 000000000000..6723860748be
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - DMA support
9 */
10
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H __FILE__
13
14#define S3C_DMA_CHANNELS (16)
15
16/* see mach-s3c2410/dma.h for notes on dma channel numbers */
17
18/* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
21 */
22enum dma_ch {
23 /* DMA0/SDMA0 */
24 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2,
26 DMACH_UART1,
27 DMACH_UART1_SRC2,
28 DMACH_UART2,
29 DMACH_UART2_SRC2,
30 DMACH_UART3,
31 DMACH_UART3_SRC2,
32 DMACH_PCM0_TX,
33 DMACH_PCM0_RX,
34 DMACH_I2S0_OUT,
35 DMACH_I2S0_IN,
36 DMACH_SPI0_TX,
37 DMACH_SPI0_RX,
38 DMACH_HSI_I2SV40_TX,
39 DMACH_HSI_I2SV40_RX,
40
41 /* DMA1/SDMA1 */
42 DMACH_PCM1_TX = 16,
43 DMACH_PCM1_RX,
44 DMACH_I2S1_OUT,
45 DMACH_I2S1_IN,
46 DMACH_SPI1_TX,
47 DMACH_SPI1_RX,
48 DMACH_AC97_PCMOUT,
49 DMACH_AC97_PCMIN,
50 DMACH_AC97_MICIN,
51 DMACH_PWM,
52 DMACH_IRDA,
53 DMACH_EXTERNAL,
54 DMACH_RES1,
55 DMACH_RES2,
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
59};
60
61static __inline__ bool s3c_dma_has_circular(void)
62{
63 return true;
64}
65
66#define S3C2410_DMAF_CIRCULAR (1 << 0)
67
68#include <plat/dma.h>
69
70#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..33a8fe240882
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * Low-level IRQ helper macros for the Samsung S3C64XX series
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13*/
14
15#include <mach/map.h>
16#include <plat/irqs.h>
17
18#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
new file mode 100644
index 000000000000..e8e35e8fe731
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -0,0 +1,96 @@
1/* arch/arm/mach-s3c6400/include/mach/gpio.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C6400 - GPIO lib support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define gpio_get_value __gpio_get_value
16#define gpio_set_value __gpio_set_value
17#define gpio_cansleep __gpio_cansleep
18#define gpio_to_irq __gpio_to_irq
19
20/* GPIO bank sizes */
21#define S3C64XX_GPIO_A_NR (8)
22#define S3C64XX_GPIO_B_NR (7)
23#define S3C64XX_GPIO_C_NR (8)
24#define S3C64XX_GPIO_D_NR (5)
25#define S3C64XX_GPIO_E_NR (5)
26#define S3C64XX_GPIO_F_NR (16)
27#define S3C64XX_GPIO_G_NR (7)
28#define S3C64XX_GPIO_H_NR (10)
29#define S3C64XX_GPIO_I_NR (16)
30#define S3C64XX_GPIO_J_NR (12)
31#define S3C64XX_GPIO_K_NR (16)
32#define S3C64XX_GPIO_L_NR (15)
33#define S3C64XX_GPIO_M_NR (6)
34#define S3C64XX_GPIO_N_NR (16)
35#define S3C64XX_GPIO_O_NR (16)
36#define S3C64XX_GPIO_P_NR (15)
37#define S3C64XX_GPIO_Q_NR (9)
38
39/* GPIO bank numbes */
40
41/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
42 * space for debugging purposes so that any accidental
43 * change from one gpio bank to another can be caught.
44*/
45
46#define S3C64XX_GPIO_NEXT(__gpio) \
47 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
48
49enum s3c_gpio_number {
50 S3C64XX_GPIO_A_START = 0,
51 S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
52 S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
53 S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
54 S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
55 S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
56 S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
57 S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
58 S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
59 S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
60 S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
61 S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
62 S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
63 S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
64 S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
65 S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
66 S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
67};
68
69/* S3C64XX GPIO number definitions. */
70
71#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
72#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
73#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
74#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
75#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
76#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
77#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
78#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
79#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
80#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
81#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
82#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
83#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
84#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
85#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
86#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
87#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
88
89/* the end of the S3C64XX specific gpios */
90#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
91#define S3C_GPIO_END S3C64XX_GPIO_END
92
93/* define the number of gpios we need to the one after the GPQ() range */
94#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
95
96#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s3c64xx/include/mach/hardware.h b/arch/arm/mach-s3c64xx/include/mach/hardware.h
new file mode 100644
index 000000000000..862d033e57a4
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/hardware.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - Hardware support
9 */
10
11#ifndef __ASM_ARCH_HARDWARE_H
12#define __ASM_ARCH_HARDWARE_H __FILE__
13
14/* currently nothing here, placeholder */
15
16#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
new file mode 100644
index 000000000000..4c97f9a4370b
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - IRQ definitions
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H __FILE__
13
14#include <plat/irqs.h>
15
16#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
new file mode 100644
index 000000000000..801c1c0f3a95
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -0,0 +1,107 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/map.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - Memory map definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_MAP_H
16#define __ASM_ARCH_MAP_H __FILE__
17
18#include <plat/map-base.h>
19
20/*
21 * Post-mux Chip Select Regions Xm0CSn_
22 * These may be used by SROM, NAND or CF depending on settings
23 */
24
25#define S3C64XX_PA_XM0CSN0 (0x10000000)
26#define S3C64XX_PA_XM0CSN1 (0x18000000)
27#define S3C64XX_PA_XM0CSN2 (0x20000000)
28#define S3C64XX_PA_XM0CSN3 (0x28000000)
29#define S3C64XX_PA_XM0CSN4 (0x30000000)
30#define S3C64XX_PA_XM0CSN5 (0x38000000)
31
32/* HSMMC units */
33#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
34#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
36#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
37
38#define S3C_PA_UART (0x7F005000)
39#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
40#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
41#define S3C_PA_UART2 (S3C_PA_UART + 0x800)
42#define S3C_PA_UART3 (S3C_PA_UART + 0xC00)
43#define S3C_UART_OFFSET (0x400)
44
45/* See notes on UART VA mapping in debug-macro.S */
46#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
47
48#define S3C_VA_UART0 S3C_VA_UARTx(0)
49#define S3C_VA_UART1 S3C_VA_UARTx(1)
50#define S3C_VA_UART2 S3C_VA_UARTx(2)
51#define S3C_VA_UART3 S3C_VA_UARTx(3)
52
53#define S3C64XX_PA_SROM (0x70000000)
54
55#define S3C64XX_PA_NAND (0x70200000)
56#define S3C64XX_PA_FB (0x77100000)
57#define S3C64XX_PA_USB_HSOTG (0x7C000000)
58#define S3C64XX_PA_WATCHDOG (0x7E004000)
59#define S3C64XX_PA_RTC (0x7E005000)
60#define S3C64XX_PA_ADC (0x7E00B000)
61#define S3C64XX_PA_SYSCON (0x7E00F000)
62#define S3C64XX_PA_AC97 (0x7F001000)
63#define S3C64XX_PA_IIS0 (0x7F002000)
64#define S3C64XX_PA_IIS1 (0x7F003000)
65#define S3C64XX_PA_TIMER (0x7F006000)
66#define S3C64XX_PA_IIC0 (0x7F004000)
67#define S3C64XX_PA_SPI0 (0x7F00B000)
68#define S3C64XX_PA_SPI1 (0x7F00C000)
69#define S3C64XX_PA_PCM0 (0x7F009000)
70#define S3C64XX_PA_PCM1 (0x7F00A000)
71#define S3C64XX_PA_IISV4 (0x7F00D000)
72#define S3C64XX_PA_IIC1 (0x7F00F000)
73
74#define S3C64XX_PA_GPIO (0x7F008000)
75#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
76#define S3C64XX_SZ_GPIO SZ_4K
77
78#define S3C64XX_PA_SDRAM (0x50000000)
79#define S3C64XX_PA_VIC0 (0x71200000)
80#define S3C64XX_PA_VIC1 (0x71300000)
81
82#define S3C64XX_PA_MODEM (0x74108000)
83#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
84
85#define S3C64XX_PA_USBHOST (0x74300000)
86
87#define S3C64XX_PA_USB_HSPHY (0x7C100000)
88#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
89
90/* place VICs close together */
91#define VA_VIC0 (S3C_VA_IRQ + 0x00)
92#define VA_VIC1 (S3C_VA_IRQ + 0x10000)
93
94/* compatibiltiy defines. */
95#define S3C_PA_TIMER S3C64XX_PA_TIMER
96#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
97#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
98#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
99#define S3C_PA_IIC S3C64XX_PA_IIC0
100#define S3C_PA_IIC1 S3C64XX_PA_IIC1
101#define S3C_PA_NAND S3C64XX_PA_NAND
102#define S3C_PA_FB S3C64XX_PA_FB
103#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
104#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
105#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
106
107#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
new file mode 100644
index 000000000000..a3ac84a65480
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/memory.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-s3c6400/include/mach/memory.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PHYS_OFFSET UL(0x50000000)
17
18#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..b25bedee0d52
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64xx - pwm clock and timer support
9 */
10
11/**
12 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
13 * @tcfg: The timer TCFG1 register bits shifted down to 0.
14 *
15 * Return true if the given configuration from TCFG1 is a TCLK instead
16 * any of the TDIV clocks.
17 */
18static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
19{
20 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
21}
22
23/**
24 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
25 * @tcfg1: The tcfg1 setting, shifted down.
26 *
27 * Get the divisor value for the given tcfg1 setting. We assume the
28 * caller has already checked to see if this is not a TCLK source.
29 */
30static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
31{
32 return 1 << tcfg1;
33}
34
35/**
36 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
37 *
38 * Return true if we have a /1 in the tdiv setting.
39 */
40static inline unsigned int pwm_tdiv_has_div1(void)
41{
42 return 1;
43}
44
45/**
46 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
47 * @div: The divisor to calculate the bit information for.
48 *
49 * Turn a divisor into the necessary bit field for TCFG1.
50 */
51static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
52{
53 return ilog2(div);
54}
55
56#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
new file mode 100644
index 000000000000..a6c7f4eb3a1b
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - clock register compatibility with s3c24xx
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/regs-clock.h>
16
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
new file mode 100644
index 000000000000..f56611526c63
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2009 Samsung Electronics Co.
5 *
6 * Pawel Osciak <p.osciak@samsung.com>
7 * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
8 *
9 * Framebuffer register definitions for Samsung S3C64xx.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARCH_MACH_REGS_FB_H
17#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
18
19#include <plat/regs-fb-v4.h>
20
21/* Palette registers */
22#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
23#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
24#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
25#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
26#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
27
28static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
29{
30 switch (window) {
31 case 0: return WIN0_PAL(reg);
32 case 1: return WIN1_PAL(reg);
33 case 2: return WIN2_PAL(reg);
34 case 3: return WIN3_PAL(reg);
35 case 4: return WIN4_PAL(reg);
36 }
37
38 BUG();
39}
40
41#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
new file mode 100644
index 000000000000..bcce68a0bb75
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-irq.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - IRQ register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_REGS_IRQ_H
16#define __ASM_ARCH_REGS_IRQ_H __FILE__
17
18#include <asm/hardware/vic.h>
19
20#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
new file mode 100644
index 000000000000..2e58cb7a7147
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
@@ -0,0 +1,30 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/system.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - system implementation
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__
13
14#include <plat/watchdog-reset.h>
15
16static void arch_idle(void)
17{
18 /* nothing here yet */
19}
20
21static void arch_reset(char mode, const char *cmd)
22{
23 if (mode != 's')
24 arch_wdt_reset();
25
26 /* if all else fails, or mode was for soft, jump to 0 */
27 cpu_reset(0);
28}
29
30#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/tick.h b/arch/arm/mach-s3c64xx/include/mach/tick.h
new file mode 100644
index 000000000000..ebe18a9469b8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/tick.h
@@ -0,0 +1,29 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - Timer tick support definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_TICK_H
16#define __ASM_ARCH_TICK_H __FILE__
17
18/* note, the timer interrutps turn up in 2 places, the vic and then
19 * the timer block. We take the VIC as the base at the moment.
20 */
21static inline u32 s3c24xx_ostimer_pending(void)
22{
23 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
24 return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
25}
26
27#define TICK_MAX (0xffffffff)
28
29#endif /* __ASM_ARCH_6400_TICK_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c6a82a20bf2a
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -0,0 +1,28 @@
1/* arch/arm/mach-s3c6400/include/mach/uncompress.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C6400 - uncompress code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_UNCOMPRESS_H
16#define __ASM_ARCH_UNCOMPRESS_H
17
18#include <mach/map.h>
19#include <plat/uncompress.h>
20
21static void arch_detect_cpu(void)
22{
23 /* we do not need to do any cpu detection here at the moment. */
24 fifo_mask = S3C2440_UFSTAT_TXMASK;
25 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
26}
27
28#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
new file mode 100644
index 000000000000..49032a85f6f8
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -0,0 +1,245 @@
1/* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 * Copyright 2009 Kwangwoo Lee
8 * Kwangwoo Lee <kwangwoo.lee@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/i2c.h>
26#include <linux/fb.h>
27#include <linux/gpio.h>
28#include <linux/delay.h>
29#include <linux/dm9000.h>
30
31#include <video/platform_lcd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38#include <mach/regs-fb.h>
39#include <mach/map.h>
40
41#include <asm/irq.h>
42#include <asm/mach-types.h>
43
44#include <plat/regs-serial.h>
45#include <plat/iic.h>
46#include <plat/fb.h>
47
48#include <plat/s3c6410.h>
49#include <plat/clock.h>
50#include <plat/devs.h>
51#include <plat/cpu.h>
52#include <plat/regs-gpio.h>
53#include <plat/regs-modem.h>
54
55/* DM9000 */
56#define ANW6410_PA_DM9000 (0x18000000)
57
58/* A hardware buffer to control external devices is mapped at 0x30000000.
59 * It can not be read. So current status must be kept in anw6410_extdev_status.
60 */
61#define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
62#define ANW6410_PA_EXTDEV (0x30000000)
63
64#define ANW6410_EN_DM9000 (1<<11)
65#define ANW6410_EN_LCD (1<<14)
66
67static __u32 anw6410_extdev_status;
68
69static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
70 [0] = {
71 .hwport = 0,
72 .flags = 0,
73 .ucon = 0x3c5,
74 .ulcon = 0x03,
75 .ufcon = 0x51,
76 },
77 [1] = {
78 .hwport = 1,
79 .flags = 0,
80 .ucon = 0x3c5,
81 .ulcon = 0x03,
82 .ufcon = 0x51,
83 },
84};
85
86/* framebuffer and LCD setup. */
87static void __init anw6410_lcd_mode_set(void)
88{
89 u32 tmp;
90
91 /* set the LCD type */
92 tmp = __raw_readl(S3C64XX_SPCON);
93 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
94 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
95 __raw_writel(tmp, S3C64XX_SPCON);
96
97 /* remove the LCD bypass */
98 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
99 tmp &= ~MIFPCON_LCD_BYPASS;
100 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
101}
102
103/* GPF1 = LCD panel power
104 * GPF4 = LCD backlight control
105 */
106static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
107 unsigned int power)
108{
109 if (power) {
110 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
111 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
112
113 gpio_direction_output(S3C64XX_GPF(1), 1);
114 gpio_direction_output(S3C64XX_GPF(4), 1);
115 } else {
116 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
117 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
118
119 gpio_direction_output(S3C64XX_GPF(1), 0);
120 gpio_direction_output(S3C64XX_GPF(4), 0);
121 }
122}
123
124static struct plat_lcd_data anw6410_lcd_power_data = {
125 .set_power = anw6410_lcd_power_set,
126};
127
128static struct platform_device anw6410_lcd_powerdev = {
129 .name = "platform-lcd",
130 .dev.parent = &s3c_device_fb.dev,
131 .dev.platform_data = &anw6410_lcd_power_data,
132};
133
134static struct s3c_fb_pd_win anw6410_fb_win0 = {
135 /* this is to ensure we use win0 */
136 .win_mode = {
137 .pixclock = 41094,
138 .left_margin = 8,
139 .right_margin = 13,
140 .upper_margin = 7,
141 .lower_margin = 5,
142 .hsync_len = 3,
143 .vsync_len = 1,
144 .xres = 800,
145 .yres = 480,
146 },
147 .max_bpp = 32,
148 .default_bpp = 16,
149};
150
151/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
152static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
153 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
154 .win[0] = &anw6410_fb_win0,
155 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
156 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
157};
158
159/* DM9000AEP 10/100 ethernet controller */
160static void __init anw6410_dm9000_enable(void)
161{
162 anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
163 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
164}
165
166static struct resource anw6410_dm9000_resource[] = {
167 [0] = {
168 .start = ANW6410_PA_DM9000,
169 .end = ANW6410_PA_DM9000 + 3,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = ANW6410_PA_DM9000 + 4,
174 .end = ANW6410_PA_DM9000 + 4 + 500,
175 .flags = IORESOURCE_MEM,
176 },
177 [2] = {
178 .start = IRQ_EINT(15),
179 .end = IRQ_EINT(15),
180 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
181 },
182};
183
184static struct dm9000_plat_data anw6410_dm9000_pdata = {
185 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
186 /* dev_addr can be set to provide hwaddr. */
187};
188
189static struct platform_device anw6410_device_eth = {
190 .name = "dm9000",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
193 .resource = anw6410_dm9000_resource,
194 .dev = {
195 .platform_data = &anw6410_dm9000_pdata,
196 },
197};
198
199static struct map_desc anw6410_iodesc[] __initdata = {
200 {
201 .virtual = (unsigned long)ANW6410_VA_EXTDEV,
202 .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
203 .length = SZ_64K,
204 .type = MT_DEVICE,
205 },
206};
207
208static struct platform_device *anw6410_devices[] __initdata = {
209 &s3c_device_fb,
210 &anw6410_lcd_powerdev,
211 &anw6410_device_eth,
212};
213
214static void __init anw6410_map_io(void)
215{
216 s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
217 s3c24xx_init_clocks(12000000);
218 s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
219
220 anw6410_lcd_mode_set();
221}
222
223static void __init anw6410_machine_init(void)
224{
225 s3c_fb_set_platdata(&anw6410_lcd_pdata);
226
227 gpio_request(S3C64XX_GPF(1), "panel power");
228 gpio_request(S3C64XX_GPF(4), "LCD backlight");
229
230 anw6410_dm9000_enable();
231
232 platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
233}
234
235MACHINE_START(ANW6410, "A&W6410")
236 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
237 .phys_io = S3C_PA_UART & 0xfff00000,
238 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
239 .boot_params = S3C64XX_PA_SDRAM + 0x100,
240
241 .init_irq = s3c6410_init_irq,
242 .map_io = anw6410_map_io,
243 .init_machine = anw6410_machine_init,
244 .timer = &s3c24xx_timer,
245MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
new file mode 100644
index 000000000000..284886c26a28
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -0,0 +1,276 @@
1/* mach-hmt.c - Platform code for Airgoo HMT
2 *
3 * Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/serial_core.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/i2c.h>
17#include <linux/fb.h>
18#include <linux/gpio.h>
19#include <linux/delay.h>
20#include <linux/leds.h>
21#include <linux/pwm_backlight.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <mach/regs-fb.h>
31#include <mach/map.h>
32
33#include <asm/irq.h>
34#include <asm/mach-types.h>
35
36#include <plat/regs-serial.h>
37#include <plat/iic.h>
38#include <plat/fb.h>
39#include <plat/nand.h>
40
41#include <plat/s3c6410.h>
42#include <plat/clock.h>
43#include <plat/devs.h>
44#include <plat/cpu.h>
45
46#define UCON S3C2410_UCON_DEFAULT
47#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
48#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
49
50static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
51 [0] = {
52 .hwport = 0,
53 .flags = 0,
54 .ucon = UCON,
55 .ulcon = ULCON,
56 .ufcon = UFCON,
57 },
58 [1] = {
59 .hwport = 1,
60 .flags = 0,
61 .ucon = UCON,
62 .ulcon = ULCON,
63 .ufcon = UFCON,
64 },
65 [2] = {
66 .hwport = 2,
67 .flags = 0,
68 .ucon = UCON,
69 .ulcon = ULCON,
70 .ufcon = UFCON,
71 },
72};
73
74static int hmt_bl_init(struct device *dev)
75{
76 int ret;
77
78 ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
79 if (!ret)
80 ret = gpio_direction_output(S3C64XX_GPB(4), 0);
81
82 return ret;
83}
84
85static int hmt_bl_notify(int brightness)
86{
87 /*
88 * translate from CIELUV/CIELAB L*->brightness, E.G. from
89 * perceived luminance to light output. Assumes range 0..25600
90 */
91 if (brightness < 0x800) {
92 /* Y = Yn * L / 903.3 */
93 brightness = (100*256 * brightness + 231245/2) / 231245;
94 } else {
95 /* Y = Yn * ((L + 16) / 116 )^3 */
96 int t = (brightness*4 + 16*1024 + 58)/116;
97 brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
98 }
99
100 gpio_set_value(S3C64XX_GPB(4), brightness);
101
102 return brightness;
103}
104
105static void hmt_bl_exit(struct device *dev)
106{
107 gpio_free(S3C64XX_GPB(4));
108}
109
110static struct platform_pwm_backlight_data hmt_backlight_data = {
111 .pwm_id = 1,
112 .max_brightness = 100 * 256,
113 .dft_brightness = 40 * 256,
114 .pwm_period_ns = 1000000000 / (100 * 256 * 20),
115 .init = hmt_bl_init,
116 .notify = hmt_bl_notify,
117 .exit = hmt_bl_exit,
118
119};
120
121static struct platform_device hmt_backlight_device = {
122 .name = "pwm-backlight",
123 .dev = {
124 .parent = &s3c_device_timer[1].dev,
125 .platform_data = &hmt_backlight_data,
126 },
127};
128
129static struct s3c_fb_pd_win hmt_fb_win0 = {
130 .win_mode = {
131 .pixclock = 41094,
132 .left_margin = 8,
133 .right_margin = 13,
134 .upper_margin = 7,
135 .lower_margin = 5,
136 .hsync_len = 3,
137 .vsync_len = 1,
138 .xres = 800,
139 .yres = 480,
140 },
141 .max_bpp = 32,
142 .default_bpp = 16,
143};
144
145/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
146static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
147 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
148 .win[0] = &hmt_fb_win0,
149 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
150 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
151};
152
153static struct mtd_partition hmt_nand_part[] = {
154 [0] = {
155 .name = "uboot",
156 .size = SZ_512K,
157 .offset = 0,
158 },
159 [1] = {
160 .name = "uboot-env1",
161 .size = SZ_256K,
162 .offset = SZ_512K,
163 },
164 [2] = {
165 .name = "uboot-env2",
166 .size = SZ_256K,
167 .offset = SZ_512K + SZ_256K,
168 },
169 [3] = {
170 .name = "kernel",
171 .size = SZ_2M,
172 .offset = SZ_1M,
173 },
174 [4] = {
175 .name = "rootfs",
176 .size = MTDPART_SIZ_FULL,
177 .offset = SZ_1M + SZ_2M,
178 },
179};
180
181static struct s3c2410_nand_set hmt_nand_sets[] = {
182 [0] = {
183 .name = "nand",
184 .nr_chips = 1,
185 .nr_partitions = ARRAY_SIZE(hmt_nand_part),
186 .partitions = hmt_nand_part,
187 },
188};
189
190static struct s3c2410_platform_nand hmt_nand_info = {
191 .tacls = 25,
192 .twrph0 = 55,
193 .twrph1 = 40,
194 .nr_sets = ARRAY_SIZE(hmt_nand_sets),
195 .sets = hmt_nand_sets,
196};
197
198static struct gpio_led hmt_leds[] = {
199 { /* left function keys */
200 .name = "left:blue",
201 .gpio = S3C64XX_GPO(12),
202 .default_trigger = "default-on",
203 },
204 { /* right function keys - red */
205 .name = "right:red",
206 .gpio = S3C64XX_GPO(13),
207 },
208 { /* right function keys - green */
209 .name = "right:green",
210 .gpio = S3C64XX_GPO(14),
211 },
212 { /* right function keys - blue */
213 .name = "right:blue",
214 .gpio = S3C64XX_GPO(15),
215 .default_trigger = "default-on",
216 },
217};
218
219static struct gpio_led_platform_data hmt_led_data = {
220 .num_leds = ARRAY_SIZE(hmt_leds),
221 .leds = hmt_leds,
222};
223
224static struct platform_device hmt_leds_device = {
225 .name = "leds-gpio",
226 .id = -1,
227 .dev.platform_data = &hmt_led_data,
228};
229
230static struct map_desc hmt_iodesc[] = {};
231
232static struct platform_device *hmt_devices[] __initdata = {
233 &s3c_device_i2c0,
234 &s3c_device_nand,
235 &s3c_device_fb,
236 &s3c_device_ohci,
237 &s3c_device_timer[1],
238 &hmt_backlight_device,
239 &hmt_leds_device,
240};
241
242static void __init hmt_map_io(void)
243{
244 s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
245 s3c24xx_init_clocks(12000000);
246 s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
247}
248
249static void __init hmt_machine_init(void)
250{
251 s3c_i2c0_set_platdata(NULL);
252 s3c_fb_set_platdata(&hmt_lcd_pdata);
253 s3c_nand_set_platdata(&hmt_nand_info);
254
255 gpio_request(S3C64XX_GPC(7), "usb power");
256 gpio_direction_output(S3C64XX_GPC(7), 0);
257 gpio_request(S3C64XX_GPM(0), "usb power");
258 gpio_direction_output(S3C64XX_GPM(0), 1);
259 gpio_request(S3C64XX_GPK(7), "usb power");
260 gpio_direction_output(S3C64XX_GPK(7), 1);
261 gpio_request(S3C64XX_GPF(13), "usb power");
262 gpio_direction_output(S3C64XX_GPF(13), 1);
263
264 platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
265}
266
267MACHINE_START(HMT, "Airgoo-HMT")
268 /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
269 .phys_io = S3C_PA_UART & 0xfff00000,
270 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
271 .boot_params = S3C64XX_PA_SDRAM + 0x100,
272 .init_irq = s3c6410_init_irq,
273 .map_io = hmt_map_io,
274 .init_machine = hmt_machine_init,
275 .timer = &s3c24xx_timer,
276MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
new file mode 100644
index 000000000000..9be92ddd2176
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -0,0 +1,107 @@
1/*
2 * linux/arch/arm/mach-s3c64xx/mach-ncp.c
3 *
4 * Copyright (C) 2008-2009 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/i2c.h>
22#include <linux/fb.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25
26#include <video/platform_lcd.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h>
33#include <mach/regs-fb.h>
34#include <mach/map.h>
35
36#include <asm/irq.h>
37#include <asm/mach-types.h>
38
39#include <plat/regs-serial.h>
40#include <plat/iic.h>
41#include <plat/fb.h>
42
43#include <plat/s3c6410.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47
48#define UCON S3C2410_UCON_DEFAULT
49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
50#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
51
52static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
53 /* REVISIT: NCP uses only serial 1, 2 */
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = UCON,
58 .ulcon = ULCON,
59 .ufcon = UFCON,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = UCON,
65 .ulcon = ULCON,
66 .ufcon = UFCON,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75};
76
77static struct platform_device *ncp_devices[] __initdata = {
78 &s3c_device_hsmmc1,
79 &s3c_device_i2c0,
80};
81
82static struct map_desc ncp_iodesc[] __initdata = {};
83
84static void __init ncp_map_io(void)
85{
86 s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
87 s3c24xx_init_clocks(12000000);
88 s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
89}
90
91static void __init ncp_machine_init(void)
92{
93 s3c_i2c0_set_platdata(NULL);
94
95 platform_add_devices(ncp_devices, ARRAY_SIZE(ncp_devices));
96}
97
98MACHINE_START(NCP, "NCP")
99 /* Maintainer: Samsung Electronics */
100 .phys_io = S3C_PA_UART & 0xfff00000,
101 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
102 .boot_params = S3C64XX_PA_SDRAM + 0x100,
103 .init_irq = s3c6410_init_irq,
104 .map_io = ncp_map_io,
105 .init_machine = ncp_machine_init,
106 .timer = &s3c24xx_timer,
107MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
new file mode 100644
index 000000000000..ba8a052a6142
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -0,0 +1,96 @@
1/* linux/arch/arm/mach-s3c64xx/mach-smdk6400.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/i2c.h>
21#include <linux/io.h>
22
23#include <asm/mach-types.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31
32#include <plat/regs-serial.h>
33
34#include <plat/s3c6400.h>
35#include <plat/clock.h>
36#include <plat/devs.h>
37#include <plat/cpu.h>
38#include <plat/iic.h>
39
40#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
41#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
42#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
43
44static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = 0x3c5,
49 .ulcon = 0x03,
50 .ufcon = 0x51,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = 0x3c5,
56 .ulcon = 0x03,
57 .ufcon = 0x51,
58 },
59};
60
61static struct map_desc smdk6400_iodesc[] = {};
62
63static void __init smdk6400_map_io(void)
64{
65 s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
66 s3c24xx_init_clocks(12000000);
67 s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
68}
69
70static struct platform_device *smdk6400_devices[] __initdata = {
71 &s3c_device_hsmmc1,
72 &s3c_device_i2c0,
73};
74
75static struct i2c_board_info i2c_devs[] __initdata = {
76 { I2C_BOARD_INFO("wm8753", 0x1A), },
77 { I2C_BOARD_INFO("24c08", 0x50), },
78};
79
80static void __init smdk6400_machine_init(void)
81{
82 i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
83 platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
84}
85
86MACHINE_START(SMDK6400, "SMDK6400")
87 /* Maintainer: Ben Dooks <ben@fluff.org> */
88 .phys_io = S3C_PA_UART & 0xfff00000,
89 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
90 .boot_params = S3C64XX_PA_SDRAM + 0x100,
91
92 .init_irq = s3c6400_init_irq,
93 .map_io = smdk6400_map_io,
94 .init_machine = smdk6400_machine_init,
95 .timer = &s3c24xx_timer,
96MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
new file mode 100644
index 000000000000..6e6ff354da42
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -0,0 +1,491 @@
1/* linux/arch/arm/mach-s3c64xx/mach-smdk6410.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/timer.h>
19#include <linux/init.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/i2c.h>
24#include <linux/fb.h>
25#include <linux/gpio.h>
26#include <linux/delay.h>
27#include <linux/smsc911x.h>
28#include <linux/regulator/fixed.h>
29
30#ifdef CONFIG_SMDK6410_WM1190_EV1
31#include <linux/mfd/wm8350/core.h>
32#include <linux/mfd/wm8350/pmic.h>
33#endif
34
35#include <video/platform_lcd.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
42#include <mach/regs-fb.h>
43#include <mach/map.h>
44
45#include <asm/irq.h>
46#include <asm/mach-types.h>
47
48#include <plat/regs-serial.h>
49#include <plat/regs-modem.h>
50#include <plat/regs-gpio.h>
51#include <plat/regs-sys.h>
52#include <plat/regs-srom.h>
53#include <plat/iic.h>
54#include <plat/fb.h>
55#include <plat/gpio-cfg.h>
56
57#include <plat/s3c6410.h>
58#include <plat/clock.h>
59#include <plat/devs.h>
60#include <plat/cpu.h>
61
62#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
63#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
64#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
65
66static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
67 [0] = {
68 .hwport = 0,
69 .flags = 0,
70 .ucon = UCON,
71 .ulcon = ULCON,
72 .ufcon = UFCON,
73 },
74 [1] = {
75 .hwport = 1,
76 .flags = 0,
77 .ucon = UCON,
78 .ulcon = ULCON,
79 .ufcon = UFCON,
80 },
81 [2] = {
82 .hwport = 2,
83 .flags = 0,
84 .ucon = UCON,
85 .ulcon = ULCON,
86 .ufcon = UFCON,
87 },
88 [3] = {
89 .hwport = 3,
90 .flags = 0,
91 .ucon = UCON,
92 .ulcon = ULCON,
93 .ufcon = UFCON,
94 },
95};
96
97/* framebuffer and LCD setup. */
98
99/* GPF15 = LCD backlight control
100 * GPF13 => Panel power
101 * GPN5 = LCD nRESET signal
102 * PWM_TOUT1 => backlight brightness
103 */
104
105static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
106 unsigned int power)
107{
108 if (power) {
109 gpio_direction_output(S3C64XX_GPF(13), 1);
110 gpio_direction_output(S3C64XX_GPF(15), 1);
111
112 /* fire nRESET on power up */
113 gpio_direction_output(S3C64XX_GPN(5), 0);
114 msleep(10);
115 gpio_direction_output(S3C64XX_GPN(5), 1);
116 msleep(1);
117 } else {
118 gpio_direction_output(S3C64XX_GPF(15), 0);
119 gpio_direction_output(S3C64XX_GPF(13), 0);
120 }
121}
122
123static struct plat_lcd_data smdk6410_lcd_power_data = {
124 .set_power = smdk6410_lcd_power_set,
125};
126
127static struct platform_device smdk6410_lcd_powerdev = {
128 .name = "platform-lcd",
129 .dev.parent = &s3c_device_fb.dev,
130 .dev.platform_data = &smdk6410_lcd_power_data,
131};
132
133static struct s3c_fb_pd_win smdk6410_fb_win0 = {
134 /* this is to ensure we use win0 */
135 .win_mode = {
136 .pixclock = 41094,
137 .left_margin = 8,
138 .right_margin = 13,
139 .upper_margin = 7,
140 .lower_margin = 5,
141 .hsync_len = 3,
142 .vsync_len = 1,
143 .xres = 800,
144 .yres = 480,
145 },
146 .max_bpp = 32,
147 .default_bpp = 16,
148};
149
150/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
151static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
152 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
153 .win[0] = &smdk6410_fb_win0,
154 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
155 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
156};
157
158/*
159 * Configuring Ethernet on SMDK6410
160 *
161 * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
162 * The constant address below corresponds to nCS1
163 *
164 * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
165 * 2) CFG6 needs to be switched to "LAN9115" side
166 */
167
168static struct resource smdk6410_smsc911x_resources[] = {
169 [0] = {
170 .start = S3C64XX_PA_XM0CSN1,
171 .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 [1] = {
175 .start = S3C_EINT(10),
176 .end = S3C_EINT(10),
177 .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
178 },
179};
180
181static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
182 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
183 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
184 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
185 .phy_interface = PHY_INTERFACE_MODE_MII,
186};
187
188
189static struct platform_device smdk6410_smsc911x = {
190 .name = "smsc911x",
191 .id = -1,
192 .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources),
193 .resource = &smdk6410_smsc911x_resources[0],
194 .dev = {
195 .platform_data = &smdk6410_smsc911x_pdata,
196 },
197};
198
199#ifdef CONFIG_REGULATOR
200static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
201 {
202 /* WM8580 */
203 .supply = "PVDD",
204 .dev_name = "0-001b",
205 },
206 {
207 /* WM8580 */
208 .supply = "AVDD",
209 .dev_name = "0-001b",
210 },
211};
212
213static struct regulator_init_data smdk6410_b_pwr_5v_data = {
214 .constraints = {
215 .always_on = 1,
216 },
217 .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
218 .consumer_supplies = smdk6410_b_pwr_5v_consumers,
219};
220
221static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
222 .supply_name = "B_PWR_5V",
223 .microvolts = 5000000,
224 .init_data = &smdk6410_b_pwr_5v_data,
225 .gpio = -EINVAL,
226};
227
228static struct platform_device smdk6410_b_pwr_5v = {
229 .name = "reg-fixed-voltage",
230 .id = -1,
231 .dev = {
232 .platform_data = &smdk6410_b_pwr_5v_pdata,
233 },
234};
235#endif
236
237static struct map_desc smdk6410_iodesc[] = {};
238
239static struct platform_device *smdk6410_devices[] __initdata = {
240#ifdef CONFIG_SMDK6410_SD_CH0
241 &s3c_device_hsmmc0,
242#endif
243#ifdef CONFIG_SMDK6410_SD_CH1
244 &s3c_device_hsmmc1,
245#endif
246 &s3c_device_i2c0,
247 &s3c_device_i2c1,
248 &s3c_device_fb,
249 &s3c_device_ohci,
250 &s3c_device_usb_hsotg,
251
252#ifdef CONFIG_REGULATOR
253 &smdk6410_b_pwr_5v,
254#endif
255 &smdk6410_lcd_powerdev,
256
257 &smdk6410_smsc911x,
258};
259
260#ifdef CONFIG_SMDK6410_WM1190_EV1
261/* S3C64xx internal logic & PLL */
262static struct regulator_init_data wm8350_dcdc1_data = {
263 .constraints = {
264 .name = "PVDD_INT/PVDD_PLL",
265 .min_uV = 1200000,
266 .max_uV = 1200000,
267 .always_on = 1,
268 .apply_uV = 1,
269 },
270};
271
272/* Memory */
273static struct regulator_init_data wm8350_dcdc3_data = {
274 .constraints = {
275 .name = "PVDD_MEM",
276 .min_uV = 1800000,
277 .max_uV = 1800000,
278 .always_on = 1,
279 .state_mem = {
280 .uV = 1800000,
281 .mode = REGULATOR_MODE_NORMAL,
282 .enabled = 1,
283 },
284 .initial_state = PM_SUSPEND_MEM,
285 },
286};
287
288/* USB, EXT, PCM, ADC/DAC, USB, MMC */
289static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
290 {
291 /* WM8580 */
292 .supply = "DVDD",
293 .dev_name = "0-001b",
294 },
295};
296
297static struct regulator_init_data wm8350_dcdc4_data = {
298 .constraints = {
299 .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
300 .min_uV = 3000000,
301 .max_uV = 3000000,
302 .always_on = 1,
303 },
304 .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
305 .consumer_supplies = wm8350_dcdc4_consumers,
306};
307
308/* ARM core */
309static struct regulator_consumer_supply dcdc6_consumers[] = {
310 {
311 .supply = "vddarm",
312 }
313};
314
315static struct regulator_init_data wm8350_dcdc6_data = {
316 .constraints = {
317 .name = "PVDD_ARM",
318 .min_uV = 1000000,
319 .max_uV = 1300000,
320 .always_on = 1,
321 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
322 },
323 .num_consumer_supplies = ARRAY_SIZE(dcdc6_consumers),
324 .consumer_supplies = dcdc6_consumers,
325};
326
327/* Alive */
328static struct regulator_init_data wm8350_ldo1_data = {
329 .constraints = {
330 .name = "PVDD_ALIVE",
331 .min_uV = 1200000,
332 .max_uV = 1200000,
333 .always_on = 1,
334 .apply_uV = 1,
335 },
336};
337
338/* OTG */
339static struct regulator_init_data wm8350_ldo2_data = {
340 .constraints = {
341 .name = "PVDD_OTG",
342 .min_uV = 3300000,
343 .max_uV = 3300000,
344 .always_on = 1,
345 },
346};
347
348/* LCD */
349static struct regulator_init_data wm8350_ldo3_data = {
350 .constraints = {
351 .name = "PVDD_LCD",
352 .min_uV = 3000000,
353 .max_uV = 3000000,
354 .always_on = 1,
355 },
356};
357
358/* OTGi/1190-EV1 HPVDD & AVDD */
359static struct regulator_init_data wm8350_ldo4_data = {
360 .constraints = {
361 .name = "PVDD_OTGI/HPVDD/AVDD",
362 .min_uV = 1200000,
363 .max_uV = 1200000,
364 .apply_uV = 1,
365 .always_on = 1,
366 },
367};
368
369static struct {
370 int regulator;
371 struct regulator_init_data *initdata;
372} wm1190_regulators[] = {
373 { WM8350_DCDC_1, &wm8350_dcdc1_data },
374 { WM8350_DCDC_3, &wm8350_dcdc3_data },
375 { WM8350_DCDC_4, &wm8350_dcdc4_data },
376 { WM8350_DCDC_6, &wm8350_dcdc6_data },
377 { WM8350_LDO_1, &wm8350_ldo1_data },
378 { WM8350_LDO_2, &wm8350_ldo2_data },
379 { WM8350_LDO_3, &wm8350_ldo3_data },
380 { WM8350_LDO_4, &wm8350_ldo4_data },
381};
382
383static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
384{
385 int i;
386
387 /* Configure the IRQ line */
388 s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
389
390 /* Instantiate the regulators */
391 for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
392 wm8350_register_regulator(wm8350,
393 wm1190_regulators[i].regulator,
394 wm1190_regulators[i].initdata);
395
396 return 0;
397}
398
399static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
400 .init = smdk6410_wm8350_init,
401 .irq_high = 1,
402 .irq_base = IRQ_BOARD_START,
403};
404#endif
405
406static struct i2c_board_info i2c_devs0[] __initdata = {
407 { I2C_BOARD_INFO("24c08", 0x50), },
408 { I2C_BOARD_INFO("wm8580", 0x1b), },
409
410#ifdef CONFIG_SMDK6410_WM1190_EV1
411 { I2C_BOARD_INFO("wm8350", 0x1a),
412 .platform_data = &smdk6410_wm8350_pdata,
413 .irq = S3C_EINT(12),
414 },
415#endif
416};
417
418static struct i2c_board_info i2c_devs1[] __initdata = {
419 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
420};
421
422static void __init smdk6410_map_io(void)
423{
424 u32 tmp;
425
426 s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
427 s3c24xx_init_clocks(12000000);
428 s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
429
430 /* set the LCD type */
431
432 tmp = __raw_readl(S3C64XX_SPCON);
433 tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
434 tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
435 __raw_writel(tmp, S3C64XX_SPCON);
436
437 /* remove the lcd bypass */
438 tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
439 tmp &= ~MIFPCON_LCD_BYPASS;
440 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
441}
442
443static void __init smdk6410_machine_init(void)
444{
445 u32 cs1;
446
447 s3c_i2c0_set_platdata(NULL);
448 s3c_i2c1_set_platdata(NULL);
449 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
450
451 /* configure nCS1 width to 16 bits */
452
453 cs1 = __raw_readl(S3C64XX_SROM_BW) &
454 ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
455 cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
456 (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
457 (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
458 S3C64XX_SROM_BW__NCS1__SHIFT;
459 __raw_writel(cs1, S3C64XX_SROM_BW);
460
461 /* set timing for nCS1 suitable for ethernet chip */
462
463 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
464 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
465 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
466 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
467 (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
468 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
469 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
470
471 gpio_request(S3C64XX_GPN(5), "LCD power");
472 gpio_request(S3C64XX_GPF(13), "LCD power");
473 gpio_request(S3C64XX_GPF(15), "LCD power");
474
475 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
476 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
477
478 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
479}
480
481MACHINE_START(SMDK6410, "SMDK6410")
482 /* Maintainer: Ben Dooks <ben@fluff.org> */
483 .phys_io = S3C_PA_UART & 0xfff00000,
484 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
485 .boot_params = S3C64XX_PA_SDRAM + 0x100,
486
487 .init_irq = s3c6410_init_irq,
488 .map_io = smdk6410_map_io,
489 .init_machine = smdk6410_machine_init,
490 .timer = &s3c24xx_timer,
491MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
new file mode 100644
index 000000000000..884858a78d49
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -0,0 +1,92 @@
1/* linux/arch/arm/mach-s3c64xx/cpu.c
2 *
3 * Copyright 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/sysdev.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <mach/hardware.h>
29#include <asm/irq.h>
30
31#include <plat/cpu-freq.h>
32#include <plat/regs-serial.h>
33#include <plat/regs-clock.h>
34
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/clock.h>
38#include <plat/sdhci.h>
39#include <plat/iic-core.h>
40#include <plat/s3c6400.h>
41
42void __init s3c6400_map_io(void)
43{
44 /* setup SDHCI */
45
46 s3c6400_default_sdhci0();
47 s3c6400_default_sdhci1();
48 s3c6400_default_sdhci2();
49
50 /* the i2c devices are directly compatible with s3c2440 */
51 s3c_i2c0_setname("s3c2440-i2c");
52
53 s3c_device_nand.name = "s3c6400-nand";
54}
55
56void __init s3c6400_init_clocks(int xtal)
57{
58 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
59 s3c24xx_register_baseclocks(xtal);
60 s3c64xx_register_clocks();
61 s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK);
62 s3c6400_setup_clocks();
63}
64
65void __init s3c6400_init_irq(void)
66{
67 /* VIC0 does not have IRQS 5..7,
68 * VIC1 is fully populated. */
69 s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
70}
71
72struct sysdev_class s3c6400_sysclass = {
73 .name = "s3c6400-core",
74};
75
76static struct sys_device s3c6400_sysdev = {
77 .cls = &s3c6400_sysclass,
78};
79
80static int __init s3c6400_core_init(void)
81{
82 return sysdev_class_register(&s3c6400_sysclass);
83}
84
85core_initcall(s3c6400_core_init);
86
87int __init s3c6400_init(void)
88{
89 printk("S3C6400: Initialising architecture\n");
90
91 return sysdev_register(&s3c6400_sysdev);
92}
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
new file mode 100644
index 000000000000..dd55c6a74ed5
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -0,0 +1,105 @@
1/* linux/arch/arm/mach-s3c64xx/s3c6410.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/sysdev.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <plat/cpu-freq.h>
33#include <plat/regs-serial.h>
34#include <plat/regs-clock.h>
35
36#include <plat/cpu.h>
37#include <plat/devs.h>
38#include <plat/clock.h>
39#include <plat/sdhci.h>
40#include <plat/iic-core.h>
41#include <plat/s3c6400.h>
42#include <plat/s3c6410.h>
43
44/* Initial IO mappings */
45
46static struct map_desc s3c6410_iodesc[] __initdata = {
47};
48
49/* s3c6410_map_io
50 *
51 * register the standard cpu IO areas
52*/
53
54void __init s3c6410_map_io(void)
55{
56 iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
57
58 /* initialise device information early */
59 s3c6410_default_sdhci0();
60 s3c6410_default_sdhci1();
61 s3c6410_default_sdhci2();
62
63 /* the i2c devices are directly compatible with s3c2440 */
64 s3c_i2c0_setname("s3c2440-i2c");
65 s3c_i2c1_setname("s3c2440-i2c");
66
67 s3c_device_nand.name = "s3c6400-nand";
68}
69
70void __init s3c6410_init_clocks(int xtal)
71{
72 printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
73 s3c24xx_register_baseclocks(xtal);
74 s3c64xx_register_clocks();
75 s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK);
76 s3c6400_setup_clocks();
77}
78
79void __init s3c6410_init_irq(void)
80{
81 /* VIC0 is missing IRQ7, VIC1 is fully populated. */
82 s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
83}
84
85struct sysdev_class s3c6410_sysclass = {
86 .name = "s3c6410-core",
87};
88
89static struct sys_device s3c6410_sysdev = {
90 .cls = &s3c6410_sysclass,
91};
92
93static int __init s3c6410_core_init(void)
94{
95 return sysdev_class_register(&s3c6410_sysclass);
96}
97
98core_initcall(s3c6410_core_init);
99
100int __init s3c6410_init(void)
101{
102 printk("S3C6410: Initialising architecture\n");
103
104 return sysdev_register(&s3c6410_sysdev);
105}
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c
new file mode 100644
index 000000000000..ec96a5863c0c
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6400.c
@@ -0,0 +1,63 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c6400_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "mmc_bus",
33 /* [3] = "48m", - note not successfully used yet */
34};
35
36void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
37 void __iomem *r,
38 struct mmc_ios *ios,
39 struct mmc_card *card)
40{
41 u32 ctrl2, ctrl3;
42
43 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
46 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
47 S3C_SDHCI_CTRL2_ENFBCLKRX |
48 S3C_SDHCI_CTRL2_DFCNT_NONE |
49 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
50
51 if (ios->clock < 25 * 1000000)
52 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
53 S3C_SDHCI_CTRL3_FCSEL2 |
54 S3C_SDHCI_CTRL3_FCSEL1 |
55 S3C_SDHCI_CTRL3_FCSEL0);
56 else
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
58
59 printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
60 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
61 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
62}
63
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c
new file mode 100644
index 000000000000..8d714a1f6dc7
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-s3c6410.c
@@ -0,0 +1,68 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <plat/regs-sdhci.h>
25#include <plat/sdhci.h>
26
27/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
28
29char *s3c6410_hsmmc_clksrcs[4] = {
30 [0] = "hsmmc",
31 [1] = "hsmmc",
32 [2] = "mmc_bus",
33 /* [3] = "48m", - note not successfully used yet */
34};
35
36
37void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
38 void __iomem *r,
39 struct mmc_ios *ios,
40 struct mmc_card *card)
41{
42 u32 ctrl2, ctrl3;
43
44 /* don't need to alter anything acording to card-type */
45
46 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
47
48 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
49 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
50 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
51 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
52 S3C_SDHCI_CTRL2_ENFBCLKRX |
53 S3C_SDHCI_CTRL2_DFCNT_NONE |
54 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
55
56 if (ios->clock < 25 * 1000000)
57 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
58 S3C_SDHCI_CTRL3_FCSEL2 |
59 S3C_SDHCI_CTRL3_FCSEL1 |
60 S3C_SDHCI_CTRL3_FCSEL0);
61 else
62 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
63
64 printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
65 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
66 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
67}
68
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 15:48:59 -0500