aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c6400
diff options
context:
space:
mode:
authorBen Dooks <ben-linux@fluff.org>2008-11-19 10:41:30 -0500
committerBen Dooks <ben-linux@fluff.org>2008-12-15 18:55:10 -0500
commit8f995cc3ac94b114fe84782b023d8706d1adf960 (patch)
tree8c9fe456c1d81e394786cf94f32603a8d1a8fe98 /arch/arm/mach-s3c6400
parent713e9dede63c775cb42c63178a6447f2c28ec2cd (diff)
[ARM] S3C: Add register defines for new style framebuffer
Provide the initial register definitions for the newer style of framebuffer cores found in the Samsung SoCs such as S3C2450, S3C64XX. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c6400')
-rw-r--r--arch/arm/mach-s3c6400/include/mach/regs-fb.h259
1 files changed, 259 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
new file mode 100644
index 000000000000..47019795ce06
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
@@ -0,0 +1,259 @@
1/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
44#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
45#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
46#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
47
48/* Video buffer addresses */
49
50#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
51#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
52#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
53#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
54#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
55
56#define VIDINTCON0 (0x130)
57
58#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
59
60/* WINCONx */
61
62#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
63#define WINCONx_CSCWIDTH_SHIFT (26)
64#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
65#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
66
67#define WINCONx_ENLOCAL (1 << 22)
68#define WINCONx_BUFSTATUS (1 << 21)
69#define WINCONx_BUFSEL (1 << 20)
70#define WINCONx_BUFAUTOEN (1 << 19)
71#define WINCONx_YCbCr (1 << 13)
72
73#define WINCON1_LOCALSEL_CAMIF (1 << 23)
74
75#define WINCON2_LOCALSEL_CAMIF (1 << 23)
76#define WINCON2_BLD_PIX (1 << 6)
77
78#define WINCON2_ALPHA_SEL (1 << 1)
79#define WINCON2_BPPMODE_MASK (0xf << 2)
80#define WINCON2_BPPMODE_SHIFT (2)
81#define WINCON2_BPPMODE_1BPP (0x0 << 2)
82#define WINCON2_BPPMODE_2BPP (0x1 << 2)
83#define WINCON2_BPPMODE_4BPP (0x2 << 2)
84#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
85#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
86#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
87#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
88#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
89#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
90#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
91#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
92#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
93#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
94#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
95
96#define WINCON3_BLD_PIX (1 << 6)
97
98#define WINCON3_ALPHA_SEL (1 << 1)
99#define WINCON3_BPPMODE_MASK (0xf << 2)
100#define WINCON3_BPPMODE_SHIFT (2)
101#define WINCON3_BPPMODE_1BPP (0x0 << 2)
102#define WINCON3_BPPMODE_2BPP (0x1 << 2)
103#define WINCON3_BPPMODE_4BPP (0x2 << 2)
104#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
105#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
106#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
107#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
108#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
109#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
110#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
111#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
112#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
113#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
114
115#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
116#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
117#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
118
119#define DITHMODE (0x170)
120#define WINxMAP(_win) (0x180 + ((_win) * 4))
121
122
123#define DITHMODE_R_POS_MASK (0x3 << 5)
124#define DITHMODE_R_POS_SHIFT (5)
125#define DITHMODE_R_POS_8BIT (0x0 << 5)
126#define DITHMODE_R_POS_6BIT (0x1 << 5)
127#define DITHMODE_R_POS_5BIT (0x2 << 5)
128
129#define DITHMODE_G_POS_MASK (0x3 << 3)
130#define DITHMODE_G_POS_SHIFT (3)
131#define DITHMODE_G_POS_8BIT (0x0 << 3)
132#define DITHMODE_G_POS_6BIT (0x1 << 3)
133#define DITHMODE_G_POS_5BIT (0x2 << 3)
134
135#define DITHMODE_B_POS_MASK (0x3 << 1)
136#define DITHMODE_B_POS_SHIFT (1)
137#define DITHMODE_B_POS_8BIT (0x0 << 1)
138#define DITHMODE_B_POS_6BIT (0x1 << 1)
139#define DITHMODE_B_POS_5BIT (0x2 << 1)
140
141#define DITHMODE_DITH_EN (1 << 0)
142
143#define WPALCON (0x1A0)
144
145#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
146#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
147#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
148
149/* Palette registers */
150
151#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
152#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
153#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
154#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
155#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
156
157/* system specific implementation code for palette sizes, and other
158 * information that changes depending on which architecture is being
159 * compiled.
160*/
161
162/* return true if window _win has OSD register D */
163#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
164
165static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
166{
167 if (win < 2)
168 return 256;
169 if (win < 4)
170 return 16;
171 if (win == 4)
172 return 4;
173
174 BUG(); /* shouldn't get here */
175}
176
177static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
178{
179 /* all windows can do 1/2 bpp */
180
181 if ((bpp == 25 || bpp == 19) && win == 0)
182 return 0; /* win 0 does not have 19 or 25bpp modes */
183
184 if (bpp == 4 && win == 4)
185 return 0;
186
187 if (bpp == 8 && (win >= 3))
188 return 0; /* win 3/4 cannot do 8bpp in any mode */
189
190 return 1;
191}
192
193static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
194{
195 switch (window) {
196 case 0: return WIN0_PAL(reg);
197 case 1: return WIN1_PAL(reg);
198 case 2: return WIN2_PAL(reg);
199 case 3: return WIN3_PAL(reg);
200 case 4: return WIN4_PAL(reg);
201 }
202
203 BUG();
204}
205
206static inline int s3c_fb_pal_is16(unsigned int window)
207{
208 return window > 1;
209}
210
211struct s3c_fb_palette {
212 struct fb_bitfield r;
213 struct fb_bitfield g;
214 struct fb_bitfield b;
215 struct fb_bitfield a;
216};
217
218static inline void s3c_fb_init_palette(unsigned int window,
219 struct s3c_fb_palette *palette)
220{
221 if (window < 2) {
222 /* Windows 0/1 are 8/8/8 or A/8/8/8 */
223 palette->r.offset = 16;
224 palette->r.length = 8;
225 palette->g.offset = 8;
226 palette->g.length = 8;
227 palette->b.offset = 0;
228 palette->b.length = 8;
229 } else {
230 /* currently we assume RGB 5/6/5 */
231 palette->r.offset = 11;
232 palette->r.length = 5;
233 palette->g.offset = 5;
234 palette->g.length = 6;
235 palette->b.offset = 0;
236 palette->b.length = 5;
237 }
238}
239
240/* Notes on per-window bpp settings
241 *
242 * Value Win0 Win1 Win2 Win3 Win 4
243 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
244 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
245 * 0010 4(P) 4(P) 4(P) 4(P) -none-
246 * 0011 8(P) 8(P) -none- -none- -none-
247 * 0100 -none- 8(A232) 8(A232) -none- -none-
248 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
249 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
250 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
251 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
252 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
253 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
254 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
255 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
256 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
257 * 1110 -none- -none- -none- -none- -none-
258 * 1111 -none- -none- -none- -none- -none-
259*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 09:50:21 -0500