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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-06-10 17:40:55 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-10 17:41:06 -0400
commit547c32aeb5a24178ef20488ae0508efcc32ae8e4 (patch)
treefdc33154820cfddc845cef2f67380dace655b28f /arch/arm/mach-s3c6400/include
parentb0efb42478c81ed0ed9aa0dc444db200c32624f0 (diff)
parent99ae99533a059750c4b0f76295625b8ac5ea751a (diff)
Merge branch for-rmk-devel of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch/arm/mach-s3c6400/include')
-rw-r--r--arch/arm/mach-s3c6400/include/mach/dma.h59
-rw-r--r--arch/arm/mach-s3c6400/include/mach/map.h6
-rw-r--r--arch/arm/mach-s3c6400/include/mach/regs-clock.h16
-rw-r--r--arch/arm/mach-s3c6400/include/mach/system.h8
4 files changed, 87 insertions, 2 deletions
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h
index 9771ac2cb07e..1067619f0ba0 100644
--- a/arch/arm/mach-s3c6400/include/mach/dma.h
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -11,6 +11,63 @@
11#ifndef __ASM_ARCH_DMA_H 11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H __FILE__ 12#define __ASM_ARCH_DMA_H __FILE__
13 13
14/* currently nothing here, placeholder */ 14#define S3C_DMA_CHANNELS (16)
15
16/* see mach-s3c2410/dma.h for notes on dma channel numbers */
17
18/* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
21 */
22enum dma_ch {
23 /* DMA0/SDMA0 */
24 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2,
26 DMACH_UART1,
27 DMACH_UART1_SRC2,
28 DMACH_UART2,
29 DMACH_UART2_SRC2,
30 DMACH_UART3,
31 DMACH_UART3_SRC2,
32 DMACH_PCM0_TX,
33 DMACH_PCM0_RX,
34 DMACH_I2S0_OUT,
35 DMACH_I2S0_IN,
36 DMACH_SPI0_TX,
37 DMACH_SPI0_RX,
38 DMACH_HSI_I2SV40_TX,
39 DMACH_HSI_I2SV40_RX,
40
41 /* DMA1/SDMA1 */
42 DMACH_PCM1_TX = 16,
43 DMACH_PCM1_RX,
44 DMACH_I2S1_OUT,
45 DMACH_I2S1_IN,
46 DMACH_SPI1_TX,
47 DMACH_SPI1_RX,
48 DMACH_AC97_PCMOUT,
49 DMACH_AC97_PCMIN,
50 DMACH_AC97_MICIN,
51 DMACH_PWM,
52 DMACH_IRDA,
53 DMACH_EXTERNAL,
54 DMACH_RES1,
55 DMACH_RES2,
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
59};
60
61static __inline__ int s3c_dma_has_circular(void)
62{
63 /* we will be supporting ciruclar buffers as soon as we have DMA
64 * engine support.
65 */
66 return 1;
67}
68
69#define S3C2410_DMAF_CIRCULAR (1 << 0)
70
71#include <plat/dma.h>
15 72
16#endif /* __ASM_ARCH_IRQ_H */ 73#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 8199972ed5bd..5057d9948d35 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -39,6 +39,8 @@
39#define S3C_VA_UART3 S3C_VA_UARTx(3) 39#define S3C_VA_UART3 S3C_VA_UARTx(3)
40 40
41#define S3C64XX_PA_FB (0x77100000) 41#define S3C64XX_PA_FB (0x77100000)
42#define S3C64XX_PA_USB_HSOTG (0x7C000000)
43#define S3C64XX_PA_WATCHDOG (0x7E004000)
42#define S3C64XX_PA_SYSCON (0x7E00F000) 44#define S3C64XX_PA_SYSCON (0x7E00F000)
43#define S3C64XX_PA_IIS0 (0x7F002000) 45#define S3C64XX_PA_IIS0 (0x7F002000)
44#define S3C64XX_PA_IIS1 (0x7F003000) 46#define S3C64XX_PA_IIS1 (0x7F003000)
@@ -57,6 +59,8 @@
57#define S3C64XX_PA_MODEM (0x74108000) 59#define S3C64XX_PA_MODEM (0x74108000)
58#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) 60#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
59 61
62#define S3C64XX_PA_USBHOST (0x74300000)
63
60/* place VICs close together */ 64/* place VICs close together */
61#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) 65#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
62#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) 66#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
@@ -69,5 +73,7 @@
69#define S3C_PA_IIC S3C64XX_PA_IIC0 73#define S3C_PA_IIC S3C64XX_PA_IIC0
70#define S3C_PA_IIC1 S3C64XX_PA_IIC1 74#define S3C_PA_IIC1 S3C64XX_PA_IIC1
71#define S3C_PA_FB S3C64XX_PA_FB 75#define S3C_PA_FB S3C64XX_PA_FB
76#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
77#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
72 78
73#endif /* __ASM_ARCH_6400_MAP_H */ 79#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
new file mode 100644
index 000000000000..a6c7f4eb3a1b
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - clock register compatibility with s3c24xx
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <plat/regs-clock.h>
16
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h
index 090cfd969bc7..2e58cb7a7147 100644
--- a/arch/arm/mach-s3c6400/include/mach/system.h
+++ b/arch/arm/mach-s3c6400/include/mach/system.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H __FILE__ 12#define __ASM_ARCH_SYSTEM_H __FILE__
13 13
14#include <plat/watchdog-reset.h>
15
14static void arch_idle(void) 16static void arch_idle(void)
15{ 17{
16 /* nothing here yet */ 18 /* nothing here yet */
@@ -18,7 +20,11 @@ static void arch_idle(void)
18 20
19static void arch_reset(char mode, const char *cmd) 21static void arch_reset(char mode, const char *cmd)
20{ 22{
21 /* nothing here yet */ 23 if (mode != 's')
24 arch_wdt_reset();
25
26 /* if all else fails, or mode was for soft, jump to 0 */
27 cpu_reset(0);
22} 28}
23 29
24#endif /* __ASM_ARCH_IRQ_H */ 30#endif /* __ASM_ARCH_IRQ_H */