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authorHeiko Stuebner <heiko@sntech.de>2014-05-08 16:49:36 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-05-12 19:00:45 -0400
commitdefd9da51d1a472ffa7a92ba71ffa07839bdc1a3 (patch)
tree0d9105b3ff04ea3dfcf73d1532d7e9b7a7a16c61 /arch/arm/mach-s3c24xx/s3c244x.c
parent07ee5e7c3ec00b30996160e9a378471872ea779e (diff)
ARM: S3C24XX: remove legacy clock code
With the move to the common clock framework completed for s3c2410, s3c2440 and s3c2442, the legacy clock code for these machines can go away too. This also includes the legacy dclk code, as all legacy users are converted. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/s3c244x.c')
-rw-r--r--arch/arm/mach-s3c24xx/s3c244x.c63
1 files changed, 0 insertions, 63 deletions
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 1d665d50b034..4a64bcc9eb51 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -78,72 +78,9 @@ void __init s3c244x_map_io(void)
78 s3c2410_device_dclk.name = "s3c2440-dclk"; 78 s3c2410_device_dclk.name = "s3c2440-dclk";
79} 79}
80 80
81#ifdef CONFIG_SAMSUNG_CLOCK
82void __init_or_cpufreq s3c244x_setup_clocks(void) 81void __init_or_cpufreq s3c244x_setup_clocks(void)
83{ 82{
84 struct clk *xtal_clk;
85 unsigned long clkdiv;
86 unsigned long camdiv;
87 unsigned long xtal;
88 unsigned long hclk, fclk, pclk;
89 int hdiv = 1;
90
91 xtal_clk = clk_get(NULL, "xtal");
92 xtal = clk_get_rate(xtal_clk);
93 clk_put(xtal_clk);
94
95 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
96
97 clkdiv = __raw_readl(S3C2410_CLKDIVN);
98 camdiv = __raw_readl(S3C2440_CAMDIVN);
99
100 /* work out clock scalings */
101
102 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
103 case S3C2440_CLKDIVN_HDIVN_1:
104 hdiv = 1;
105 break;
106
107 case S3C2440_CLKDIVN_HDIVN_2:
108 hdiv = 2;
109 break;
110
111 case S3C2440_CLKDIVN_HDIVN_4_8:
112 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
113 break;
114
115 case S3C2440_CLKDIVN_HDIVN_3_6:
116 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
117 break;
118 }
119
120 hclk = fclk / hdiv;
121 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
122
123 /* print brief summary of clocks, etc */
124
125 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
126 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
127
128 s3c24xx_setup_clocks(fclk, hclk, pclk);
129}
130
131void __init s3c244x_init_clocks(int xtal)
132{
133 /* initialise the clocks here, to allow other things like the
134 * console to use them, and to add new ones after the initialisation
135 */
136
137 s3c24xx_register_baseclocks(xtal);
138 s3c244x_setup_clocks();
139 s3c2410_baseclk_add();
140 samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
141} 83}
142#else
143void __init_or_cpufreq s3c244x_setup_clocks(void)
144{
145}
146#endif
147 84
148/* Since the S3C2442 and S3C2440 share items, put both subsystems here */ 85/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
149 86