diff options
author | Heiko Stuebner <heiko@sntech.de> | 2013-02-12 13:09:21 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-03-05 06:21:16 -0500 |
commit | 4245944c71f90c0b38659e4a4f0d7741c79ef2b0 (patch) | |
tree | bc71a083d16ad6105587d931e3c4ff716c47a516 /arch/arm/mach-s3c24xx/irq.c | |
parent | 0da09930d515da5848eba343e965ebbc853c8a44 (diff) |
ARM: S3C24XX: transform s3c2412 irqs into new structure
Contains only the new mapping structure. The special handling
of the eint0 to eint3 interrupts still needs to be solved.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/irq.c')
-rw-r--r-- | arch/arm/mach-s3c24xx/irq.c | 122 |
1 files changed, 66 insertions, 56 deletions
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c index 55a73c4d2c95..292f974c5294 100644 --- a/arch/arm/mach-s3c24xx/irq.c +++ b/arch/arm/mach-s3c24xx/irq.c | |||
@@ -627,9 +627,58 @@ void __init s3c24xx_init_irq(void) | |||
627 | } | 627 | } |
628 | 628 | ||
629 | #ifdef CONFIG_CPU_S3C2412 | 629 | #ifdef CONFIG_CPU_S3C2412 |
630 | static struct s3c_irq_data init_s3c2412base[32] = { | ||
631 | { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ | ||
632 | { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ | ||
633 | { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ | ||
634 | { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ | ||
635 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ | ||
636 | { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ | ||
637 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
638 | { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ | ||
639 | { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ | ||
640 | { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ | ||
641 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ | ||
642 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ | ||
643 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ | ||
644 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ | ||
645 | { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ | ||
646 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ | ||
647 | { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ | ||
648 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ | ||
649 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ | ||
650 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ | ||
651 | { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ | ||
652 | { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ | ||
653 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ | ||
654 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ | ||
655 | { .type = S3C_IRQTYPE_NONE, }, /* reserved */ | ||
656 | { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ | ||
657 | { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ | ||
658 | { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ | ||
659 | { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ | ||
660 | { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ | ||
661 | { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ | ||
662 | { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ | ||
663 | }; | ||
630 | 664 | ||
631 | #define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) | 665 | static struct s3c_irq_data init_s3c2412subint[32] = { |
632 | #define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) | 666 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ |
667 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ | ||
668 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ | ||
669 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ | ||
670 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ | ||
671 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ | ||
672 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ | ||
673 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ | ||
674 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ | ||
675 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ | ||
676 | { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ | ||
677 | { .type = S3C_IRQTYPE_NONE, }, | ||
678 | { .type = S3C_IRQTYPE_NONE, }, | ||
679 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ | ||
680 | { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ | ||
681 | }; | ||
633 | 682 | ||
634 | /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by | 683 | /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by |
635 | * having them turn up in both the INT* and the EINT* registers. Whilst | 684 | * having them turn up in both the INT* and the EINT* registers. Whilst |
@@ -698,72 +747,33 @@ static struct irq_chip s3c2412_irq_eint0t4 = { | |||
698 | .irq_set_type = s3c_irqext_type, | 747 | .irq_set_type = s3c_irqext_type, |
699 | }; | 748 | }; |
700 | 749 | ||
701 | #define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) | 750 | void s3c2412_init_irq(void) |
702 | |||
703 | /* CF and SDI sub interrupts */ | ||
704 | |||
705 | static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc) | ||
706 | { | ||
707 | unsigned int subsrc, submsk; | ||
708 | |||
709 | subsrc = __raw_readl(S3C2410_SUBSRCPND); | ||
710 | submsk = __raw_readl(S3C2410_INTSUBMSK); | ||
711 | |||
712 | subsrc &= ~submsk; | ||
713 | |||
714 | if (subsrc & INTBIT(IRQ_S3C2412_SDI)) | ||
715 | generic_handle_irq(IRQ_S3C2412_SDI); | ||
716 | |||
717 | if (subsrc & INTBIT(IRQ_S3C2412_CF)) | ||
718 | generic_handle_irq(IRQ_S3C2412_CF); | ||
719 | } | ||
720 | |||
721 | #define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) | ||
722 | #define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) | ||
723 | |||
724 | static void s3c2412_irq_cfsdi_mask(struct irq_data *data) | ||
725 | { | 751 | { |
726 | s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); | 752 | struct s3c_irq_intc *main_intc; |
727 | } | 753 | unsigned int irqno; |
728 | 754 | ||
729 | static void s3c2412_irq_cfsdi_unmask(struct irq_data *data) | 755 | pr_info("S3C2412: IRQ Support\n"); |
730 | { | ||
731 | s3c_irqsub_unmask(data->irq, INTMSK_CFSDI); | ||
732 | } | ||
733 | 756 | ||
734 | static void s3c2412_irq_cfsdi_ack(struct irq_data *data) | 757 | #ifdef CONFIG_FIQ |
735 | { | 758 | init_FIQ(FIQ_START); |
736 | s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI); | 759 | #endif |
737 | } | ||
738 | 760 | ||
739 | static struct irq_chip s3c2412_irq_cfsdi = { | 761 | main_intc = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, 0x4a000000); |
740 | .name = "s3c2412-cfsdi", | 762 | if (IS_ERR(main_intc)) { |
741 | .irq_ack = s3c2412_irq_cfsdi_ack, | 763 | pr_err("irq: could not create main interrupt controller\n"); |
742 | .irq_mask = s3c2412_irq_cfsdi_mask, | 764 | return; |
743 | .irq_unmask = s3c2412_irq_cfsdi_unmask, | 765 | } |
744 | }; | ||
745 | 766 | ||
746 | void s3c2412_init_irq(void) | 767 | s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); |
747 | { | 768 | s3c24xx_init_intc(NULL, &init_s3c2412subint[0], main_intc, 0x4a000018); |
748 | unsigned int irqno; | ||
749 | 769 | ||
750 | s3c24xx_init_irq(); | 770 | /* special handling for eints 0 to 3 */ |
751 | 771 | ||
752 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 772 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
753 | irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, | 773 | irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, |
754 | handle_edge_irq); | 774 | handle_edge_irq); |
755 | set_irq_flags(irqno, IRQF_VALID); | 775 | set_irq_flags(irqno, IRQF_VALID); |
756 | } | 776 | } |
757 | |||
758 | /* add demux support for CF/SDI */ | ||
759 | |||
760 | irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); | ||
761 | |||
762 | for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { | ||
763 | irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, | ||
764 | handle_level_irq); | ||
765 | set_irq_flags(irqno, IRQF_VALID); | ||
766 | } | ||
767 | } | 777 | } |
768 | #endif | 778 | #endif |
769 | 779 | ||