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authorOlof Johansson <olof@lixom.net>2013-02-05 20:01:56 -0500
committerOlof Johansson <olof@lixom.net>2013-02-05 20:01:56 -0500
commitcf55f672c325f234d96911571a775b2e7d9cf284 (patch)
tree9242f9ddb0f556dca7884c60ad81aefbe35ae258 /arch/arm/mach-s3c24xx/include
parent5060c8881a4b177e27d5bcf351212f2bee125955 (diff)
parent37c3adca81b282bdf310d5ed54acbc28ac0b20a3 (diff)
Merge branch 'next/cleanup-s3c24xx-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
From Kukjin Kim: This is 4th cleanup for Samsung S3C24XX stuff, and removes plat-s3c24xx directory. * 'next/cleanup-s3c24xx-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C24XX: header mach/regs-mem.h local ARM: S3C24XX: header mach/regs-power.h local ARM: S3C24XX: header mach/regs-s3c2412-mem.h local ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/
Diffstat (limited to 'arch/arm/mach-s3c24xx/include')
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-mem.h202
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-power.h40
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h48
3 files changed, 0 insertions, 290 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Memory Control register definitions
11*/
12
13#ifndef __ASM_ARM_MEMREGS_H
14#define __ASM_ARM_MEMREGS_H
15
16#ifndef S3C2410_MEMREG
17#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#endif
19
20/* bus width, and wait state control */
21#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
22
23/* bank zero config - note, pinstrapped from OM pins! */
24#define S3C2410_BWSCON_DW0_16 (1<<1)
25#define S3C2410_BWSCON_DW0_32 (2<<1)
26
27/* bank one configs */
28#define S3C2410_BWSCON_DW1_8 (0<<4)
29#define S3C2410_BWSCON_DW1_16 (1<<4)
30#define S3C2410_BWSCON_DW1_32 (2<<4)
31#define S3C2410_BWSCON_WS1 (1<<6)
32#define S3C2410_BWSCON_ST1 (1<<7)
33
34/* bank 2 configurations */
35#define S3C2410_BWSCON_DW2_8 (0<<8)
36#define S3C2410_BWSCON_DW2_16 (1<<8)
37#define S3C2410_BWSCON_DW2_32 (2<<8)
38#define S3C2410_BWSCON_WS2 (1<<10)
39#define S3C2410_BWSCON_ST2 (1<<11)
40
41/* bank 3 configurations */
42#define S3C2410_BWSCON_DW3_8 (0<<12)
43#define S3C2410_BWSCON_DW3_16 (1<<12)
44#define S3C2410_BWSCON_DW3_32 (2<<12)
45#define S3C2410_BWSCON_WS3 (1<<14)
46#define S3C2410_BWSCON_ST3 (1<<15)
47
48/* bank 4 configurations */
49#define S3C2410_BWSCON_DW4_8 (0<<16)
50#define S3C2410_BWSCON_DW4_16 (1<<16)
51#define S3C2410_BWSCON_DW4_32 (2<<16)
52#define S3C2410_BWSCON_WS4 (1<<18)
53#define S3C2410_BWSCON_ST4 (1<<19)
54
55/* bank 5 configurations */
56#define S3C2410_BWSCON_DW5_8 (0<<20)
57#define S3C2410_BWSCON_DW5_16 (1<<20)
58#define S3C2410_BWSCON_DW5_32 (2<<20)
59#define S3C2410_BWSCON_WS5 (1<<22)
60#define S3C2410_BWSCON_ST5 (1<<23)
61
62/* bank 6 configurations */
63#define S3C2410_BWSCON_DW6_8 (0<<24)
64#define S3C2410_BWSCON_DW6_16 (1<<24)
65#define S3C2410_BWSCON_DW6_32 (2<<24)
66#define S3C2410_BWSCON_WS6 (1<<26)
67#define S3C2410_BWSCON_ST6 (1<<27)
68
69/* bank 7 configurations */
70#define S3C2410_BWSCON_DW7_8 (0<<28)
71#define S3C2410_BWSCON_DW7_16 (1<<28)
72#define S3C2410_BWSCON_DW7_32 (2<<28)
73#define S3C2410_BWSCON_WS7 (1<<30)
74#define S3C2410_BWSCON_ST7 (1<<31)
75
76/* accesor functions for getting BANK(n) configuration. (n != 0) */
77
78#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79
80#define S3C2410_BWSCON_DW8 (0)
81#define S3C2410_BWSCON_DW16 (1)
82#define S3C2410_BWSCON_DW32 (2)
83#define S3C2410_BWSCON_WS (1 << 2)
84#define S3C2410_BWSCON_ST (1 << 3)
85
86/* memory set (rom, ram) */
87#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
88#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
89#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
90#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
91#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
92#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
93#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
94#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
95
96/* bank configuration registers */
97
98#define S3C2410_BANKCON_PMCnorm (0x00)
99#define S3C2410_BANKCON_PMC4 (0x01)
100#define S3C2410_BANKCON_PMC8 (0x02)
101#define S3C2410_BANKCON_PMC16 (0x03)
102
103/* bank configurations for banks 0..7, note banks
104 * 6 and 7 have different configurations depending on
105 * the memory type bits */
106
107#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
108#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
109#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
110#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
111#define S3C2410_BANKCON_Tacp_SHIFT (2)
112
113#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
114#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
115#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
116#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
117#define S3C2410_BANKCON_Tcah_SHIFT (4)
118
119#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
120#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
121#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
122#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
123#define S3C2410_BANKCON_Tcoh_SHIFT (6)
124
125#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
126#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
127#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
128#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
129#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
130#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
131#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
132#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
133#define S3C2410_BANKCON_Tacc_SHIFT (8)
134
135#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
136#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
137#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
138#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
139#define S3C2410_BANKCON_Tcos_SHIFT (11)
140
141#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
142#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
143#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
144#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
145#define S3C2410_BANKCON_Tacs_SHIFT (13)
146
147#define S3C2410_BANKCON_SRAM (0x0 << 15)
148#define S3C2410_BANKCON_SDRAM (0x3 << 15)
149
150/* next bits only for SDRAM in 6,7 */
151#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
152#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
153#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
154
155/* control column address select */
156#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
157#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
158#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
159
160#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
161#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
162#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
163#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
164
165/* refresh control */
166
167#define S3C2410_REFRESH_REFEN (1<<23)
168#define S3C2410_REFRESH_SELF (1<<22)
169#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
170
171#define S3C2410_REFRESH_TRP_MASK (3<<20)
172#define S3C2410_REFRESH_TRP_2clk (0<<20)
173#define S3C2410_REFRESH_TRP_3clk (1<<20)
174#define S3C2410_REFRESH_TRP_4clk (2<<20)
175
176#define S3C2410_REFRESH_TSRC_MASK (3<<18)
177#define S3C2410_REFRESH_TSRC_4clk (0<<18)
178#define S3C2410_REFRESH_TSRC_5clk (1<<18)
179#define S3C2410_REFRESH_TSRC_6clk (2<<18)
180#define S3C2410_REFRESH_TSRC_7clk (3<<18)
181
182
183/* mode select register(s) */
184
185#define S3C2410_MRSRB_CL1 (0x00 << 4)
186#define S3C2410_MRSRB_CL2 (0x02 << 4)
187#define S3C2410_MRSRB_CL3 (0x03 << 4)
188
189/* bank size register */
190#define S3C2410_BANKSIZE_128M (0x2 << 0)
191#define S3C2410_BANKSIZE_64M (0x1 << 0)
192#define S3C2410_BANKSIZE_32M (0x0 << 0)
193#define S3C2410_BANKSIZE_16M (0x7 << 0)
194#define S3C2410_BANKSIZE_8M (0x6 << 0)
195#define S3C2410_BANKSIZE_4M (0x5 << 0)
196#define S3C2410_BANKSIZE_2M (0x4 << 0)
197#define S3C2410_BANKSIZE_MASK (0x7 << 0)
198#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
199#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
200#define S3C2410_BANKSIZE_BURST (1<<7)
201
202#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
deleted file mode 100644
index 4932b87bdf3d..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-power.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24XX power control register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
19#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
20
21#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
22#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
25
26#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
27#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
28#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
29#define S3C2412_PWRCFG_BATF_MASK (3<<0)
30
31#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6)
32#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6)
33#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6)
34#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6)
35#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6)
36
37#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8)
38#define S3C2412_PWRCFG_NAND_NORST (1<<9)
39
40#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
deleted file mode 100644
index fb6352515090..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2412 memory register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2412_MEM
15#define __ASM_ARM_REGS_S3C2412_MEM
16
17#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
19
20#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
21#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
22
23#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
24#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
25#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08)
26#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C)
27
28#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
29#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
30
31/* EBI control registers */
32
33#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
34#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
35
36/* SSMC control registers */
37
38#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
39#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
40#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
41#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
42#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
43#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
44#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
45#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
46#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
47
48#endif /* __ASM_ARM_REGS_S3C2412_MEM */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 01:47:26 -0500