diff options
author | Lennert Buytenhek <buytenh@secretlab.ca> | 2011-01-03 05:15:54 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-01-03 05:15:54 -0500 |
commit | 57436c2db4426c5dcbaaba0acd5204f5fa71b762 (patch) | |
tree | 353d62b67ef3cbabd405266fd17e7c847943b0ec /arch/arm/mach-s3c2443 | |
parent | d930596a3c093bf3f4fbf24f10ad0d8372d6ac21 (diff) |
ARM: S3C24XX: irq_data conversion
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
[kgene.kim@samsung.com: coding-style fixes]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c2443')
-rw-r--r-- | arch/arm/mach-s3c2443/irq.c | 95 |
1 files changed, 45 insertions, 50 deletions
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index 893424767ce1..c7820f9c1352 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c | |||
@@ -75,28 +75,27 @@ static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc) | |||
75 | #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) | 75 | #define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) |
76 | #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) | 76 | #define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) |
77 | 77 | ||
78 | static void s3c2443_irq_wdtac97_mask(unsigned int irqno) | 78 | static void s3c2443_irq_wdtac97_mask(struct irq_data *data) |
79 | { | 79 | { |
80 | s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); | 80 | s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); |
81 | } | 81 | } |
82 | 82 | ||
83 | static void s3c2443_irq_wdtac97_unmask(unsigned int irqno) | 83 | static void s3c2443_irq_wdtac97_unmask(struct irq_data *data) |
84 | { | 84 | { |
85 | s3c_irqsub_unmask(irqno, INTMSK_WDTAC97); | 85 | s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97); |
86 | } | 86 | } |
87 | 87 | ||
88 | static void s3c2443_irq_wdtac97_ack(unsigned int irqno) | 88 | static void s3c2443_irq_wdtac97_ack(struct irq_data *data) |
89 | { | 89 | { |
90 | s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); | 90 | s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97); |
91 | } | 91 | } |
92 | 92 | ||
93 | static struct irq_chip s3c2443_irq_wdtac97 = { | 93 | static struct irq_chip s3c2443_irq_wdtac97 = { |
94 | .mask = s3c2443_irq_wdtac97_mask, | 94 | .irq_mask = s3c2443_irq_wdtac97_mask, |
95 | .unmask = s3c2443_irq_wdtac97_unmask, | 95 | .irq_unmask = s3c2443_irq_wdtac97_unmask, |
96 | .ack = s3c2443_irq_wdtac97_ack, | 96 | .irq_ack = s3c2443_irq_wdtac97_ack, |
97 | }; | 97 | }; |
98 | 98 | ||
99 | |||
100 | /* LCD sub interrupts */ | 99 | /* LCD sub interrupts */ |
101 | 100 | ||
102 | static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) | 101 | static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) |
@@ -107,28 +106,27 @@ static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) | |||
107 | #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) | 106 | #define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) |
108 | #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) | 107 | #define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) |
109 | 108 | ||
110 | static void s3c2443_irq_lcd_mask(unsigned int irqno) | 109 | static void s3c2443_irq_lcd_mask(struct irq_data *data) |
111 | { | 110 | { |
112 | s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD); | 111 | s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD); |
113 | } | 112 | } |
114 | 113 | ||
115 | static void s3c2443_irq_lcd_unmask(unsigned int irqno) | 114 | static void s3c2443_irq_lcd_unmask(struct irq_data *data) |
116 | { | 115 | { |
117 | s3c_irqsub_unmask(irqno, INTMSK_LCD); | 116 | s3c_irqsub_unmask(data->irq, INTMSK_LCD); |
118 | } | 117 | } |
119 | 118 | ||
120 | static void s3c2443_irq_lcd_ack(unsigned int irqno) | 119 | static void s3c2443_irq_lcd_ack(struct irq_data *data) |
121 | { | 120 | { |
122 | s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD); | 121 | s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD); |
123 | } | 122 | } |
124 | 123 | ||
125 | static struct irq_chip s3c2443_irq_lcd = { | 124 | static struct irq_chip s3c2443_irq_lcd = { |
126 | .mask = s3c2443_irq_lcd_mask, | 125 | .irq_mask = s3c2443_irq_lcd_mask, |
127 | .unmask = s3c2443_irq_lcd_unmask, | 126 | .irq_unmask = s3c2443_irq_lcd_unmask, |
128 | .ack = s3c2443_irq_lcd_ack, | 127 | .irq_ack = s3c2443_irq_lcd_ack, |
129 | }; | 128 | }; |
130 | 129 | ||
131 | |||
132 | /* DMA sub interrupts */ | 130 | /* DMA sub interrupts */ |
133 | 131 | ||
134 | static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) | 132 | static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) |
@@ -139,29 +137,27 @@ static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) | |||
139 | #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) | 137 | #define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) |
140 | #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) | 138 | #define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) |
141 | 139 | ||
142 | 140 | static void s3c2443_irq_dma_mask(struct irq_data *data) | |
143 | static void s3c2443_irq_dma_mask(unsigned int irqno) | ||
144 | { | 141 | { |
145 | s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA); | 142 | s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA); |
146 | } | 143 | } |
147 | 144 | ||
148 | static void s3c2443_irq_dma_unmask(unsigned int irqno) | 145 | static void s3c2443_irq_dma_unmask(struct irq_data *data) |
149 | { | 146 | { |
150 | s3c_irqsub_unmask(irqno, INTMSK_DMA); | 147 | s3c_irqsub_unmask(data->irq, INTMSK_DMA); |
151 | } | 148 | } |
152 | 149 | ||
153 | static void s3c2443_irq_dma_ack(unsigned int irqno) | 150 | static void s3c2443_irq_dma_ack(struct irq_data *data) |
154 | { | 151 | { |
155 | s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA); | 152 | s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA); |
156 | } | 153 | } |
157 | 154 | ||
158 | static struct irq_chip s3c2443_irq_dma = { | 155 | static struct irq_chip s3c2443_irq_dma = { |
159 | .mask = s3c2443_irq_dma_mask, | 156 | .irq_mask = s3c2443_irq_dma_mask, |
160 | .unmask = s3c2443_irq_dma_unmask, | 157 | .irq_unmask = s3c2443_irq_dma_unmask, |
161 | .ack = s3c2443_irq_dma_ack, | 158 | .irq_ack = s3c2443_irq_dma_ack, |
162 | }; | 159 | }; |
163 | 160 | ||
164 | |||
165 | /* UART3 sub interrupts */ | 161 | /* UART3 sub interrupts */ |
166 | 162 | ||
167 | static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) | 163 | static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) |
@@ -172,28 +168,27 @@ static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) | |||
172 | #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) | 168 | #define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) |
173 | #define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) | 169 | #define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) |
174 | 170 | ||
175 | static void s3c2443_irq_uart3_mask(unsigned int irqno) | 171 | static void s3c2443_irq_uart3_mask(struct irq_data *data) |
176 | { | 172 | { |
177 | s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3); | 173 | s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3); |
178 | } | 174 | } |
179 | 175 | ||
180 | static void s3c2443_irq_uart3_unmask(unsigned int irqno) | 176 | static void s3c2443_irq_uart3_unmask(struct irq_data *data) |
181 | { | 177 | { |
182 | s3c_irqsub_unmask(irqno, INTMSK_UART3); | 178 | s3c_irqsub_unmask(data->irq, INTMSK_UART3); |
183 | } | 179 | } |
184 | 180 | ||
185 | static void s3c2443_irq_uart3_ack(unsigned int irqno) | 181 | static void s3c2443_irq_uart3_ack(struct irq_data *data) |
186 | { | 182 | { |
187 | s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3); | 183 | s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3); |
188 | } | 184 | } |
189 | 185 | ||
190 | static struct irq_chip s3c2443_irq_uart3 = { | 186 | static struct irq_chip s3c2443_irq_uart3 = { |
191 | .mask = s3c2443_irq_uart3_mask, | 187 | .irq_mask = s3c2443_irq_uart3_mask, |
192 | .unmask = s3c2443_irq_uart3_unmask, | 188 | .irq_unmask = s3c2443_irq_uart3_unmask, |
193 | .ack = s3c2443_irq_uart3_ack, | 189 | .irq_ack = s3c2443_irq_uart3_ack, |
194 | }; | 190 | }; |
195 | 191 | ||
196 | |||
197 | /* CAM sub interrupts */ | 192 | /* CAM sub interrupts */ |
198 | 193 | ||
199 | static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) | 194 | static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) |
@@ -204,25 +199,25 @@ static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) | |||
204 | #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) | 199 | #define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) |
205 | #define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P) | 200 | #define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P) |
206 | 201 | ||
207 | static void s3c2443_irq_cam_mask(unsigned int irqno) | 202 | static void s3c2443_irq_cam_mask(struct irq_data *data) |
208 | { | 203 | { |
209 | s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM); | 204 | s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM); |
210 | } | 205 | } |
211 | 206 | ||
212 | static void s3c2443_irq_cam_unmask(unsigned int irqno) | 207 | static void s3c2443_irq_cam_unmask(struct irq_data *data) |
213 | { | 208 | { |
214 | s3c_irqsub_unmask(irqno, INTMSK_CAM); | 209 | s3c_irqsub_unmask(data->irq, INTMSK_CAM); |
215 | } | 210 | } |
216 | 211 | ||
217 | static void s3c2443_irq_cam_ack(unsigned int irqno) | 212 | static void s3c2443_irq_cam_ack(struct irq_data *data) |
218 | { | 213 | { |
219 | s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM); | 214 | s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM); |
220 | } | 215 | } |
221 | 216 | ||
222 | static struct irq_chip s3c2443_irq_cam = { | 217 | static struct irq_chip s3c2443_irq_cam = { |
223 | .mask = s3c2443_irq_cam_mask, | 218 | .irq_mask = s3c2443_irq_cam_mask, |
224 | .unmask = s3c2443_irq_cam_unmask, | 219 | .irq_unmask = s3c2443_irq_cam_unmask, |
225 | .ack = s3c2443_irq_cam_ack, | 220 | .irq_ack = s3c2443_irq_cam_ack, |
226 | }; | 221 | }; |
227 | 222 | ||
228 | /* IRQ initialisation code */ | 223 | /* IRQ initialisation code */ |