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authorBen Dooks <ben-linux@fluff.org>2010-04-29 05:59:43 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-09 22:44:44 -0400
commitc140c98ac161ad270a768126431e36a22f86f6b3 (patch)
tree0ce2aa19fb1f088d155564b55a444275dce0f4de /arch/arm/mach-s3c2410
parent8d6f8658305db969981f64a22296b487ef2f1148 (diff)
ARM: S3C2416: Add support for second HSMMC channel
Add support for the second HSMMC channel on the S3C2416. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h5
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index c1b8ec07bf45..877c15e1b154 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -150,7 +150,10 @@
150#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ 150#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
151#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 151#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
152 152
153#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
154
153#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC 155#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
156#define IRQ_HSMMC1 IRQ_S3C2416_HSMMC0
154 157
155#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 158#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
156#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) 159#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index b049e61460b6..f07d68066d7e 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -63,9 +63,9 @@
63#define S3C2440_PA_AC97 (0x5B000000) 63#define S3C2440_PA_AC97 (0x5B000000)
64#define S3C2440_SZ_AC97 SZ_1M 64#define S3C2440_SZ_AC97 SZ_1M
65 65
66/* S3C2443 High-speed SD/MMC */ 66/* S3C2443/S3C2416 High-speed SD/MMC */
67#define S3C2443_PA_HSMMC (0x4A800000) 67#define S3C2443_PA_HSMMC (0x4A800000)
68#define S3C2443_SZ_HSMMC (256) 68#define S3C2416_PA_HSMMC0 (0x4AC00000)
69 69
70/* S3C2412 memory and IO controls */ 70/* S3C2412 memory and IO controls */
71#define S3C2412_PA_SSMC (0x4F000000) 71#define S3C2412_PA_SSMC (0x4F000000)
@@ -110,6 +110,7 @@
110#define S3C_PA_UART S3C24XX_PA_UART 110#define S3C_PA_UART S3C24XX_PA_UART
111#define S3C_PA_USBHOST S3C2410_PA_USBHOST 111#define S3C_PA_USBHOST S3C2410_PA_USBHOST
112#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC 112#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
113#define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0
113#define S3C_PA_NAND S3C24XX_PA_NAND 114#define S3C_PA_NAND S3C24XX_PA_NAND
114 115
115#endif /* __ASM_ARCH_MAP_H */ 116#endif /* __ASM_ARCH_MAP_H */