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authorBen Dooks <ben-linux@fluff.org>2006-03-20 12:10:04 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-21 17:06:02 -0500
commit8e40a2f91c6e73726a75381e4438478eb5964cb7 (patch)
treeb0b66666c84151a2c382e189e2fbcc619d1edfb0 /arch/arm/mach-s3c2410
parent766636cc3630ae3b9827e7b4b1f566572963f1ef (diff)
[ARM] 3330/1: S3C24XX - move UPLL to main clock
Patch from Ben Dooks Move the UPLL clock registration to the central clock file, and add an enable method Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/clock.c38
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-clock.c19
2 files changed, 38 insertions, 19 deletions
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 08489efdaf06..aaada9e3d67f 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -38,6 +38,7 @@
38#include <linux/ioport.h> 38#include <linux/ioport.h>
39#include <linux/clk.h> 39#include <linux/clk.h>
40#include <linux/mutex.h> 40#include <linux/mutex.h>
41#include <linux/delay.h>
41 42
42#include <asm/hardware.h> 43#include <asm/hardware.h>
43#include <asm/irq.h> 44#include <asm/irq.h>
@@ -200,6 +201,28 @@ EXPORT_SYMBOL(clk_round_rate);
200EXPORT_SYMBOL(clk_set_rate); 201EXPORT_SYMBOL(clk_set_rate);
201EXPORT_SYMBOL(clk_get_parent); 202EXPORT_SYMBOL(clk_get_parent);
202 203
204/* base clock enable */
205
206static int s3c24xx_upll_enable(struct clk *clk, int enable)
207{
208 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
209 unsigned long orig = clkslow;
210
211 if (enable)
212 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
213 else
214 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
215
216 __raw_writel(clkslow, S3C2410_CLKSLOW);
217
218 /* if we started the UPLL, then allow to settle */
219
220 if (enable && !(orig & S3C2410_CLKSLOW_UCLK_OFF))
221 udelay(200);
222
223 return 0;
224}
225
203/* base clocks */ 226/* base clocks */
204 227
205static struct clk clk_xtal = { 228static struct clk clk_xtal = {
@@ -210,6 +233,14 @@ static struct clk clk_xtal = {
210 .ctrlbit = 0, 233 .ctrlbit = 0,
211}; 234};
212 235
236static struct clk clk_upll = {
237 .name = "upll",
238 .id = -1,
239 .parent = NULL,
240 .enable = s3c24xx_upll_enable,
241 .ctrlbit = 0,
242};
243
213static struct clk clk_f = { 244static struct clk clk_f = {
214 .name = "fclk", 245 .name = "fclk",
215 .id = -1, 246 .id = -1,
@@ -262,7 +293,7 @@ struct clk s3c24xx_uclk = {
262}; 293};
263 294
264 295
265/* clock definitions */ 296/* standard clock definitions */
266 297
267static struct clk init_clocks[] = { 298static struct clk init_clocks[] = {
268 { 299 {
@@ -396,6 +427,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
396 unsigned long hclk, 427 unsigned long hclk,
397 unsigned long pclk) 428 unsigned long pclk)
398{ 429{
430 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
399 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); 431 unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
400 struct clk *clkp = init_clocks; 432 struct clk *clkp = init_clocks;
401 int ptr; 433 int ptr;
@@ -406,6 +438,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
406 /* initialise the main system clocks */ 438 /* initialise the main system clocks */
407 439
408 clk_xtal.rate = xtal; 440 clk_xtal.rate = xtal;
441 clk_upll.rate = s3c2410_get_pll(upllcon, xtal);
409 442
410 clk_h.rate = hclk; 443 clk_h.rate = hclk;
411 clk_p.rate = pclk; 444 clk_p.rate = pclk;
@@ -439,6 +472,9 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
439 if (s3c24xx_register_clock(&clk_xtal) < 0) 472 if (s3c24xx_register_clock(&clk_xtal) < 0)
440 printk(KERN_ERR "failed to register master xtal\n"); 473 printk(KERN_ERR "failed to register master xtal\n");
441 474
475 if (s3c24xx_register_clock(&clk_upll) < 0)
476 printk(KERN_ERR "failed to register upll clock\n");
477
442 if (s3c24xx_register_clock(&clk_f) < 0) 478 if (s3c24xx_register_clock(&clk_f) < 0)
443 printk(KERN_ERR "failed to register cpu fclk\n"); 479 printk(KERN_ERR "failed to register cpu fclk\n");
444 480
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c
index b557a2be8a01..2d0fa03a257a 100644
--- a/arch/arm/mach-s3c2410/s3c2440-clock.c
+++ b/arch/arm/mach-s3c2410/s3c2440-clock.c
@@ -45,11 +45,6 @@
45 45
46/* S3C2440 extended clock support */ 46/* S3C2440 extended clock support */
47 47
48static struct clk s3c2440_clk_upll = {
49 .name = "upll",
50 .id = -1,
51};
52
53static struct clk s3c2440_clk_cam = { 48static struct clk s3c2440_clk_cam = {
54 .name = "camif", 49 .name = "camif",
55 .id = -1, 50 .id = -1,
@@ -66,22 +61,11 @@ static struct clk s3c2440_clk_ac97 = {
66 61
67static int s3c2440_clk_add(struct sys_device *sysdev) 62static int s3c2440_clk_add(struct sys_device *sysdev)
68{ 63{
69 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
70 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); 64 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
71 struct clk *clk_h; 65 struct clk *clk_h;
72 struct clk *clk_p; 66 struct clk *clk_p;
73 struct clk *clk_xtal;
74
75 clk_xtal = clk_get(NULL, "xtal");
76 if (IS_ERR(clk_xtal)) {
77 printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
78 return -EINVAL;
79 }
80
81 s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
82 67
83 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n", 68 printk("S3C2440: Clock Support, DVS %s\n",
84 print_mhz(s3c2440_clk_upll.rate),
85 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); 69 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
86 70
87 clk_p = clk_get(NULL, "pclk"); 71 clk_p = clk_get(NULL, "pclk");
@@ -97,7 +81,6 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
97 81
98 s3c24xx_register_clock(&s3c2440_clk_ac97); 82 s3c24xx_register_clock(&s3c2440_clk_ac97);
99 s3c24xx_register_clock(&s3c2440_clk_cam); 83 s3c24xx_register_clock(&s3c2440_clk_cam);
100 s3c24xx_register_clock(&s3c2440_clk_upll);
101 84
102 clk_disable(&s3c2440_clk_ac97); 85 clk_disable(&s3c2440_clk_ac97);
103 clk_disable(&s3c2440_clk_cam); 86 clk_disable(&s3c2440_clk_cam);