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authorKukjin Kim <kgene.kim@samsung.com>2012-02-05 19:38:19 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-02 17:47:38 -0500
commit85fd6d63bf2927b9da7ab1b0d46723bfdb13808c (patch)
tree7033ac06e365209b09ba4b97eba0cf2f7ceb3312 /arch/arm/mach-s3c2410
parentb130d5c29544fe4cedafd35b112d27a06550d844 (diff)
ARM: S3C2410: move mach-s3c2410/* into mach-s3c24xx/
This patch moves S3C2410 stuff into mach-s3c24xx/ directory so that we can merge the s3c24 series' directories to the just one mach-s3c24xx/ directory. And this patch is including following. - re-ordered alphabetically by option text at Kconfig and Makefile - removed unused option, MACH_N35 - fixed duplcated option name, S3C2410_DMA to S3C24XX_DMA which is in plat-s3c24xx/ Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/Kconfig154
-rw-r--r--arch/arm/mach-s3c2410/Makefile26
-rw-r--r--arch/arm/mach-s3c2410/Makefile.boot7
-rw-r--r--arch/arm/mach-s3c2410/bast-ide.c112
-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c166
-rw-r--r--arch/arm/mach-s3c2410/common.h17
-rw-r--r--arch/arm/mach-s3c2410/dma.c185
-rw-r--r--arch/arm/mach-s3c2410/h1940-bluetooth.c157
-rw-r--r--arch/arm/mach-s3c2410/include/mach/anubis-cpld.h25
-rw-r--r--arch/arm/mach-s3c2410/include/mach/anubis-irq.h21
-rw-r--r--arch/arm/mach-s3c2410/include/mach/anubis-map.h38
-rw-r--r--arch/arm/mach-s3c2410/include/mach/bast-cpld.h53
-rw-r--r--arch/arm/mach-s3c2410/include/mach/bast-irq.h29
-rw-r--r--arch/arm/mach-s3c2410/include/mach/bast-map.h146
-rw-r--r--arch/arm/mach-s3c2410/include/mach/bast-pmu.h40
-rw-r--r--arch/arm/mach-s3c2410/include/mach/debug-macro.S101
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h210
-rw-r--r--arch/arm/mach-s3c2410/include/mach/entry-macro.S78
-rw-r--r--arch/arm/mach-s3c2410/include/mach/fb.h1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-fns.h1
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h118
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-track.h33
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio.h35
-rw-r--r--arch/arm/mach-s3c2410/include/mach/h1940-latch.h43
-rw-r--r--arch/arm/mach-s3c2410/include/mach/h1940.h24
-rw-r--r--arch/arm/mach-s3c2410/include/mach/hardware.h42
-rw-r--r--arch/arm/mach-s3c2410/include/mach/idle.h24
-rw-r--r--arch/arm/mach-s3c2410/include/mach/io.h216
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h202
-rw-r--r--arch/arm/mach-s3c2410/include/mach/leds-gpio.h28
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h165
-rw-r--r--arch/arm/mach-s3c2410/include/mach/osiris-cpld.h30
-rw-r--r--arch/arm/mach-s3c2410/include/mach/osiris-map.h42
-rw-r--r--arch/arm/mach-s3c2410/include/mach/otom-map.h30
-rw-r--r--arch/arm/mach-s3c2410/include/mach/pm-core.h67
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-clock.h166
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-dsc.h220
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h602
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpioj.h70
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-irq.h53
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-lcd.h162
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-mem.h202
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-power.h40
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h48
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h23
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h30
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h24
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h194
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-sdi.h127
-rw-r--r--arch/arm/mach-s3c2410/include/mach/system.h54
-rw-r--r--arch/arm/mach-s3c2410/include/mach/tick.h15
-rw-r--r--arch/arm/mach-s3c2410/include/mach/timex.h24
-rw-r--r--arch/arm/mach-s3c2410/include/mach/uncompress.h54
-rw-r--r--arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h18
-rw-r--r--arch/arm/mach-s3c2410/include/mach/vr1000-irq.h26
-rw-r--r--arch/arm/mach-s3c2410/include/mach/vr1000-map.h110
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c247
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c645
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c757
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c608
-rw-r--r--arch/arm/mach-s3c2410/mach-otom.c127
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c356
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2410.c122
-rw-r--r--arch/arm/mach-s3c2410/mach-tct_hammer.c157
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c386
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.c87
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.h14
-rw-r--r--arch/arm/mach-s3c2410/pm-h1940.S33
-rw-r--r--arch/arm/mach-s3c2410/pm.c180
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c206
-rw-r--r--arch/arm/mach-s3c2410/sleep.S68
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c132
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.h16
73 files changed, 0 insertions, 9069 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index ce620993bec1..68d89cb96af0 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -2,42 +2,6 @@
2# 2#
3# Licensed under GPLv2 3# Licensed under GPLv2
4 4
5config CPU_S3C2410
6 bool
7 depends on ARCH_S3C24XX
8 select CPU_ARM920T
9 select S3C2410_CLOCK
10 select CPU_LLSERIAL_S3C2410
11 select S3C2410_PM if PM
12 select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
13 help
14 Support for S3C2410 and S3C2410A family from the S3C24XX line
15 of Samsung Mobile CPUs.
16
17config CPU_S3C2410_DMA
18 bool
19 depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442)
20 default y if CPU_S3C2410 || CPU_S3C2442
21 help
22 DMA device selection for S3C2410 and compatible CPUs
23
24config S3C2410_PM
25 bool
26 help
27 Power Management code common to S3C2410 and better
28
29config SIMTEC_NOR
30 bool
31 help
32 Internal node to specify machine has simtec NOR mapping
33
34config MACH_BAST_IDE
35 bool
36 select HAVE_PATA_PLATFORM
37 help
38 Internal node for machines with an BAST style IDE
39 interface
40
41# cpu frequency scaling support 5# cpu frequency scaling support
42 6
43config S3C2410_CPUFREQ 7config S3C2410_CPUFREQ
@@ -54,121 +18,3 @@ config S3C2410_PLLTABLE
54 help 18 help
55 Select the PLL table for the S3C2410 19 Select the PLL table for the S3C2410
56 20
57menu "S3C2410 Machines"
58
59config ARCH_SMDK2410
60 bool "SMDK2410/A9M2410"
61 select CPU_S3C2410
62 select MACH_SMDK
63 help
64 Say Y here if you are using the SMDK2410 or the derived module A9M2410
65 <http://www.fsforth.de>
66
67config ARCH_H1940
68 bool "IPAQ H1940"
69 select CPU_S3C2410
70 select PM_H1940 if PM
71 select S3C_DEV_USB_HOST
72 select S3C_DEV_NAND
73 select S3C2410_SETUP_TS
74 help
75 Say Y here if you are using the HP IPAQ H1940
76
77config H1940BT
78 tristate "Control the state of H1940 bluetooth chip"
79 depends on ARCH_H1940
80 select RFKILL
81 help
82 This is a simple driver that is able to control
83 the state of built in bluetooth chip on h1940.
84
85config PM_H1940
86 bool
87 help
88 Internal node for H1940 and related PM
89
90config MACH_N30
91 bool "Acer N30 family"
92 select CPU_S3C2410
93 select MACH_N35
94 select S3C_DEV_USB_HOST
95 select S3C_DEV_NAND
96 help
97 Say Y here if you want suppt for the Acer N30, Acer N35,
98 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
99
100config MACH_N35
101 bool
102 help
103 Internal node in order to enable support for Acer N35 if Acer N30 is
104 selected.
105
106config ARCH_BAST
107 bool "Simtec Electronics BAST (EB2410ITX)"
108 select CPU_S3C2410
109 select S3C2410_IOTIMING if S3C2410_CPUFREQ
110 select PM_SIMTEC if PM
111 select SIMTEC_NOR
112 select MACH_BAST_IDE
113 select S3C24XX_DCLK
114 select ISA
115 select S3C_DEV_HWMON
116 select S3C_DEV_USB_HOST
117 select S3C_DEV_NAND
118 help
119 Say Y here if you are using the Simtec Electronics EB2410ITX
120 development board (also known as BAST)
121
122config MACH_OTOM
123 bool "NexVision OTOM Board"
124 select CPU_S3C2410
125 select S3C_DEV_USB_HOST
126 select S3C_DEV_NAND
127 help
128 Say Y here if you are using the Nex Vision OTOM board
129
130config MACH_AML_M5900
131 bool "AML M5900 Series"
132 select CPU_S3C2410
133 select PM_SIMTEC if PM
134 select S3C_DEV_USB_HOST
135 help
136 Say Y here if you are using the American Microsystems M5900 Series
137 <http://www.amltd.com>
138
139config BAST_PC104_IRQ
140 bool "BAST PC104 IRQ support"
141 depends on ARCH_BAST
142 default y
143 help
144 Say Y here to enable the PC104 IRQ routing on the
145 Simtec BAST (EB2410ITX)
146
147config MACH_TCT_HAMMER
148 bool "TCT Hammer Board"
149 select CPU_S3C2410
150 select S3C_DEV_USB_HOST
151 help
152 Say Y here if you are using the TinCanTools Hammer Board
153 <http://www.tincantools.com>
154
155config MACH_VR1000
156 bool "Thorcom VR1000"
157 select PM_SIMTEC if PM
158 select S3C24XX_DCLK
159 select SIMTEC_NOR
160 select MACH_BAST_IDE
161 select CPU_S3C2410
162 select S3C_DEV_USB_HOST
163 help
164 Say Y here if you are using the Thorcom VR1000 board.
165
166config MACH_QT2410
167 bool "QT2410"
168 select CPU_S3C2410
169 select S3C_DEV_USB_HOST
170 select S3C_DEV_NAND
171 help
172 Say Y here if you are using the Armzone QT2410
173
174endmenu
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 782fd81144e9..6b9a316e0041 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -9,32 +9,6 @@ obj-m :=
9obj-n := 9obj-n :=
10obj- := 10obj- :=
11 11
12obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
13obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
14obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
15obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
16obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o 12obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o
17obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o 13obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
18 14
19# Machine support
20
21obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o
22obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
23obj-$(CONFIG_H1940BT) += h1940-bluetooth.o
24obj-$(CONFIG_PM_H1940) += pm-h1940.o
25obj-$(CONFIG_MACH_N30) += mach-n30.o
26obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
27obj-$(CONFIG_MACH_OTOM) += mach-otom.o
28obj-$(CONFIG_MACH_AML_M5900) += mach-amlm5900.o
29obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
30obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o
31obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
32obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o
33
34# Common bits of machine support
35
36obj-$(CONFIG_SIMTEC_NOR) += nor-simtec.o
37
38# machine additions
39
40obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o
diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot
deleted file mode 100644
index 4457605ba04a..000000000000
--- a/arch/arm/mach-s3c2410/Makefile.boot
+++ /dev/null
@@ -1,7 +0,0 @@
1ifeq ($(CONFIG_PM_H1940),y)
2 zreladdr-y += 0x30108000
3 params_phys-y := 0x30100100
4else
5 zreladdr-y += 0x30008000
6 params_phys-y := 0x30000100
7endif
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c2410/bast-ide.c
deleted file mode 100644
index 298ececfa366..000000000000
--- a/arch/arm/mach-s3c2410/bast-ide.c
+++ /dev/null
@@ -1,112 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/bast-ide.c
2 *
3 * Copyright 2007 Simtec Electronics
4 * http://www.simtec.co.uk/products/EB2410ITX/
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17
18#include <linux/platform_device.h>
19#include <linux/ata_platform.h>
20
21#include <asm/mach-types.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <mach/map.h>
28#include <mach/bast-map.h>
29#include <mach/bast-irq.h>
30
31/* IDE ports */
32
33static struct pata_platform_info bast_ide_platdata = {
34 .ioport_shift = 5,
35};
36
37#define IDE_CS S3C2410_CS5
38
39static struct resource bast_ide0_resource[] = {
40 [0] = {
41 .start = IDE_CS + BAST_PA_IDEPRI,
42 .end = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
47 .end = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
48 .flags = IORESOURCE_MEM,
49 },
50 [2] = {
51 .start = IRQ_IDE0,
52 .end = IRQ_IDE0,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct platform_device bast_device_ide0 = {
58 .name = "pata_platform",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(bast_ide0_resource),
61 .resource = bast_ide0_resource,
62 .dev = {
63 .platform_data = &bast_ide_platdata,
64 .coherent_dma_mask = ~0,
65 }
66
67};
68
69static struct resource bast_ide1_resource[] = {
70 [0] = {
71 .start = IDE_CS + BAST_PA_IDESEC,
72 .end = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
73 .flags = IORESOURCE_MEM,
74 },
75 [1] = {
76 .start = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
77 .end = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
78 .flags = IORESOURCE_MEM,
79 },
80 [2] = {
81 .start = IRQ_IDE1,
82 .end = IRQ_IDE1,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct platform_device bast_device_ide1 = {
88 .name = "pata_platform",
89 .id = 1,
90 .num_resources = ARRAY_SIZE(bast_ide1_resource),
91 .resource = bast_ide1_resource,
92 .dev = {
93 .platform_data = &bast_ide_platdata,
94 .coherent_dma_mask = ~0,
95 }
96};
97
98static struct platform_device *bast_ide_devices[] __initdata = {
99 &bast_device_ide0,
100 &bast_device_ide1,
101};
102
103static __init int bast_ide_init(void)
104{
105 if (machine_is_bast() || machine_is_vr1000())
106 return platform_add_devices(bast_ide_devices,
107 ARRAY_SIZE(bast_ide_devices));
108
109 return 0;
110}
111
112fs_initcall(bast_ide_init);
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
deleted file mode 100644
index ac7b2ad5c405..000000000000
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ /dev/null
@@ -1,166 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/bast-irq.c
2 *
3 * Copyright 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/ioport.h>
27#include <linux/device.h>
28#include <linux/io.h>
29
30#include <asm/mach-types.h>
31
32#include <mach/hardware.h>
33#include <asm/irq.h>
34
35#include <asm/mach/irq.h>
36
37#include <mach/regs-irq.h>
38#include <mach/bast-map.h>
39#include <mach/bast-irq.h>
40
41#include <plat/irq.h>
42
43#if 0
44#include <asm/debug-ll.h>
45#endif
46
47#define irqdbf(x...)
48#define irqdbf2(x...)
49
50
51/* handle PC104 ISA interrupts from the system CPLD */
52
53/* table of ISA irq nos to the relevant mask... zero means
54 * the irq is not implemented
55*/
56static unsigned char bast_pc104_irqmasks[] = {
57 0, /* 0 */
58 0, /* 1 */
59 0, /* 2 */
60 1, /* 3 */
61 0, /* 4 */
62 2, /* 5 */
63 0, /* 6 */
64 4, /* 7 */
65 0, /* 8 */
66 0, /* 9 */
67 8, /* 10 */
68 0, /* 11 */
69 0, /* 12 */
70 0, /* 13 */
71 0, /* 14 */
72 0, /* 15 */
73};
74
75static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
76
77static void
78bast_pc104_mask(struct irq_data *data)
79{
80 unsigned long temp;
81
82 temp = __raw_readb(BAST_VA_PC104_IRQMASK);
83 temp &= ~bast_pc104_irqmasks[data->irq];
84 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
85}
86
87static void
88bast_pc104_maskack(struct irq_data *data)
89{
90 struct irq_desc *desc = irq_desc + IRQ_ISA;
91
92 bast_pc104_mask(data);
93 desc->irq_data.chip->irq_ack(&desc->irq_data);
94}
95
96static void
97bast_pc104_unmask(struct irq_data *data)
98{
99 unsigned long temp;
100
101 temp = __raw_readb(BAST_VA_PC104_IRQMASK);
102 temp |= bast_pc104_irqmasks[data->irq];
103 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
104}
105
106static struct irq_chip bast_pc104_chip = {
107 .irq_mask = bast_pc104_mask,
108 .irq_unmask = bast_pc104_unmask,
109 .irq_ack = bast_pc104_maskack
110};
111
112static void
113bast_irq_pc104_demux(unsigned int irq,
114 struct irq_desc *desc)
115{
116 unsigned int stat;
117 unsigned int irqno;
118 int i;
119
120 stat = __raw_readb(BAST_VA_PC104_IRQREQ) & 0xf;
121
122 if (unlikely(stat == 0)) {
123 /* ack if we get an irq with nothing (ie, startup) */
124
125 desc = irq_desc + IRQ_ISA;
126 desc->irq_data.chip->irq_ack(&desc->irq_data);
127 } else {
128 /* handle the IRQ */
129
130 for (i = 0; stat != 0; i++, stat >>= 1) {
131 if (stat & 1) {
132 irqno = bast_pc104_irqs[i];
133 generic_handle_irq(irqno);
134 }
135 }
136 }
137}
138
139static __init int bast_irq_init(void)
140{
141 unsigned int i;
142
143 if (machine_is_bast()) {
144 printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
145
146 /* zap all the IRQs */
147
148 __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
149
150 irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
151
152 /* register our IRQs */
153
154 for (i = 0; i < 4; i++) {
155 unsigned int irqno = bast_pc104_irqs[i];
156
157 irq_set_chip_and_handler(irqno, &bast_pc104_chip,
158 handle_level_irq);
159 set_irq_flags(irqno, IRQF_VALID);
160 }
161 }
162
163 return 0;
164}
165
166arch_initcall(bast_irq_init);
diff --git a/arch/arm/mach-s3c2410/common.h b/arch/arm/mach-s3c2410/common.h
deleted file mode 100644
index f65dc8062961..000000000000
--- a/arch/arm/mach-s3c2410/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for S3C2410 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_S3C2410_COMMON_H
13#define __ARCH_ARM_MACH_S3C2410_COMMON_H
14
15void s3c2410_restart(char mode, const char *cmd);
16
17#endif /* __ARCH_ARM_MACH_S3C2410_COMMON_H */
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
deleted file mode 100644
index 2afd00014a77..000000000000
--- a/arch/arm/mach-s3c2410/dma.c
+++ /dev/null
@@ -1,185 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/dma.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/serial_core.h>
19
20#include <mach/map.h>
21#include <mach/dma.h>
22
23#include <plat/cpu.h>
24#include <plat/dma-s3c24xx.h>
25
26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h>
34#include <plat/regs-spi.h>
35
36static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
37 [DMACH_XD0] = {
38 .name = "xdreq0",
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
40 },
41 [DMACH_XD1] = {
42 .name = "xdreq1",
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
44 },
45 [DMACH_SDI] = {
46 .name = "sdi",
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 },
51 [DMACH_SPI0] = {
52 .name = "spi0",
53 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
54 },
55 [DMACH_SPI1] = {
56 .name = "spi1",
57 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
58 },
59 [DMACH_UART0] = {
60 .name = "uart0",
61 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
62 },
63 [DMACH_UART1] = {
64 .name = "uart1",
65 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
66 },
67 [DMACH_UART2] = {
68 .name = "uart2",
69 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
70 },
71 [DMACH_TIMER] = {
72 .name = "timer",
73 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
74 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
75 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
76 },
77 [DMACH_I2S_IN] = {
78 .name = "i2s-sdi",
79 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
80 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
81 },
82 [DMACH_I2S_OUT] = {
83 .name = "i2s-sdo",
84 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
85 },
86 [DMACH_USB_EP1] = {
87 .name = "usb-ep1",
88 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
89 },
90 [DMACH_USB_EP2] = {
91 .name = "usb-ep2",
92 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
93 },
94 [DMACH_USB_EP3] = {
95 .name = "usb-ep3",
96 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
97 },
98 [DMACH_USB_EP4] = {
99 .name = "usb-ep4",
100 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
101 },
102};
103
104static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
105 struct s3c24xx_dma_map *map)
106{
107 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
108}
109
110static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
111 .select = s3c2410_dma_select,
112 .dcon_mask = 7 << 24,
113 .map = s3c2410_dma_mappings,
114 .map_size = ARRAY_SIZE(s3c2410_dma_mappings),
115};
116
117static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
118 .channels = {
119 [DMACH_SDI] = {
120 .list = {
121 [0] = 3 | DMA_CH_VALID,
122 [1] = 2 | DMA_CH_VALID,
123 [2] = 0 | DMA_CH_VALID,
124 },
125 },
126 [DMACH_I2S_IN] = {
127 .list = {
128 [0] = 1 | DMA_CH_VALID,
129 [1] = 2 | DMA_CH_VALID,
130 },
131 },
132 },
133};
134
135static int __init s3c2410_dma_add(struct device *dev)
136{
137 s3c2410_dma_init();
138 s3c24xx_dma_order_set(&s3c2410_dma_order);
139 return s3c24xx_dma_init_map(&s3c2410_dma_sel);
140}
141
142#if defined(CONFIG_CPU_S3C2410)
143static struct subsys_interface s3c2410_dma_interface = {
144 .name = "s3c2410_dma",
145 .subsys = &s3c2410_subsys,
146 .add_dev = s3c2410_dma_add,
147};
148
149static int __init s3c2410_dma_drvinit(void)
150{
151 return subsys_interface_register(&s3c2410_interface);
152}
153
154arch_initcall(s3c2410_dma_drvinit);
155
156static struct subsys_interface s3c2410a_dma_interface = {
157 .name = "s3c2410a_dma",
158 .subsys = &s3c2410a_subsys,
159 .add_dev = s3c2410_dma_add,
160};
161
162static int __init s3c2410a_dma_drvinit(void)
163{
164 return subsys_interface_register(&s3c2410a_dma_interface);
165}
166
167arch_initcall(s3c2410a_dma_drvinit);
168#endif
169
170#if defined(CONFIG_CPU_S3C2442)
171/* S3C2442 DMA contains the same selection table as the S3C2410 */
172static struct subsys_interface s3c2442_dma_interface = {
173 .name = "s3c2442_dma",
174 .subsys = &s3c2442_subsys,
175 .add_dev = s3c2410_dma_add,
176};
177
178static int __init s3c2442_dma_drvinit(void)
179{
180 return subsys_interface_register(&s3c2442_dma_interface);
181}
182
183arch_initcall(s3c2442_dma_drvinit);
184#endif
185
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
deleted file mode 100644
index a5eeb62ce1c2..000000000000
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * arch/arm/mach-s3c2410/h1940-bluetooth.c
3 * Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 *
9 * S3C2410 bluetooth "driver"
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/leds.h>
19#include <linux/gpio.h>
20#include <linux/rfkill.h>
21
22#include <mach/regs-gpio.h>
23#include <mach/hardware.h>
24#include <mach/h1940-latch.h>
25#include <mach/h1940.h>
26
27#define DRV_NAME "h1940-bt"
28
29/* Bluetooth control */
30static void h1940bt_enable(int on)
31{
32 if (on) {
33 /* Power on the chip */
34 gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1);
35 /* Reset the chip */
36 mdelay(10);
37
38 gpio_set_value(S3C2410_GPH(1), 1);
39 mdelay(10);
40 gpio_set_value(S3C2410_GPH(1), 0);
41
42 h1940_led_blink_set(-EINVAL, GPIO_LED_BLINK, NULL, NULL);
43 }
44 else {
45 gpio_set_value(S3C2410_GPH(1), 1);
46 mdelay(10);
47 gpio_set_value(S3C2410_GPH(1), 0);
48 mdelay(10);
49 gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
50
51 h1940_led_blink_set(-EINVAL, GPIO_LED_NO_BLINK_LOW, NULL, NULL);
52 }
53}
54
55static int h1940bt_set_block(void *data, bool blocked)
56{
57 h1940bt_enable(!blocked);
58 return 0;
59}
60
61static const struct rfkill_ops h1940bt_rfkill_ops = {
62 .set_block = h1940bt_set_block,
63};
64
65static int __devinit h1940bt_probe(struct platform_device *pdev)
66{
67 struct rfkill *rfk;
68 int ret = 0;
69
70 ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
71 if (ret) {
72 dev_err(&pdev->dev, "could not get GPH1\n");
73 return ret;
74 }
75
76 ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev));
77 if (ret) {
78 gpio_free(S3C2410_GPH(1));
79 dev_err(&pdev->dev, "could not get BT_POWER\n");
80 return ret;
81 }
82
83 /* Configures BT serial port GPIOs */
84 s3c_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
85 s3c_gpio_setpull(S3C2410_GPH(0), S3C_GPIO_PULL_NONE);
86 s3c_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
87 s3c_gpio_setpull(S3C2410_GPH(1), S3C_GPIO_PULL_NONE);
88 s3c_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
89 s3c_gpio_setpull(S3C2410_GPH(2), S3C_GPIO_PULL_NONE);
90 s3c_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
91 s3c_gpio_setpull(S3C2410_GPH(3), S3C_GPIO_PULL_NONE);
92
93 rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
94 &h1940bt_rfkill_ops, NULL);
95 if (!rfk) {
96 ret = -ENOMEM;
97 goto err_rfk_alloc;
98 }
99
100 ret = rfkill_register(rfk);
101 if (ret)
102 goto err_rfkill;
103
104 platform_set_drvdata(pdev, rfk);
105
106 return 0;
107
108err_rfkill:
109 rfkill_destroy(rfk);
110err_rfk_alloc:
111 return ret;
112}
113
114static int h1940bt_remove(struct platform_device *pdev)
115{
116 struct rfkill *rfk = platform_get_drvdata(pdev);
117
118 platform_set_drvdata(pdev, NULL);
119 gpio_free(S3C2410_GPH(1));
120
121 if (rfk) {
122 rfkill_unregister(rfk);
123 rfkill_destroy(rfk);
124 }
125 rfk = NULL;
126
127 h1940bt_enable(0);
128
129 return 0;
130}
131
132
133static struct platform_driver h1940bt_driver = {
134 .driver = {
135 .name = DRV_NAME,
136 },
137 .probe = h1940bt_probe,
138 .remove = h1940bt_remove,
139};
140
141
142static int __init h1940bt_init(void)
143{
144 return platform_driver_register(&h1940bt_driver);
145}
146
147static void __exit h1940bt_exit(void)
148{
149 platform_driver_unregister(&h1940bt_driver);
150}
151
152module_init(h1940bt_init);
153module_exit(h1940bt_exit);
154
155MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
156MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
157MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
deleted file mode 100644
index 1b614d5a81f3..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * ANUBIS - CPLD control constants
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_ANUBISCPLD_H
15#define __ASM_ARCH_ANUBISCPLD_H
16
17/* CTRL2 - NAND WP control, IDE Reset assert/check */
18
19#define ANUBIS_CTRL1_NANDSEL (0x3)
20
21/* IDREG - revision */
22
23#define ANUBIS_IDREG_REVMASK (0x7)
24
25#endif /* __ASM_ARCH_ANUBISCPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c2410/include/mach/anubis-irq.h
deleted file mode 100644
index a2a328134e34..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/anubis-irq.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * ANUBIS - IRQ Number definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_ANUBISIRQ_H
15#define __ASM_ARCH_ANUBISIRQ_H
16
17#define IRQ_IDE0 IRQ_EINT2
18#define IRQ_IDE1 IRQ_EINT3
19#define IRQ_ASIX IRQ_EINT1
20
21#endif /* __ASM_ARCH_ANUBISIRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c2410/include/mach/anubis-map.h
deleted file mode 100644
index c9deb3a5b2c3..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/anubis-map.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/anubis-map.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * ANUBIS - Memory map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* needs arch/map.h including with this */
15
16#ifndef __ASM_ARCH_ANUBISMAP_H
17#define __ASM_ARCH_ANUBISMAP_H
18
19/* start peripherals off after the S3C2410 */
20
21#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
22
23#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
24
25/* we put the CPLD registers next, to get them out of the way */
26
27#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
28#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
29
30#define ANUBIS_VA_IDREG ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
31#define ANUBIS_PA_IDREG (ANUBIS_PA_CPLD + (3<<23))
32
33#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
34#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
35#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
36#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
37
38#endif /* __ASM_ARCH_ANUBISMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
deleted file mode 100644
index bee2a7a932a0..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * BAST - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_BASTCPLD_H
14#define __ASM_ARCH_BASTCPLD_H
15
16/* CTRL1 - Audio LR routing */
17
18#define BAST_CPLD_CTRL1_LRCOFF (0x00)
19#define BAST_CPLD_CTRL1_LRCADC (0x01)
20#define BAST_CPLD_CTRL1_LRCDAC (0x02)
21#define BAST_CPLD_CTRL1_LRCARM (0x03)
22#define BAST_CPLD_CTRL1_LRMASK (0x03)
23
24/* CTRL2 - NAND WP control, IDE Reset assert/check */
25
26#define BAST_CPLD_CTRL2_WNAND (0x04)
27#define BAST_CPLD_CTLR2_IDERST (0x08)
28
29/* CTRL3 - rom write control, CPLD identity */
30
31#define BAST_CPLD_CTRL3_IDMASK (0x0e)
32#define BAST_CPLD_CTRL3_ROMWEN (0x01)
33
34/* CTRL4 - 8bit LCD interface control/status */
35
36#define BAST_CPLD_CTRL4_LLAT (0x01)
37#define BAST_CPLD_CTRL4_LCDRW (0x02)
38#define BAST_CPLD_CTRL4_LCDCMD (0x04)
39#define BAST_CPLD_CTRL4_LCDE2 (0x01)
40
41/* CTRL5 - DMA routing */
42
43#define BAST_CPLD_DMA0_PRIIDE (0<<0)
44#define BAST_CPLD_DMA0_SECIDE (1<<0)
45#define BAST_CPLD_DMA0_ISA15 (2<<0)
46#define BAST_CPLD_DMA0_ISA36 (3<<0)
47
48#define BAST_CPLD_DMA1_PRIIDE (0<<2)
49#define BAST_CPLD_DMA1_SECIDE (1<<2)
50#define BAST_CPLD_DMA1_ISA15 (2<<2)
51#define BAST_CPLD_DMA1_ISA36 (3<<2)
52
53#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
deleted file mode 100644
index cac428c42e7f..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-irq.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_BASTIRQ_H
14#define __ASM_ARCH_BASTIRQ_H
15
16/* irq numbers to onboard peripherals */
17
18#define IRQ_USBOC IRQ_EINT18
19#define IRQ_IDE0 IRQ_EINT16
20#define IRQ_IDE1 IRQ_EINT17
21#define IRQ_PCSERIAL1 IRQ_EINT15
22#define IRQ_PCSERIAL2 IRQ_EINT14
23#define IRQ_PCPARALLEL IRQ_EINT13
24#define IRQ_ASIX IRQ_EINT11
25#define IRQ_DM9000 IRQ_EINT10
26#define IRQ_ISA IRQ_EINT9
27#define IRQ_SMALERT IRQ_EINT8
28
29#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h
deleted file mode 100644
index 6e7dc9d0cf0e..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/bast-map.h
+++ /dev/null
@@ -1,146 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-map.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine BAST - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x13000000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space. We also have the board's CPLD to find register space
18 * for.
19 */
20
21#ifndef __ASM_ARCH_BASTMAP_H
22#define __ASM_ARCH_BASTMAP_H
23
24#define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
25
26/* we put the CPLD registers next, to get them out of the way */
27
28#define BAST_VA_CTRL1 BAST_IOADDR(0x00000000) /* 0x01300000 */
29#define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
30
31#define BAST_VA_CTRL2 BAST_IOADDR(0x00100000) /* 0x01400000 */
32#define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
33
34#define BAST_VA_CTRL3 BAST_IOADDR(0x00200000) /* 0x01500000 */
35#define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
36
37#define BAST_VA_CTRL4 BAST_IOADDR(0x00300000) /* 0x01600000 */
38#define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
39
40/* next, we have the PC104 ISA interrupt registers */
41
42#define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
43#define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
44
45#define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
46#define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
47
48#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
49#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
50
51#define BAST_PA_LCD_RCMD1 (0x8800000)
52#define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
53
54#define BAST_PA_LCD_WCMD1 (0x8000000)
55#define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
56
57#define BAST_PA_LCD_RDATA1 (0x9800000)
58#define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
59
60#define BAST_PA_LCD_WDATA1 (0x9000000)
61#define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
62
63#define BAST_PA_LCD_RCMD2 (0xA800000)
64#define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
65
66#define BAST_PA_LCD_WCMD2 (0xA000000)
67#define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
68
69#define BAST_PA_LCD_RDATA2 (0xB800000)
70#define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
71
72#define BAST_PA_LCD_WDATA2 (0xB000000)
73#define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
74
75
76/* 0xE0000000 contains the IO space that is split by speed and
77 * wether the access is for 8 or 16bit IO... this ensures that
78 * the correct access is made
79 *
80 * 0x10000000 of space, partitioned as so:
81 *
82 * 0x00000000 to 0x04000000 8bit, slow
83 * 0x04000000 to 0x08000000 16bit, slow
84 * 0x08000000 to 0x0C000000 16bit, net
85 * 0x0C000000 to 0x10000000 16bit, fast
86 *
87 * each of these spaces has the following in:
88 *
89 * 0x00000000 to 0x01000000 16MB ISA IO space
90 * 0x01000000 to 0x02000000 16MB ISA memory space
91 * 0x02000000 to 0x02100000 1MB IDE primary channel
92 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
93 * 0x02200000 to 0x02400000 1MB IDE secondary channel
94 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
95 * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
96 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
97 * 0x02600000 to 0x02700000 1MB PC SuperIO controller
98 *
99 * the phyiscal layout of the zones are:
100 * nGCS2 - 8bit, slow
101 * nGCS3 - 16bit, slow
102 * nGCS4 - 16bit, net
103 * nGCS5 - 16bit, fast
104 */
105
106#define BAST_VA_MULTISPACE (0xE0000000)
107
108#define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
109#define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
110#define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
111#define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
112#define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
113#define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
114#define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
115#define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
116#define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
117
118#define BAST_VA_MULTISPACE (0xE0000000)
119
120#define BAST_VAM_CS2 (0x00000000)
121#define BAST_VAM_CS3 (0x04000000)
122#define BAST_VAM_CS4 (0x08000000)
123#define BAST_VAM_CS5 (0x0C000000)
124
125/* physical offset addresses for the peripherals */
126
127#define BAST_PA_ISAIO (0x00000000)
128#define BAST_PA_ASIXNET (0x01000000)
129#define BAST_PA_SUPERIO (0x01800000)
130#define BAST_PA_IDEPRI (0x02000000)
131#define BAST_PA_IDEPRIAUX (0x02800000)
132#define BAST_PA_IDESEC (0x03000000)
133#define BAST_PA_IDESECAUX (0x03800000)
134#define BAST_PA_ISAMEM (0x04000000)
135#define BAST_PA_DM9000 (0x05000000)
136
137/* some configurations for the peripherals */
138
139#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
140/* */
141
142#define BAST_ASIXNET_CS BAST_VAM_CS5
143#define BAST_IDE_CS BAST_VAM_CS5
144#define BAST_DM9000_CS BAST_VAM_CS4
145
146#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
deleted file mode 100644
index 4c38b39b741d..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * Machine BAST - Power Management chip
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_BASTPMU_H
15#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
16
17#define BASTPMU_REG_IDENT (0x00)
18#define BASTPMU_REG_VERSION (0x01)
19#define BASTPMU_REG_DDCCTRL (0x02)
20#define BASTPMU_REG_POWER (0x03)
21#define BASTPMU_REG_RESET (0x04)
22#define BASTPMU_REG_GWO (0x05)
23#define BASTPMU_REG_WOL (0x06)
24#define BASTPMU_REG_WOR (0x07)
25#define BASTPMU_REG_UID (0x09)
26
27#define BASTPMU_EEPROM (0xC0)
28
29#define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0)
30#define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8)
31#define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9)
32
33#define BASTPMU_IDENT_0 0x53
34#define BASTPMU_IDENT_1 0x42
35#define BASTPMU_IDENT_2 0x50
36#define BASTPMU_IDENT_3 0x4d
37
38#define BASTPMU_RESET_GUARD (0x55)
39
40#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
deleted file mode 100644
index 4135de87d1f7..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ /dev/null
@@ -1,101 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Copyright (C) 2005 Simtec Electronics
7 *
8 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <mach/map.h>
16#include <mach/regs-gpio.h>
17#include <plat/regs-serial.h>
18
19#define S3C2410_UART1_OFF (0x4000)
20#define SHIFT_2440TXF (14-9)
21
22 .macro addruart, rp, rv, tmp
23 ldr \rp, = S3C24XX_PA_UART
24 ldr \rv, = S3C24XX_VA_UART
25#if CONFIG_DEBUG_S3C_UART != 0
26 add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
27 add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
28#endif
29 .endm
30
31 .macro fifo_full_s3c24xx rd, rx
32 @ check for arm920 vs arm926. currently assume all arm926
33 @ devices have an 64 byte FIFO identical to the s3c2440
34 mrc p15, 0, \rd, c0, c0
35 and \rd, \rd, #0xff0
36 teq \rd, #0x260
37 beq 1004f
38 mrc p15, 0, \rd, c1, c0
39 tst \rd, #1
40 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
41 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
42 bic \rd, \rd, #0xff000
43 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
44 and \rd, \rd, #0x00ff0000
45 teq \rd, #0x00440000 @ is it 2440?
461004:
47 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
48 moveq \rd, \rd, lsr #SHIFT_2440TXF
49 tst \rd, #S3C2410_UFSTAT_TXFULL
50 .endm
51
52 .macro fifo_full_s3c2410 rd, rx
53 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
54 tst \rd, #S3C2410_UFSTAT_TXFULL
55 .endm
56
57/* fifo level reading */
58
59 .macro fifo_level_s3c24xx rd, rx
60 @ check for arm920 vs arm926. currently assume all arm926
61 @ devices have an 64 byte FIFO identical to the s3c2440
62 mrc p15, 0, \rd, c0, c0
63 and \rd, \rd, #0xff0
64 teq \rd, #0x260
65 beq 10000f
66 mrc p15, 0, \rd, c1, c0
67 tst \rd, #1
68 addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
69 addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
70 bic \rd, \rd, #0xff000
71 ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
72 and \rd, \rd, #0x00ff0000
73 teq \rd, #0x00440000 @ is it 2440?
74
7510000:
76 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
77 andne \rd, \rd, #S3C2410_UFSTAT_TXMASK
78 andeq \rd, \rd, #S3C2440_UFSTAT_TXMASK
79 .endm
80
81 .macro fifo_level_s3c2410 rd, rx
82 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
83 and \rd, \rd, #S3C2410_UFSTAT_TXMASK
84 .endm
85
86/* Select the correct implementation depending on the configuration. The
87 * S3C2440 will get selected by default, as these are the most widely
88 * used variants of these
89*/
90
91#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
92#define fifo_full fifo_full_s3c2410
93#define fifo_level fifo_level_s3c2410
94#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
95#define fifo_full fifo_full_s3c24xx
96#define fifo_level fifo_level_s3c24xx
97#endif
98
99/* include the reset of the code which will do the work */
100
101#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
deleted file mode 100644
index acbdfecd4186..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ /dev/null
@@ -1,210 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H __FILE__
15
16#include <linux/device.h>
17
18#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
19
20/* We use `virtual` dma channels to hide the fact we have only a limited
21 * number of DMA channels, and not of all of them (dependent on the device)
22 * can be attached to any DMA source. We therefore let the DMA core handle
23 * the allocation of hardware channels to clients.
24*/
25
26enum dma_ch {
27 DMACH_XD0,
28 DMACH_XD1,
29 DMACH_SDI,
30 DMACH_SPI0,
31 DMACH_SPI1,
32 DMACH_UART0,
33 DMACH_UART1,
34 DMACH_UART2,
35 DMACH_TIMER,
36 DMACH_I2S_IN,
37 DMACH_I2S_OUT,
38 DMACH_PCM_IN,
39 DMACH_PCM_OUT,
40 DMACH_MIC_IN,
41 DMACH_USB_EP1,
42 DMACH_USB_EP2,
43 DMACH_USB_EP3,
44 DMACH_USB_EP4,
45 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
46 DMACH_UART1_SRC2,
47 DMACH_UART2_SRC2,
48 DMACH_UART3, /* s3c2443 has extra uart */
49 DMACH_UART3_SRC2,
50 DMACH_MAX, /* the end entry */
51};
52
53static inline bool samsung_dma_has_circular(void)
54{
55 return false;
56}
57
58static inline bool samsung_dma_is_dmadev(void)
59{
60 return false;
61}
62
63#include <plat/dma.h>
64
65#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
66
67/* we have 4 dma channels */
68#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
69#define S3C_DMA_CHANNELS (4)
70#else
71#define S3C_DMA_CHANNELS (6)
72#endif
73
74/* types */
75
76enum s3c2410_dma_state {
77 S3C2410_DMA_IDLE,
78 S3C2410_DMA_RUNNING,
79 S3C2410_DMA_PAUSED
80};
81
82/* enum s3c2410_dma_loadst
83 *
84 * This represents the state of the DMA engine, wrt to the loaded / running
85 * transfers. Since we don't have any way of knowing exactly the state of
86 * the DMA transfers, we need to know the state to make decisions on wether
87 * we can
88 *
89 * S3C2410_DMA_NONE
90 *
91 * There are no buffers loaded (the channel should be inactive)
92 *
93 * S3C2410_DMA_1LOADED
94 *
95 * There is one buffer loaded, however it has not been confirmed to be
96 * loaded by the DMA engine. This may be because the channel is not
97 * yet running, or the DMA driver decided that it was too costly to
98 * sit and wait for it to happen.
99 *
100 * S3C2410_DMA_1RUNNING
101 *
102 * The buffer has been confirmed running, and not finisged
103 *
104 * S3C2410_DMA_1LOADED_1RUNNING
105 *
106 * There is a buffer waiting to be loaded by the DMA engine, and one
107 * currently running.
108*/
109
110enum s3c2410_dma_loadst {
111 S3C2410_DMALOAD_NONE,
112 S3C2410_DMALOAD_1LOADED,
113 S3C2410_DMALOAD_1RUNNING,
114 S3C2410_DMALOAD_1LOADED_1RUNNING,
115};
116
117
118/* flags */
119
120#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
121 * waiting for reloads */
122#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
123
124#define S3C2410_DMAF_CIRCULAR (1 << 2) /* no circular dma support */
125
126/* dma buffer */
127
128struct s3c2410_dma_buf;
129
130/* s3c2410_dma_buf
131 *
132 * internally used buffer structure to describe a queued or running
133 * buffer.
134*/
135
136struct s3c2410_dma_buf {
137 struct s3c2410_dma_buf *next;
138 int magic; /* magic */
139 int size; /* buffer size in bytes */
140 dma_addr_t data; /* start of DMA data */
141 dma_addr_t ptr; /* where the DMA got to [1] */
142 void *id; /* client's id */
143};
144
145/* [1] is this updated for both recv/send modes? */
146
147struct s3c2410_dma_stats {
148 unsigned long loads;
149 unsigned long timeout_longest;
150 unsigned long timeout_shortest;
151 unsigned long timeout_avg;
152 unsigned long timeout_failed;
153};
154
155struct s3c2410_dma_map;
156
157/* struct s3c2410_dma_chan
158 *
159 * full state information for each DMA channel
160*/
161
162struct s3c2410_dma_chan {
163 /* channel state flags and information */
164 unsigned char number; /* number of this dma channel */
165 unsigned char in_use; /* channel allocated */
166 unsigned char irq_claimed; /* irq claimed for channel */
167 unsigned char irq_enabled; /* irq enabled for channel */
168 unsigned char xfer_unit; /* size of an transfer */
169
170 /* channel state */
171
172 enum s3c2410_dma_state state;
173 enum s3c2410_dma_loadst load_state;
174 struct s3c2410_dma_client *client;
175
176 /* channel configuration */
177 enum dma_data_direction source;
178 enum dma_ch req_ch;
179 unsigned long dev_addr;
180 unsigned long load_timeout;
181 unsigned int flags; /* channel flags */
182
183 struct s3c24xx_dma_map *map; /* channel hw maps */
184
185 /* channel's hardware position and configuration */
186 void __iomem *regs; /* channels registers */
187 void __iomem *addr_reg; /* data address register */
188 unsigned int irq; /* channel irq */
189 unsigned long dcon; /* default value of DCON */
190
191 /* driver handles */
192 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
193 s3c2410_dma_opfn_t op_fn; /* channel op callback */
194
195 /* stats gathering */
196 struct s3c2410_dma_stats *stats;
197 struct s3c2410_dma_stats stats_store;
198
199 /* buffer list and information */
200 struct s3c2410_dma_buf *curr; /* current dma buffer */
201 struct s3c2410_dma_buf *next; /* next buffer to load */
202 struct s3c2410_dma_buf *end; /* end of queue */
203
204 /* system device */
205 struct device dev;
206};
207
208typedef unsigned long dma_device_t;
209
210#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c2410/include/mach/entry-macro.S
deleted file mode 100644
index 473b3cd37d9b..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/entry-macro.S
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for S3C2410-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9*/
10
11/* We have a problem that the INTOFFSET register does not always
12 * show one interrupt. Occasionally we get two interrupts through
13 * the prioritiser, and this causes the INTOFFSET register to show
14 * what looks like the logical-or of the two interrupt numbers.
15 *
16 * Thanks to Klaus, Shannon, et al for helping to debug this problem
17*/
18
19#define INTPND (0x10)
20#define INTOFFSET (0x14)
21
22#include <mach/hardware.h>
23#include <asm/irq.h>
24
25 .macro get_irqnr_preamble, base, tmp
26 .endm
27
28 .macro arch_ret_to_user, tmp1, tmp2
29 .endm
30
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32
33 mov \base, #S3C24XX_VA_IRQ
34
35 @@ try the interrupt offset register, since it is there
36
37 ldr \irqstat, [ \base, #INTPND ]
38 teq \irqstat, #0
39 beq 1002f
40 ldr \irqnr, [ \base, #INTOFFSET ]
41 mov \tmp, #1
42 tst \irqstat, \tmp, lsl \irqnr
43 bne 1001f
44
45 @@ the number specified is not a valid irq, so try
46 @@ and work it out for ourselves
47
48 mov \irqnr, #0 @@ start here
49
50 @@ work out which irq (if any) we got
51
52 movs \tmp, \irqstat, lsl#16
53 addeq \irqnr, \irqnr, #16
54 moveq \irqstat, \irqstat, lsr#16
55 tst \irqstat, #0xff
56 addeq \irqnr, \irqnr, #8
57 moveq \irqstat, \irqstat, lsr#8
58 tst \irqstat, #0xf
59 addeq \irqnr, \irqnr, #4
60 moveq \irqstat, \irqstat, lsr#4
61 tst \irqstat, #0x3
62 addeq \irqnr, \irqnr, #2
63 moveq \irqstat, \irqstat, lsr#2
64 tst \irqstat, #0x1
65 addeq \irqnr, \irqnr, #1
66
67 @@ we have the value
681001:
69 adds \irqnr, \irqnr, #IRQ_EINT0
701002:
71 @@ exit here, Z flag unset if IRQ
72
73 .endm
74
75 /* currently don't need an disable_fiq macro */
76
77 .macro disable_fiq
78 .endm
diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c2410/include/mach/fb.h
deleted file mode 100644
index a957bc8ed44f..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/fb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <plat/fb-s3c2410.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
deleted file mode 100644
index c53ad34c6579..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <plat/gpio-fns.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
deleted file mode 100644
index 019ea86057f6..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ /dev/null
@@ -1,118 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - GPIO bank numbering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __MACH_GPIONRS_H
15#define __MACH_GPIONRS_H
16
17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
18
19#define S3C2410_GPIO_BANKG (32*6)
20#define S3C2410_GPIO_BANKH (32*7)
21
22/* GPIO sizes for various SoCs:
23 *
24 * 2442
25 * 2410 2412 2440 2443 2416
26 * ---- ---- ---- ---- ----
27 * A 23 22 25 16 25
28 * B 11 11 11 11 9
29 * C 16 15 16 16 16
30 * D 16 16 16 16 16
31 * E 16 16 16 16 16
32 * F 8 8 8 8 8
33 * G 16 16 16 16 8
34 * H 11 11 9 15 15
35 * J -- -- 13 16 --
36 * K -- -- -- -- 16
37 * L -- -- -- 15 7
38 * M -- -- -- 2 2
39 */
40
41/* GPIO bank sizes */
42#define S3C2410_GPIO_A_NR (32)
43#define S3C2410_GPIO_B_NR (32)
44#define S3C2410_GPIO_C_NR (32)
45#define S3C2410_GPIO_D_NR (32)
46#define S3C2410_GPIO_E_NR (32)
47#define S3C2410_GPIO_F_NR (32)
48#define S3C2410_GPIO_G_NR (32)
49#define S3C2410_GPIO_H_NR (32)
50#define S3C2410_GPIO_J_NR (32) /* technically 16. */
51#define S3C2410_GPIO_K_NR (32) /* technically 16. */
52#define S3C2410_GPIO_L_NR (32) /* technically 15. */
53#define S3C2410_GPIO_M_NR (32) /* technically 2. */
54
55#if CONFIG_S3C_GPIO_SPACE != 0
56#error CONFIG_S3C_GPIO_SPACE cannot be nonzero at the moment
57#endif
58
59#define S3C2410_GPIO_NEXT(__gpio) \
60 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
61
62#ifndef __ASSEMBLY__
63
64enum s3c_gpio_number {
65 S3C2410_GPIO_A_START = 0,
66 S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A),
67 S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B),
68 S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C),
69 S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D),
70 S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E),
71 S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F),
72 S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G),
73 S3C2410_GPIO_J_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_H),
74 S3C2410_GPIO_K_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_J),
75 S3C2410_GPIO_L_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_K),
76 S3C2410_GPIO_M_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_L),
77};
78
79#endif /* __ASSEMBLY__ */
80
81/* S3C2410 GPIO number definitions. */
82
83#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
84#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
85#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
86#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
87#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
88#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
89#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
90#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
91#define S3C2410_GPJ(_nr) (S3C2410_GPIO_J_START + (_nr))
92#define S3C2410_GPK(_nr) (S3C2410_GPIO_K_START + (_nr))
93#define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr))
94#define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr))
95
96/* compatibility until drivers can be modified */
97
98#define S3C2410_GPA0 S3C2410_GPA(0)
99#define S3C2410_GPA1 S3C2410_GPA(1)
100#define S3C2410_GPA3 S3C2410_GPA(3)
101#define S3C2410_GPA7 S3C2410_GPA(7)
102
103#define S3C2410_GPE0 S3C2410_GPE(0)
104#define S3C2410_GPE1 S3C2410_GPE(1)
105#define S3C2410_GPE2 S3C2410_GPE(2)
106#define S3C2410_GPE3 S3C2410_GPE(3)
107#define S3C2410_GPE4 S3C2410_GPE(4)
108#define S3C2410_GPE5 S3C2410_GPE(5)
109#define S3C2410_GPE6 S3C2410_GPE(6)
110#define S3C2410_GPE7 S3C2410_GPE(7)
111#define S3C2410_GPE8 S3C2410_GPE(8)
112#define S3C2410_GPE9 S3C2410_GPE(9)
113#define S3C2410_GPE10 S3C2410_GPE(10)
114
115#define S3C2410_GPH10 S3C2410_GPH(10)
116
117#endif /* __MACH_GPIONRS_H */
118
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
deleted file mode 100644
index c410a078622c..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C2410 - GPIO core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_GPIO_CORE_H
16#define __ASM_ARCH_GPIO_CORE_H __FILE__
17
18#include <mach/regs-gpio.h>
19
20extern struct samsung_gpio_chip s3c24xx_gpios[];
21
22static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
23{
24 struct samsung_gpio_chip *chip;
25
26 if (pin > S3C_GPIO_END)
27 return NULL;
28
29 chip = &s3c24xx_gpios[pin/32];
30 return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
31}
32
33#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
deleted file mode 100644
index 6fac70f3484e..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/gpio.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - GPIO lib support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* some boards require extra gpio capacity to support external
15 * devices that need GPIO.
16 */
17
18#ifdef CONFIG_CPU_S3C244X
19#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
20#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
21#define ARCH_NR_GPIOS (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
22#else
23#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
24#endif
25
26#include <mach/gpio-nrs.h>
27#include <mach/gpio-fns.h>
28
29#ifdef CONFIG_CPU_S3C244X
30#define S3C_GPIO_END (S3C2410_GPJ(0) + 32)
31#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
32#define S3C_GPIO_END (S3C2410_GPM(0) + 32)
33#else
34#define S3C_GPIO_END (S3C2410_GPH(0) + 32)
35#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
deleted file mode 100644
index fc897d3a056c..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/h1940-latch.h
2 *
3 * Copyright (c) 2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * iPAQ H1940 series - latch definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_H1940_LATCH_H
15#define __ASM_ARCH_H1940_LATCH_H
16
17#include <asm/gpio.h>
18
19#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x))
20
21/* SD layer latch */
22
23#define H1940_LATCH_LCD_P0 H1940_LATCH_GPIO(0)
24#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1)
25#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2)
26#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3)
27#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4)
28#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5)
29#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6)
30#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7)
31
32/* CPU layer latch */
33
34#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8)
35#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9)
36#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10)
37#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11)
38#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12)
39#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13)
40#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14)
41#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15)
42
43#endif /* __ASM_ARCH_H1940_LATCH_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c2410/include/mach/h1940.h
deleted file mode 100644
index 2aa683c8d3d6..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/h1940.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/h1940.h
2 *
3 * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_H1940_H
13#define __ASM_ARCH_H1940_H
14
15#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
16#define H1940_SUSPEND_RESUMEAT (0x30081000)
17#define H1940_SUSPEND_CHECK (0x30080000)
18
19extern void h1940_pm_return(void);
20extern int h1940_led_blink_set(unsigned gpio, int state,
21 unsigned long *delay_on, unsigned long *delay_off);
22
23
24#endif /* __ASM_ARCH_H1940_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h
deleted file mode 100644
index aef5631eac58..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/hardware.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - hardware
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H
15
16#ifndef __ASSEMBLY__
17
18extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
19
20#ifdef CONFIG_CPU_S3C2440
21
22extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
23
24#endif /* CONFIG_CPU_S3C2440 */
25
26#ifdef CONFIG_CPU_S3C2412
27
28extern int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state);
29
30#endif /* CONFIG_CPU_S3C2412 */
31
32#endif /* __ASSEMBLY__ */
33
34#include <asm/sizes.h>
35#include <mach/map.h>
36
37/* machine specific hardware definitions should go after this */
38
39/* currently here until moved into config (todo) */
40#define CONFIG_NO_MULTIWORD_IO
41
42#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c2410/include/mach/idle.h
deleted file mode 100644
index e9ddd706b16e..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/idle.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/idle.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 CPU Idle controls
11*/
12
13#ifndef __ASM_ARCH_IDLE_H
14#define __ASM_ARCH_IDLE_H __FILE__
15
16/* This allows the over-ride of the default idle code, in case there
17 * is any other things to be done over idle (like DVS)
18*/
19
20extern void (*s3c24xx_idle)(void);
21
22extern void s3c24xx_default_idle(void);
23
24#endif /* __ASM_ARCH_IDLE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h
deleted file mode 100644
index 118749f37c4c..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/io.h
+++ /dev/null
@@ -1,216 +0,0 @@
1/*
2 * arch/arm/mach-s3c2410/include/mach/io.h
3 * from arch/arm/mach-rpc/include/mach/io.h
4 *
5 * Copyright (C) 1997 Russell King
6 * (C) 2003 Simtec Electronics
7*/
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12#include <mach/hardware.h>
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16/*
17 * We use two different types of addressing - PC style addresses, and ARM
18 * addresses. PC style accesses the PC hardware with the normal PC IO
19 * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
20 * and are translated to the start of IO. Note that all addresses are
21 * not shifted left!
22 */
23
24#define __PORT_PCIO(x) ((x) < (1<<28))
25
26#define PCIO_BASE (S3C24XX_VA_ISA_WORD)
27#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
28#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
29#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
30/*
31 * Dynamic IO functions - let the compiler
32 * optimize the expressions
33 */
34
35#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
36static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
37{ \
38 unsigned long temp; \
39 __asm__ __volatile__( \
40 "cmp %2, #(1<<28)\n\t" \
41 "mov %0, %2\n\t" \
42 "addcc %0, %0, %3\n\t" \
43 "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
44 : "=&r" (temp) \
45 : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
46 : "cc"); \
47}
48
49
50#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
51static inline unsigned sz __in##fnsuffix (unsigned int port) \
52{ \
53 unsigned long temp, value; \
54 __asm__ __volatile__( \
55 "cmp %2, #(1<<28)\n\t" \
56 "mov %0, %2\n\t" \
57 "addcc %0, %0, %3\n\t" \
58 "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
59 : "=&r" (temp), "=r" (value) \
60 : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
61 : "cc"); \
62 return (unsigned sz)value; \
63}
64
65static inline void __iomem *__ioaddr (unsigned long port)
66{
67 return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
68}
69
70#define DECLARE_IO(sz,fnsuffix,instr) \
71 DECLARE_DYN_IN(sz,fnsuffix,instr) \
72 DECLARE_DYN_OUT(sz,fnsuffix,instr)
73
74DECLARE_IO(char,b,"b")
75DECLARE_IO(short,w,"h")
76DECLARE_IO(int,l,"")
77
78#undef DECLARE_IO
79#undef DECLARE_DYN_IN
80
81/*
82 * Constant address IO functions
83 *
84 * These have to be macros for the 'J' constraint to work -
85 * +/-4096 immediate operand.
86 */
87#define __outbc(value,port) \
88({ \
89 if (__PORT_PCIO((port))) \
90 __asm__ __volatile__( \
91 "strb %0, [%1, %2] @ outbc" \
92 : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
93 else \
94 __asm__ __volatile__( \
95 "strb %0, [%1, #0] @ outbc" \
96 : : "r" (value), "r" ((port))); \
97})
98
99#define __inbc(port) \
100({ \
101 unsigned char result; \
102 if (__PORT_PCIO((port))) \
103 __asm__ __volatile__( \
104 "ldrb %0, [%1, %2] @ inbc" \
105 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
106 else \
107 __asm__ __volatile__( \
108 "ldrb %0, [%1, #0] @ inbc" \
109 : "=r" (result) : "r" ((port))); \
110 result; \
111})
112
113#define __outwc(value,port) \
114({ \
115 unsigned long v = value; \
116 if (__PORT_PCIO((port))) { \
117 if ((port) < 256 && (port) > -256) \
118 __asm__ __volatile__( \
119 "strh %0, [%1, %2] @ outwc" \
120 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
121 else if ((port) > 0) \
122 __asm__ __volatile__( \
123 "strh %0, [%1, %2] @ outwc" \
124 : : "r" (v), \
125 "r" (PCIO_BASE + ((port) & ~0xff)), \
126 "Jr" (((port) & 0xff))); \
127 else \
128 __asm__ __volatile__( \
129 "strh %0, [%1, #0] @ outwc" \
130 : : "r" (v), \
131 "r" (PCIO_BASE + (port))); \
132 } else \
133 __asm__ __volatile__( \
134 "strh %0, [%1, #0] @ outwc" \
135 : : "r" (v), "r" ((port))); \
136})
137
138#define __inwc(port) \
139({ \
140 unsigned short result; \
141 if (__PORT_PCIO((port))) { \
142 if ((port) < 256 && (port) > -256 ) \
143 __asm__ __volatile__( \
144 "ldrh %0, [%1, %2] @ inwc" \
145 : "=r" (result) \
146 : "r" (PCIO_BASE), \
147 "Jr" ((port))); \
148 else if ((port) > 0) \
149 __asm__ __volatile__( \
150 "ldrh %0, [%1, %2] @ inwc" \
151 : "=r" (result) \
152 : "r" (PCIO_BASE + ((port) & ~0xff)), \
153 "Jr" (((port) & 0xff))); \
154 else \
155 __asm__ __volatile__( \
156 "ldrh %0, [%1, #0] @ inwc" \
157 : "=r" (result) \
158 : "r" (PCIO_BASE + ((port)))); \
159 } else \
160 __asm__ __volatile__( \
161 "ldrh %0, [%1, #0] @ inwc" \
162 : "=r" (result) : "r" ((port))); \
163 result; \
164})
165
166#define __outlc(value,port) \
167({ \
168 unsigned long v = value; \
169 if (__PORT_PCIO((port))) \
170 __asm__ __volatile__( \
171 "str %0, [%1, %2] @ outlc" \
172 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
173 else \
174 __asm__ __volatile__( \
175 "str %0, [%1, #0] @ outlc" \
176 : : "r" (v), "r" ((port))); \
177})
178
179#define __inlc(port) \
180({ \
181 unsigned long result; \
182 if (__PORT_PCIO((port))) \
183 __asm__ __volatile__( \
184 "ldr %0, [%1, %2] @ inlc" \
185 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
186 else \
187 __asm__ __volatile__( \
188 "ldr %0, [%1, #0] @ inlc" \
189 : "=r" (result) : "r" ((port))); \
190 result; \
191})
192
193#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
194
195#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
196#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
197#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
198#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
199#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
200#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
201#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
202
203#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
204#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
205#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
206
207#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
208#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
209#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
210
211/*
212 * 1:1 mapping for ioremapped regions.
213 */
214#define __mem_pci(x) (x)
215
216#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
deleted file mode 100644
index e53b2177319e..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/irqs.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef __ASM_ARCH_IRQS_H
13#define __ASM_ARCH_IRQS_H __FILE__
14
15/* we keep the first set of CPU IRQs out of the range of
16 * the ISA space, so that the PC104 has them to itself
17 * and we don't end up having to do horrible things to the
18 * standard ISA drivers....
19 */
20
21#define S3C2410_CPUIRQ_OFFSET (16)
22
23#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
24
25/* main cpu interrupts */
26#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
27#define IRQ_EINT1 S3C2410_IRQ(1)
28#define IRQ_EINT2 S3C2410_IRQ(2)
29#define IRQ_EINT3 S3C2410_IRQ(3)
30#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
31#define IRQ_EINT8t23 S3C2410_IRQ(5)
32#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
33#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
34#define IRQ_BATT_FLT S3C2410_IRQ(7)
35#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
36#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
37#define IRQ_TIMER0 S3C2410_IRQ(10)
38#define IRQ_TIMER1 S3C2410_IRQ(11)
39#define IRQ_TIMER2 S3C2410_IRQ(12)
40#define IRQ_TIMER3 S3C2410_IRQ(13)
41#define IRQ_TIMER4 S3C2410_IRQ(14)
42#define IRQ_UART2 S3C2410_IRQ(15)
43#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
44#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
45#define IRQ_DMA1 S3C2410_IRQ(18)
46#define IRQ_DMA2 S3C2410_IRQ(19)
47#define IRQ_DMA3 S3C2410_IRQ(20)
48#define IRQ_SDI S3C2410_IRQ(21)
49#define IRQ_SPI0 S3C2410_IRQ(22)
50#define IRQ_UART1 S3C2410_IRQ(23)
51#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
52#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
53#define IRQ_USBD S3C2410_IRQ(25)
54#define IRQ_USBH S3C2410_IRQ(26)
55#define IRQ_IIC S3C2410_IRQ(27)
56#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
57#define IRQ_SPI1 S3C2410_IRQ(29)
58#define IRQ_RTC S3C2410_IRQ(30)
59#define IRQ_ADCPARENT S3C2410_IRQ(31)
60
61/* interrupts generated from the external interrupts sources */
62#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
63#define IRQ_EINT5 S3C2410_IRQ(33)
64#define IRQ_EINT6 S3C2410_IRQ(34)
65#define IRQ_EINT7 S3C2410_IRQ(35)
66#define IRQ_EINT8 S3C2410_IRQ(36)
67#define IRQ_EINT9 S3C2410_IRQ(37)
68#define IRQ_EINT10 S3C2410_IRQ(38)
69#define IRQ_EINT11 S3C2410_IRQ(39)
70#define IRQ_EINT12 S3C2410_IRQ(40)
71#define IRQ_EINT13 S3C2410_IRQ(41)
72#define IRQ_EINT14 S3C2410_IRQ(42)
73#define IRQ_EINT15 S3C2410_IRQ(43)
74#define IRQ_EINT16 S3C2410_IRQ(44)
75#define IRQ_EINT17 S3C2410_IRQ(45)
76#define IRQ_EINT18 S3C2410_IRQ(46)
77#define IRQ_EINT19 S3C2410_IRQ(47)
78#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
79#define IRQ_EINT21 S3C2410_IRQ(49)
80#define IRQ_EINT22 S3C2410_IRQ(50)
81#define IRQ_EINT23 S3C2410_IRQ(51)
82
83#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
84#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
85
86#define IRQ_LCD_FIFO S3C2410_IRQ(52)
87#define IRQ_LCD_FRAME S3C2410_IRQ(53)
88
89/* IRQs for the interal UARTs, and ADC
90 * these need to be ordered in number of appearance in the
91 * SUBSRC mask register
92*/
93
94#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54)
95
96#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */
97#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
98#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
99
100#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */
101#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
102#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
103
104#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */
105#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
106#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
107
108#define IRQ_TC S3C2410_IRQSUB(9)
109#define IRQ_ADC S3C2410_IRQSUB(10)
110
111/* extra irqs for s3c2412 */
112
113#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
114
115#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
116#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
117
118
119#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
120#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
121#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
122#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
123#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
124
125#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
126#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
127#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
128#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
129#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
130#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
131#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
132#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
133#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
134#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
135#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
136
137
138/* extra irqs for s3c2440 */
139
140#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
141#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
142#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
143#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
144
145/* irqs for s3c2443 */
146
147#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
148#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
149#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
150#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
151#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
152
153#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
154
155#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
156#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
157
158#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
159#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
160#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
161#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
162
163#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
164#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
165#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
166#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
167#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
168#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
169
170/* UART3 */
171#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
172#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
173#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
174
175#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
176#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
177
178#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
179#define NR_IRQS (IRQ_S3C2443_AC97+1)
180#else
181#define NR_IRQS (IRQ_S3C2440_AC97+1)
182#endif
183
184/* compatibility define. */
185#define IRQ_UART3 IRQ_S3C2443_UART3
186#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
187#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
188#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
189
190#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
191#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
192
193#ifdef CONFIG_CPU_S3C2440
194#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
195#else
196#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
197#endif
198
199/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
200#define FIQ_START IRQ_EINT0
201
202#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c2410/include/mach/leds-gpio.h
deleted file mode 100644
index d8a7672519b6..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/leds-gpio.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX - LEDs GPIO connector
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_LEDSGPIO_H
15#define __ASM_ARCH_LEDSGPIO_H "leds-gpio.h"
16
17#define S3C24XX_LEDF_ACTLOW (1<<0) /* LED is on when GPIO low */
18#define S3C24XX_LEDF_TRISTATE (1<<1) /* tristate to turn off */
19
20struct s3c24xx_led_platdata {
21 unsigned int gpio;
22 unsigned int flags;
23
24 char *name;
25 char *def_trigger;
26};
27
28#endif /* __ASM_ARCH_LEDSGPIO_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
deleted file mode 100644
index 78ae807f1281..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ /dev/null
@@ -1,165 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/map.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H
15
16#include <plat/map-base.h>
17
18/*
19 * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x4000)
23
24#include <plat/map-s3c.h>
25
26/*
27 * interrupt controller is the first thing we put in, to make
28 * the assembly code for the irq detection easier
29 */
30#define S3C2410_PA_IRQ (0x4A000000)
31#define S3C24XX_SZ_IRQ SZ_1M
32
33/* memory controller registers */
34#define S3C2410_PA_MEMCTRL (0x48000000)
35#define S3C24XX_SZ_MEMCTRL SZ_1M
36
37/* UARTs */
38#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
39
40/* Timers */
41#define S3C2410_PA_TIMER (0x51000000)
42#define S3C24XX_SZ_TIMER SZ_1M
43
44/* Clock and Power management */
45#define S3C24XX_SZ_CLKPWR SZ_1M
46
47/* USB Device port */
48#define S3C2410_PA_USBDEV (0x52000000)
49#define S3C24XX_SZ_USBDEV SZ_1M
50
51/* Watchdog */
52#define S3C2410_PA_WATCHDOG (0x53000000)
53#define S3C24XX_SZ_WATCHDOG SZ_1M
54
55/* Standard size definitions for peripheral blocks. */
56
57#define S3C24XX_SZ_UART SZ_1M
58#define S3C24XX_SZ_IIS SZ_1M
59#define S3C24XX_SZ_ADC SZ_1M
60#define S3C24XX_SZ_SPI SZ_1M
61#define S3C24XX_SZ_SDI SZ_1M
62#define S3C24XX_SZ_NAND SZ_1M
63#define S3C24XX_SZ_GPIO SZ_1M
64
65/* USB host controller */
66#define S3C2410_PA_USBHOST (0x49000000)
67
68/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
69#define S3C2416_PA_HSUDC (0x49800000)
70#define S3C2416_SZ_HSUDC (SZ_4K)
71
72/* DMA controller */
73#define S3C2410_PA_DMA (0x4B000000)
74#define S3C24XX_SZ_DMA SZ_1M
75
76/* Clock and Power management */
77#define S3C2410_PA_CLKPWR (0x4C000000)
78
79/* LCD controller */
80#define S3C2410_PA_LCD (0x4D000000)
81#define S3C24XX_SZ_LCD SZ_1M
82
83/* NAND flash controller */
84#define S3C2410_PA_NAND (0x4E000000)
85
86/* IIC hardware controller */
87#define S3C2410_PA_IIC (0x54000000)
88
89/* IIS controller */
90#define S3C2410_PA_IIS (0x55000000)
91
92/* RTC */
93#define S3C2410_PA_RTC (0x57000000)
94#define S3C24XX_SZ_RTC SZ_1M
95
96/* ADC */
97#define S3C2410_PA_ADC (0x58000000)
98
99/* SPI */
100#define S3C2410_PA_SPI (0x59000000)
101
102/* SDI */
103#define S3C2410_PA_SDI (0x5A000000)
104
105/* CAMIF */
106#define S3C2440_PA_CAMIF (0x4F000000)
107#define S3C2440_SZ_CAMIF SZ_1M
108
109/* AC97 */
110
111#define S3C2440_PA_AC97 (0x5B000000)
112#define S3C2440_SZ_AC97 SZ_1M
113
114/* S3C2443/S3C2416 High-speed SD/MMC */
115#define S3C2443_PA_HSMMC (0x4A800000)
116#define S3C2416_PA_HSMMC0 (0x4AC00000)
117
118#define S3C2443_PA_FB (0x4C800000)
119
120/* S3C2412 memory and IO controls */
121#define S3C2412_PA_SSMC (0x4F000000)
122
123#define S3C2412_PA_EBI (0x48800000)
124
125/* physical addresses of all the chip-select areas */
126
127#define S3C2410_CS0 (0x00000000)
128#define S3C2410_CS1 (0x08000000)
129#define S3C2410_CS2 (0x10000000)
130#define S3C2410_CS3 (0x18000000)
131#define S3C2410_CS4 (0x20000000)
132#define S3C2410_CS5 (0x28000000)
133#define S3C2410_CS6 (0x30000000)
134#define S3C2410_CS7 (0x38000000)
135
136#define S3C2410_SDRAM_PA (S3C2410_CS6)
137
138/* Use a single interface for common resources between S3C24XX cpus */
139
140#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
141#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
142#define S3C24XX_PA_DMA S3C2410_PA_DMA
143#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
144#define S3C24XX_PA_LCD S3C2410_PA_LCD
145#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
146#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
147#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
148#define S3C24XX_PA_IIS S3C2410_PA_IIS
149#define S3C24XX_PA_RTC S3C2410_PA_RTC
150#define S3C24XX_PA_ADC S3C2410_PA_ADC
151#define S3C24XX_PA_SPI S3C2410_PA_SPI
152#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1)
153#define S3C24XX_PA_SDI S3C2410_PA_SDI
154#define S3C24XX_PA_NAND S3C2410_PA_NAND
155
156#define S3C_PA_FB S3C2443_PA_FB
157#define S3C_PA_IIC S3C2410_PA_IIC
158#define S3C_PA_UART S3C24XX_PA_UART
159#define S3C_PA_USBHOST S3C2410_PA_USBHOST
160#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
161#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
162#define S3C_PA_WDT S3C2410_PA_WATCHDOG
163#define S3C_PA_NAND S3C24XX_PA_NAND
164
165#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
deleted file mode 100644
index e9e36b0abbac..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
2 *
3 * Copyright 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * OSIRIS - CPLD control constants
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_OSIRISCPLD_H
15#define __ASM_ARCH_OSIRISCPLD_H
16
17/* CTRL0 - NAND WP control */
18
19#define OSIRIS_CTRL0_NANDSEL (0x3)
20#define OSIRIS_CTRL0_BOOT_INT (1<<3)
21#define OSIRIS_CTRL0_PCMCIA (1<<4)
22#define OSIRIS_CTRL0_FIX8 (1<<5)
23#define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6)
24#define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7)
25
26#define OSIRIS_CTRL1_FIX8 (1<<0)
27
28#define OSIRIS_ID_REVMASK (0x7)
29
30#endif /* __ASM_ARCH_OSIRISCPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
deleted file mode 100644
index 17380f848428..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/osiris-map.h
2 *
3 * Copyright 2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * OSIRIS - Memory map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* needs arch/map.h including with this */
15
16#ifndef __ASM_ARCH_OSIRISMAP_H
17#define __ASM_ARCH_OSIRISMAP_H
18
19/* start peripherals off after the S3C2410 */
20
21#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000))
22
23#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26))
24
25/* we put the CPLD registers next, to get them out of the way */
26
27#define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000)
28#define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD)
29
30#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000)
31#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23))
32
33#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000)
34#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23))
35
36#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000)
37#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
38
39#define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000)
40#define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23))
41
42#endif /* __ASM_ARCH_OSIRISMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c2410/include/mach/otom-map.h
deleted file mode 100644
index f9277a52c145..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/otom-map.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/otom-map.h
2 *
3 * (c) 2005 Guillaume GOURAT / NexVision
4 * guillaume.gourat@nexvision.fr
5 *
6 * NexVision OTOM board memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x01300000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space.
18 */
19
20#ifndef __ASM_ARCH_OTOMMAP_H
21#define __ASM_ARCH_OTOMMAP_H
22
23#define OTOM_PA_CS8900A_BASE (S3C2410_CS3 + 0x01000000) /* nGCS3 +0x01000000 */
24#define OTOM_VA_CS8900A_BASE S3C2410_ADDR(0x04000000) /* 0xF4000000 */
25
26/* physical offset addresses for the peripherals */
27
28#define OTOM_PA_FLASH0_BASE (S3C2410_CS0) /* Bank 0 */
29
30#endif /* __ASM_ARCH_OTOMMAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h
deleted file mode 100644
index 2eef7e6f7675..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/include/pm-core.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14static inline void s3c_pm_debug_init_uart(void)
15{
16 unsigned long tmp = __raw_readl(S3C2410_CLKCON);
17
18 /* re-start uart clocks */
19 tmp |= S3C2410_CLKCON_UART0;
20 tmp |= S3C2410_CLKCON_UART1;
21 tmp |= S3C2410_CLKCON_UART2;
22
23 __raw_writel(tmp, S3C2410_CLKCON);
24 udelay(10);
25}
26
27static inline void s3c_pm_arch_prepare_irqs(void)
28{
29 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
30 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
31
32 /* ack any outstanding external interrupts before we go to sleep */
33
34 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
35 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
36 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
37
38}
39
40static inline void s3c_pm_arch_stop_clocks(void)
41{
42 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
43}
44
45static void s3c_pm_show_resume_irqs(int start, unsigned long which,
46 unsigned long mask);
47
48static inline void s3c_pm_arch_show_resume_irqs(void)
49{
50 S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
51 __raw_readl(S3C2410_SRCPND),
52 __raw_readl(S3C2410_EINTPEND));
53
54 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
55 s3c_irqwake_intmask);
56
57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
58 s3c_irqwake_eintmask);
59}
60
61static inline void s3c_pm_arch_update_uart(void __iomem *regs,
62 struct pm_uart_save *save)
63{
64}
65
66static inline void s3c_pm_restored_gpios(void) { }
67static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
deleted file mode 100644
index 3415b60082d7..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_CLOCK
14#define __ASM_ARM_REGS_CLOCK
15
16#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
19
20#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
21#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
22#define S3C2410_UPLLCON S3C2410_CLKREG(0x08)
23#define S3C2410_CLKCON S3C2410_CLKREG(0x0C)
24#define S3C2410_CLKSLOW S3C2410_CLKREG(0x10)
25#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
26
27#define S3C2410_CLKCON_IDLE (1<<2)
28#define S3C2410_CLKCON_POWER (1<<3)
29#define S3C2410_CLKCON_NAND (1<<4)
30#define S3C2410_CLKCON_LCDC (1<<5)
31#define S3C2410_CLKCON_USBH (1<<6)
32#define S3C2410_CLKCON_USBD (1<<7)
33#define S3C2410_CLKCON_PWMT (1<<8)
34#define S3C2410_CLKCON_SDI (1<<9)
35#define S3C2410_CLKCON_UART0 (1<<10)
36#define S3C2410_CLKCON_UART1 (1<<11)
37#define S3C2410_CLKCON_UART2 (1<<12)
38#define S3C2410_CLKCON_GPIO (1<<13)
39#define S3C2410_CLKCON_RTC (1<<14)
40#define S3C2410_CLKCON_ADC (1<<15)
41#define S3C2410_CLKCON_IIC (1<<16)
42#define S3C2410_CLKCON_IIS (1<<17)
43#define S3C2410_CLKCON_SPI (1<<18)
44
45/* DCLKCON register addresses in gpio.h */
46
47#define S3C2410_DCLKCON_DCLK0EN (1<<0)
48#define S3C2410_DCLKCON_DCLK0_PCLK (0<<1)
49#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
50#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
51#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
52#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
53#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
54
55#define S3C2410_DCLKCON_DCLK1EN (1<<16)
56#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
57#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
58#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
59#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
60#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
61#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
62
63#define S3C2410_CLKDIVN_PDIVN (1<<0)
64#define S3C2410_CLKDIVN_HDIVN (1<<1)
65
66#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
67#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
68#define S3C2410_CLKSLOW_SLOW (1<<4)
69#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
70#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
71
72#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
73
74/* extra registers */
75#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
76
77#define S3C2440_CLKCON_CAMERA (1<<19)
78#define S3C2440_CLKCON_AC97 (1<<20)
79
80#define S3C2440_CLKDIVN_PDIVN (1<<0)
81#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
82#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
83#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
84#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
85#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
86#define S3C2440_CLKDIVN_UCLK (1<<3)
87
88#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
89#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
90#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
91#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
92#define S3C2440_CAMDIVN_DVSEN (1<<12)
93
94#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
95
96#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
97
98#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
99
100#define S3C2412_OSCSET S3C2410_CLKREG(0x18)
101#define S3C2412_CLKSRC S3C2410_CLKREG(0x1C)
102
103#define S3C2412_PLLCON_OFF (1<<20)
104
105#define S3C2412_CLKDIVN_PDIVN (1<<2)
106#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
107#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
108#define S3C2412_CLKDIVN_DVSEN (1<<4)
109#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
110#define S3C2412_CLKDIVN_USB48DIV (1<<6)
111#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
112#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
113#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
114#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
115#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
116#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
117
118#define S3C2412_CLKCON_WDT (1<<28)
119#define S3C2412_CLKCON_SPI (1<<27)
120#define S3C2412_CLKCON_IIS (1<<26)
121#define S3C2412_CLKCON_IIC (1<<25)
122#define S3C2412_CLKCON_ADC (1<<24)
123#define S3C2412_CLKCON_RTC (1<<23)
124#define S3C2412_CLKCON_GPIO (1<<22)
125#define S3C2412_CLKCON_UART2 (1<<21)
126#define S3C2412_CLKCON_UART1 (1<<20)
127#define S3C2412_CLKCON_UART0 (1<<19)
128#define S3C2412_CLKCON_SDI (1<<18)
129#define S3C2412_CLKCON_PWMT (1<<17)
130#define S3C2412_CLKCON_USBD (1<<16)
131#define S3C2412_CLKCON_CAMCLK (1<<15)
132#define S3C2412_CLKCON_UARTCLK (1<<14)
133/* missing 13 */
134#define S3C2412_CLKCON_USB_HOST48 (1<<12)
135#define S3C2412_CLKCON_USB_DEV48 (1<<11)
136#define S3C2412_CLKCON_HCLKdiv2 (1<<10)
137#define S3C2412_CLKCON_HCLKx2 (1<<9)
138#define S3C2412_CLKCON_SDRAM (1<<8)
139/* missing 7 */
140#define S3C2412_CLKCON_USBH S3C2410_CLKCON_USBH
141#define S3C2412_CLKCON_LCDC S3C2410_CLKCON_LCDC
142#define S3C2412_CLKCON_NAND S3C2410_CLKCON_NAND
143#define S3C2412_CLKCON_DMA3 (1<<3)
144#define S3C2412_CLKCON_DMA2 (1<<2)
145#define S3C2412_CLKCON_DMA1 (1<<1)
146#define S3C2412_CLKCON_DMA0 (1<<0)
147
148/* clock sourec controls */
149
150#define S3C2412_CLKSRC_EXTCLKDIV_MASK (7 << 0)
151#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT (0)
152#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV (1<<3)
153#define S3C2412_CLKSRC_MSYSCLK_MPLL (1<<4)
154#define S3C2412_CLKSRC_USYSCLK_UPLL (1<<5)
155#define S3C2412_CLKSRC_UARTCLK_MPLL (1<<8)
156#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
157#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
158#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
159#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
160#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
161
162#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
163
164#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
165
166#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
deleted file mode 100644
index 98fd4a05587c..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440/S3C2412 Signal Drive Strength Control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_DSC_H
15#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
16
17#if defined(CONFIG_CPU_S3C2412)
18#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
19#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
20#endif
21
22#if defined(CONFIG_CPU_S3C2416)
23#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
24#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
25#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
26#define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
27
28#define S3C2416_SELECT_DSC0 (0 << 30)
29#define S3C2416_SELECT_DSC1 (1 << 30)
30#define S3C2416_SELECT_DSC2 (2 << 30)
31#define S3C2416_SELECT_DSC3 (3 << 30)
32
33#define S3C2416_DSC_GETSHIFT(x) (x & 30)
34
35#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
36#define S3C2416_DSC0_CF_5mA (0 << 28)
37#define S3C2416_DSC0_CF_10mA (1 << 28)
38#define S3C2416_DSC0_CF_15mA (2 << 28)
39#define S3C2416_DSC0_CF_21mA (3 << 28)
40#define S3C2416_DSC0_CF_MASK (3 << 28)
41
42#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
43#define S3C2416_DSC0_nRBE_5mA (0 << 26)
44#define S3C2416_DSC0_nRBE_10mA (1 << 26)
45#define S3C2416_DSC0_nRBE_15mA (2 << 26)
46#define S3C2416_DSC0_nRBE_21mA (3 << 26)
47#define S3C2416_DSC0_nRBE_MASK (3 << 26)
48
49#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
50#define S3C2416_DSC0_nROE_5mA (0 << 24)
51#define S3C2416_DSC0_nROE_10mA (1 << 24)
52#define S3C2416_DSC0_nROE_15mA (2 << 24)
53#define S3C2416_DSC0_nROE_21mA (3 << 24)
54#define S3C2416_DSC0_nROE_MASK (3 << 24)
55
56#endif
57
58#if defined(CONFIG_CPU_S3C244X)
59
60#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
61#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
62
63#define S3C2440_SELECT_DSC0 (0)
64#define S3C2440_SELECT_DSC1 (1<<31)
65
66#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
67
68#define S3C2440_DSC0_DISABLE (1<<31)
69
70#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8)
71#define S3C2440_DSC0_ADDR_12mA (0<<8)
72#define S3C2440_DSC0_ADDR_10mA (1<<8)
73#define S3C2440_DSC0_ADDR_8mA (2<<8)
74#define S3C2440_DSC0_ADDR_6mA (3<<8)
75#define S3C2440_DSC0_ADDR_MASK (3<<8)
76
77/* D24..D31 */
78#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6)
79#define S3C2440_DSC0_DATA3_12mA (0<<6)
80#define S3C2440_DSC0_DATA3_10mA (1<<6)
81#define S3C2440_DSC0_DATA3_8mA (2<<6)
82#define S3C2440_DSC0_DATA3_6mA (3<<6)
83#define S3C2440_DSC0_DATA3_MASK (3<<6)
84
85/* D16..D23 */
86#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4)
87#define S3C2440_DSC0_DATA2_12mA (0<<4)
88#define S3C2440_DSC0_DATA2_10mA (1<<4)
89#define S3C2440_DSC0_DATA2_8mA (2<<4)
90#define S3C2440_DSC0_DATA2_6mA (3<<4)
91#define S3C2440_DSC0_DATA2_MASK (3<<4)
92
93/* D8..D15 */
94#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2)
95#define S3C2440_DSC0_DATA1_12mA (0<<2)
96#define S3C2440_DSC0_DATA1_10mA (1<<2)
97#define S3C2440_DSC0_DATA1_8mA (2<<2)
98#define S3C2440_DSC0_DATA1_6mA (3<<2)
99#define S3C2440_DSC0_DATA1_MASK (3<<2)
100
101/* D0..D7 */
102#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0)
103#define S3C2440_DSC0_DATA0_12mA (0<<0)
104#define S3C2440_DSC0_DATA0_10mA (1<<0)
105#define S3C2440_DSC0_DATA0_8mA (2<<0)
106#define S3C2440_DSC0_DATA0_6mA (3<<0)
107#define S3C2440_DSC0_DATA0_MASK (3<<0)
108
109#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28)
110#define S3C2440_DSC1_SCK1_12mA (0<<28)
111#define S3C2440_DSC1_SCK1_10mA (1<<28)
112#define S3C2440_DSC1_SCK1_8mA (2<<28)
113#define S3C2440_DSC1_SCK1_6mA (3<<28)
114#define S3C2440_DSC1_SCK1_MASK (3<<28)
115
116#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26)
117#define S3C2440_DSC1_SCK0_12mA (0<<26)
118#define S3C2440_DSC1_SCK0_10mA (1<<26)
119#define S3C2440_DSC1_SCK0_8mA (2<<26)
120#define S3C2440_DSC1_SCK0_6mA (3<<26)
121#define S3C2440_DSC1_SCK0_MASK (3<<26)
122
123#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24)
124#define S3C2440_DSC1_SCKE_10mA (0<<24)
125#define S3C2440_DSC1_SCKE_8mA (1<<24)
126#define S3C2440_DSC1_SCKE_6mA (2<<24)
127#define S3C2440_DSC1_SCKE_4mA (3<<24)
128#define S3C2440_DSC1_SCKE_MASK (3<<24)
129
130/* SDRAM nRAS/nCAS */
131#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22)
132#define S3C2440_DSC1_SDR_10mA (0<<22)
133#define S3C2440_DSC1_SDR_8mA (1<<22)
134#define S3C2440_DSC1_SDR_6mA (2<<22)
135#define S3C2440_DSC1_SDR_4mA (3<<22)
136#define S3C2440_DSC1_SDR_MASK (3<<22)
137
138/* NAND Flash Controller */
139#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20)
140#define S3C2440_DSC1_NFC_10mA (0<<20)
141#define S3C2440_DSC1_NFC_8mA (1<<20)
142#define S3C2440_DSC1_NFC_6mA (2<<20)
143#define S3C2440_DSC1_NFC_4mA (3<<20)
144#define S3C2440_DSC1_NFC_MASK (3<<20)
145
146/* nBE[0..3] */
147#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18)
148#define S3C2440_DSC1_nBE_10mA (0<<18)
149#define S3C2440_DSC1_nBE_8mA (1<<18)
150#define S3C2440_DSC1_nBE_6mA (2<<18)
151#define S3C2440_DSC1_nBE_4mA (3<<18)
152#define S3C2440_DSC1_nBE_MASK (3<<18)
153
154#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16)
155#define S3C2440_DSC1_WOE_10mA (0<<16)
156#define S3C2440_DSC1_WOE_8mA (1<<16)
157#define S3C2440_DSC1_WOE_6mA (2<<16)
158#define S3C2440_DSC1_WOE_4mA (3<<16)
159#define S3C2440_DSC1_WOE_MASK (3<<16)
160
161#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14)
162#define S3C2440_DSC1_CS7_10mA (0<<14)
163#define S3C2440_DSC1_CS7_8mA (1<<14)
164#define S3C2440_DSC1_CS7_6mA (2<<14)
165#define S3C2440_DSC1_CS7_4mA (3<<14)
166#define S3C2440_DSC1_CS7_MASK (3<<14)
167
168#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12)
169#define S3C2440_DSC1_CS6_10mA (0<<12)
170#define S3C2440_DSC1_CS6_8mA (1<<12)
171#define S3C2440_DSC1_CS6_6mA (2<<12)
172#define S3C2440_DSC1_CS6_4mA (3<<12)
173#define S3C2440_DSC1_CS6_MASK (3<<12)
174
175#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10)
176#define S3C2440_DSC1_CS5_10mA (0<<10)
177#define S3C2440_DSC1_CS5_8mA (1<<10)
178#define S3C2440_DSC1_CS5_6mA (2<<10)
179#define S3C2440_DSC1_CS5_4mA (3<<10)
180#define S3C2440_DSC1_CS5_MASK (3<<10)
181
182#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8)
183#define S3C2440_DSC1_CS4_10mA (0<<8)
184#define S3C2440_DSC1_CS4_8mA (1<<8)
185#define S3C2440_DSC1_CS4_6mA (2<<8)
186#define S3C2440_DSC1_CS4_4mA (3<<8)
187#define S3C2440_DSC1_CS4_MASK (3<<8)
188
189#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6)
190#define S3C2440_DSC1_CS3_10mA (0<<6)
191#define S3C2440_DSC1_CS3_8mA (1<<6)
192#define S3C2440_DSC1_CS3_6mA (2<<6)
193#define S3C2440_DSC1_CS3_4mA (3<<6)
194#define S3C2440_DSC1_CS3_MASK (3<<6)
195
196#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4)
197#define S3C2440_DSC1_CS2_10mA (0<<4)
198#define S3C2440_DSC1_CS2_8mA (1<<4)
199#define S3C2440_DSC1_CS2_6mA (2<<4)
200#define S3C2440_DSC1_CS2_4mA (3<<4)
201#define S3C2440_DSC1_CS2_MASK (3<<4)
202
203#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2)
204#define S3C2440_DSC1_CS1_10mA (0<<2)
205#define S3C2440_DSC1_CS1_8mA (1<<2)
206#define S3C2440_DSC1_CS1_6mA (2<<2)
207#define S3C2440_DSC1_CS1_4mA (3<<2)
208#define S3C2440_DSC1_CS1_MASK (3<<2)
209
210#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0)
211#define S3C2440_DSC1_CS0_10mA (0<<0)
212#define S3C2440_DSC1_CS0_8mA (1<<0)
213#define S3C2440_DSC1_CS0_6mA (2<<0)
214#define S3C2440_DSC1_CS0_4mA (3<<0)
215#define S3C2440_DSC1_CS0_MASK (3<<0)
216
217#endif /* CONFIG_CPU_S3C2440 */
218
219#endif /* __ASM_ARCH_REGS_DSC_H */
220
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
deleted file mode 100644
index cac1ad6b582c..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,602 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 GPIO register definitions
11*/
12
13
14#ifndef __ASM_ARCH_REGS_GPIO_H
15#define __ASM_ARCH_REGS_GPIO_H
16
17#include <mach/gpio-nrs.h>
18
19#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
20
21/* general configuration options */
22
23#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
24#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */
25#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
26#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
27#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */
28#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
29
30/* register address for the GPIO registers.
31 * S3C24XX_GPIOREG2 is for the second set of registers in the
32 * GPIO which move between s3c2410 and s3c2412 type systems */
33
34#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
35#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
36
37
38/* configure GPIO ports A..G */
39
40/* port A - S3C2410: 22bits, zero in bit X makes pin X output
41 * 1 makes port special function, this is default
42*/
43#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
44#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
45
46#define S3C2410_GPA0_ADDR0 (1<<0)
47#define S3C2410_GPA1_ADDR16 (1<<1)
48#define S3C2410_GPA2_ADDR17 (1<<2)
49#define S3C2410_GPA3_ADDR18 (1<<3)
50#define S3C2410_GPA4_ADDR19 (1<<4)
51#define S3C2410_GPA5_ADDR20 (1<<5)
52#define S3C2410_GPA6_ADDR21 (1<<6)
53#define S3C2410_GPA7_ADDR22 (1<<7)
54#define S3C2410_GPA8_ADDR23 (1<<8)
55#define S3C2410_GPA9_ADDR24 (1<<9)
56#define S3C2410_GPA10_ADDR25 (1<<10)
57#define S3C2410_GPA11_ADDR26 (1<<11)
58#define S3C2410_GPA12_nGCS1 (1<<12)
59#define S3C2410_GPA13_nGCS2 (1<<13)
60#define S3C2410_GPA14_nGCS3 (1<<14)
61#define S3C2410_GPA15_nGCS4 (1<<15)
62#define S3C2410_GPA16_nGCS5 (1<<16)
63#define S3C2410_GPA17_CLE (1<<17)
64#define S3C2410_GPA18_ALE (1<<18)
65#define S3C2410_GPA19_nFWE (1<<19)
66#define S3C2410_GPA20_nFRE (1<<20)
67#define S3C2410_GPA21_nRSTOUT (1<<21)
68#define S3C2410_GPA22_nFCE (1<<22)
69
70/* 0x08 and 0x0c are reserved on S3C2410 */
71
72/* S3C2410:
73 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
74 * 00 = input, 01 = output, 10=special function, 11=reserved
75
76 * bit 0,1 = pin 0, 2,3= pin 1...
77 *
78 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
79*/
80
81#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
82#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
83#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
84
85/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
86
87#define S3C2410_GPB0_TOUT0 (0x02 << 0)
88
89#define S3C2410_GPB1_TOUT1 (0x02 << 2)
90
91#define S3C2410_GPB2_TOUT2 (0x02 << 4)
92
93#define S3C2410_GPB3_TOUT3 (0x02 << 6)
94
95#define S3C2410_GPB4_TCLK0 (0x02 << 8)
96#define S3C2410_GPB4_MASK (0x03 << 8)
97
98#define S3C2410_GPB5_nXBACK (0x02 << 10)
99#define S3C2443_GPB5_XBACK (0x03 << 10)
100
101#define S3C2410_GPB6_nXBREQ (0x02 << 12)
102#define S3C2443_GPB6_XBREQ (0x03 << 12)
103
104#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
105#define S3C2443_GPB7_XDACK1 (0x03 << 14)
106
107#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
108
109#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
110#define S3C2443_GPB9_XDACK0 (0x03 << 18)
111
112#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
113#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
114
115#define S3C2410_GPB_PUPDIS(x) (1<<(x))
116
117/* Port C consits of 16 GPIO/Special function
118 *
119 * almost identical setup to port b, but the special functions are mostly
120 * to do with the video system's sync/etc.
121*/
122
123#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
124#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
125#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
126#define S3C2410_GPC0_LEND (0x02 << 0)
127#define S3C2410_GPC1_VCLK (0x02 << 2)
128#define S3C2410_GPC2_VLINE (0x02 << 4)
129#define S3C2410_GPC3_VFRAME (0x02 << 6)
130#define S3C2410_GPC4_VM (0x02 << 8)
131#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
132#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
133#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
134#define S3C2410_GPC8_VD0 (0x02 << 16)
135#define S3C2410_GPC9_VD1 (0x02 << 18)
136#define S3C2410_GPC10_VD2 (0x02 << 20)
137#define S3C2410_GPC11_VD3 (0x02 << 22)
138#define S3C2410_GPC12_VD4 (0x02 << 24)
139#define S3C2410_GPC13_VD5 (0x02 << 26)
140#define S3C2410_GPC14_VD6 (0x02 << 28)
141#define S3C2410_GPC15_VD7 (0x02 << 30)
142#define S3C2410_GPC_PUPDIS(x) (1<<(x))
143
144/*
145 * S3C2410: Port D consists of 16 GPIO/Special function
146 *
147 * almost identical setup to port b, but the special functions are mostly
148 * to do with the video system's data.
149 *
150 * almost identical setup to port c
151*/
152
153#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
154#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
155#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
156
157#define S3C2410_GPD0_VD8 (0x02 << 0)
158#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
159
160#define S3C2410_GPD1_VD9 (0x02 << 2)
161#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
162
163#define S3C2410_GPD2_VD10 (0x02 << 4)
164
165#define S3C2410_GPD3_VD11 (0x02 << 6)
166
167#define S3C2410_GPD4_VD12 (0x02 << 8)
168
169#define S3C2410_GPD5_VD13 (0x02 << 10)
170
171#define S3C2410_GPD6_VD14 (0x02 << 12)
172
173#define S3C2410_GPD7_VD15 (0x02 << 14)
174
175#define S3C2410_GPD8_VD16 (0x02 << 16)
176#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
177
178#define S3C2410_GPD9_VD17 (0x02 << 18)
179#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
180
181#define S3C2410_GPD10_VD18 (0x02 << 20)
182#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
183
184#define S3C2410_GPD11_VD19 (0x02 << 22)
185
186#define S3C2410_GPD12_VD20 (0x02 << 24)
187
188#define S3C2410_GPD13_VD21 (0x02 << 26)
189
190#define S3C2410_GPD14_VD22 (0x02 << 28)
191#define S3C2410_GPD14_nSS1 (0x03 << 28)
192
193#define S3C2410_GPD15_VD23 (0x02 << 30)
194#define S3C2410_GPD15_nSS0 (0x03 << 30)
195
196#define S3C2410_GPD_PUPDIS(x) (1<<(x))
197
198/* S3C2410:
199 * Port E consists of 16 GPIO/Special function
200 *
201 * again, the same as port B, but dealing with I2S, SDI, and
202 * more miscellaneous functions
203 *
204 * GPIO / interrupt inputs
205*/
206
207#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
208#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
209#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
210
211#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
212#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
213#define S3C2410_GPE0_MASK (0x03 << 0)
214
215#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
216#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
217#define S3C2410_GPE1_MASK (0x03 << 2)
218
219#define S3C2410_GPE2_CDCLK (0x02 << 4)
220#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
221
222#define S3C2410_GPE3_I2SSDI (0x02 << 6)
223#define S3C2443_GPE3_AC_SDI (0x03 << 6)
224#define S3C2410_GPE3_nSS0 (0x03 << 6)
225#define S3C2410_GPE3_MASK (0x03 << 6)
226
227#define S3C2410_GPE4_I2SSDO (0x02 << 8)
228#define S3C2443_GPE4_AC_SDO (0x03 << 8)
229#define S3C2410_GPE4_I2SSDI (0x03 << 8)
230#define S3C2410_GPE4_MASK (0x03 << 8)
231
232#define S3C2410_GPE5_SDCLK (0x02 << 10)
233#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
234#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
235
236#define S3C2410_GPE6_SDCMD (0x02 << 12)
237#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
238#define S3C2443_GPE6_AC_SDI (0x03 << 12)
239
240#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
241#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
242#define S3C2443_GPE7_AC_SDO (0x03 << 14)
243
244#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
245#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
246#define S3C2443_GPE8_AC_SYNC (0x03 << 16)
247
248#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
249#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
250#define S3C2443_GPE9_AC_nRESET (0x03 << 18)
251
252#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
253#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
254
255#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
256
257#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
258
259#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
260
261#define S3C2410_GPE14_IICSCL (0x02 << 28)
262#define S3C2410_GPE14_MASK (0x03 << 28)
263
264#define S3C2410_GPE15_IICSDA (0x02 << 30)
265#define S3C2410_GPE15_MASK (0x03 << 30)
266
267#define S3C2440_GPE0_ACSYNC (0x03 << 0)
268#define S3C2440_GPE1_ACBITCLK (0x03 << 2)
269#define S3C2440_GPE2_ACRESET (0x03 << 4)
270#define S3C2440_GPE3_ACIN (0x03 << 6)
271#define S3C2440_GPE4_ACOUT (0x03 << 8)
272
273#define S3C2410_GPE_PUPDIS(x) (1<<(x))
274
275/* S3C2410:
276 * Port F consists of 8 GPIO/Special function
277 *
278 * GPIO / interrupt inputs
279 *
280 * GPFCON has 2 bits for each of the input pins on port F
281 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
282 *
283 * pull up works like all other ports.
284 *
285 * GPIO/serial/misc pins
286*/
287
288#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
289#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
290#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
291
292#define S3C2410_GPF0_EINT0 (0x02 << 0)
293#define S3C2410_GPF1_EINT1 (0x02 << 2)
294#define S3C2410_GPF2_EINT2 (0x02 << 4)
295#define S3C2410_GPF3_EINT3 (0x02 << 6)
296#define S3C2410_GPF4_EINT4 (0x02 << 8)
297#define S3C2410_GPF5_EINT5 (0x02 << 10)
298#define S3C2410_GPF6_EINT6 (0x02 << 12)
299#define S3C2410_GPF7_EINT7 (0x02 << 14)
300#define S3C2410_GPF_PUPDIS(x) (1<<(x))
301
302/* S3C2410:
303 * Port G consists of 8 GPIO/IRQ/Special function
304 *
305 * GPGCON has 2 bits for each of the input pins on port F
306 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
307 *
308 * pull up works like all other ports.
309*/
310
311#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
312#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
313#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
314
315#define S3C2410_GPG0_EINT8 (0x02 << 0)
316
317#define S3C2410_GPG1_EINT9 (0x02 << 2)
318
319#define S3C2410_GPG2_EINT10 (0x02 << 4)
320#define S3C2410_GPG2_nSS0 (0x03 << 4)
321
322#define S3C2410_GPG3_EINT11 (0x02 << 6)
323#define S3C2410_GPG3_nSS1 (0x03 << 6)
324
325#define S3C2410_GPG4_EINT12 (0x02 << 8)
326#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
327#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
328
329#define S3C2410_GPG5_EINT13 (0x02 << 10)
330#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
331
332#define S3C2410_GPG6_EINT14 (0x02 << 12)
333#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
334
335#define S3C2410_GPG7_EINT15 (0x02 << 14)
336#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
337
338#define S3C2410_GPG8_EINT16 (0x02 << 16)
339
340#define S3C2410_GPG9_EINT17 (0x02 << 18)
341
342#define S3C2410_GPG10_EINT18 (0x02 << 20)
343
344#define S3C2410_GPG11_EINT19 (0x02 << 22)
345#define S3C2410_GPG11_TCLK1 (0x03 << 22)
346#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
347
348#define S3C2410_GPG12_EINT20 (0x02 << 24)
349#define S3C2410_GPG12_XMON (0x03 << 24)
350#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
351#define S3C2443_GPG12_nINPACK (0x03 << 24)
352
353#define S3C2410_GPG13_EINT21 (0x02 << 26)
354#define S3C2410_GPG13_nXPON (0x03 << 26)
355#define S3C2443_GPG13_CF_nREG (0x03 << 26)
356
357#define S3C2410_GPG14_EINT22 (0x02 << 28)
358#define S3C2410_GPG14_YMON (0x03 << 28)
359#define S3C2443_GPG14_CF_RESET (0x03 << 28)
360
361#define S3C2410_GPG15_EINT23 (0x02 << 30)
362#define S3C2410_GPG15_nYPON (0x03 << 30)
363#define S3C2443_GPG15_CF_PWR (0x03 << 30)
364
365#define S3C2410_GPG_PUPDIS(x) (1<<(x))
366
367/* Port H consists of11 GPIO/serial/Misc pins
368 *
369 * GPGCON has 2 bits for each of the input pins on port F
370 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
371 *
372 * pull up works like all other ports.
373*/
374
375#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
376#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
377#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
378
379#define S3C2410_GPH0_nCTS0 (0x02 << 0)
380#define S3C2416_GPH0_TXD0 (0x02 << 0)
381
382#define S3C2410_GPH1_nRTS0 (0x02 << 2)
383#define S3C2416_GPH1_RXD0 (0x02 << 2)
384
385#define S3C2410_GPH2_TXD0 (0x02 << 4)
386#define S3C2416_GPH2_TXD1 (0x02 << 4)
387
388#define S3C2410_GPH3_RXD0 (0x02 << 6)
389#define S3C2416_GPH3_RXD1 (0x02 << 6)
390
391#define S3C2410_GPH4_TXD1 (0x02 << 8)
392#define S3C2416_GPH4_TXD2 (0x02 << 8)
393
394#define S3C2410_GPH5_RXD1 (0x02 << 10)
395#define S3C2416_GPH5_RXD2 (0x02 << 10)
396
397#define S3C2410_GPH6_TXD2 (0x02 << 12)
398#define S3C2416_GPH6_TXD3 (0x02 << 12)
399#define S3C2410_GPH6_nRTS1 (0x03 << 12)
400#define S3C2416_GPH6_nRTS2 (0x03 << 12)
401
402#define S3C2410_GPH7_RXD2 (0x02 << 14)
403#define S3C2416_GPH7_RXD3 (0x02 << 14)
404#define S3C2410_GPH7_nCTS1 (0x03 << 14)
405#define S3C2416_GPH7_nCTS2 (0x03 << 14)
406
407#define S3C2410_GPH8_UCLK (0x02 << 16)
408#define S3C2416_GPH8_nCTS0 (0x02 << 16)
409
410#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
411#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
412#define S3C2416_GPH9_nRTS0 (0x02 << 18)
413
414#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
415#define S3C2416_GPH10_nCTS1 (0x02 << 20)
416
417#define S3C2416_GPH11_nRTS1 (0x02 << 22)
418
419#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
420
421#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
422
423#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
424
425/* The S3C2412 and S3C2413 move the GPJ register set to after
426 * GPH, which means all registers after 0x80 are now offset by 0x10
427 * for the 2412/2413 from the 2410/2440/2442
428*/
429
430/* S3C2443 and above */
431#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)
432#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)
433#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)
434
435#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)
436#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)
437#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)
438
439#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)
440#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)
441#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)
442
443#define S3C2443_GPMCON S3C2410_GPIOREG(0x100)
444#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)
445#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
446
447/* miscellaneous control */
448#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
449#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
450
451#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
452
453/* see clock.h for dclk definitions */
454
455/* pullup control on databus */
456#define S3C2410_MISCCR_SPUCR_HEN (0<<0)
457#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
458#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
459#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
460
461#define S3C2410_MISCCR_USBDEV (0<<3)
462#define S3C2410_MISCCR_USBHOST (1<<3)
463
464#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
465#define S3C2410_MISCCR_CLK0_UPLL (1<<4)
466#define S3C2410_MISCCR_CLK0_FCLK (2<<4)
467#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
468#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
469#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
470#define S3C2410_MISCCR_CLK0_MASK (7<<4)
471
472#define S3C2412_MISCCR_CLK0_RTC (2<<4)
473
474#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
475#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
476#define S3C2410_MISCCR_CLK1_FCLK (2<<8)
477#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
478#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
479#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
480#define S3C2410_MISCCR_CLK1_MASK (7<<8)
481
482#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
483
484#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
485#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
486#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
487
488#define S3C2410_MISCCR_nRSTCON (1<<16)
489
490#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
491#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
492#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
493#define S3C2410_MISCCR_SDSLEEP (7<<17)
494
495#define S3C2416_MISCCR_FLT_I2C (1<<24)
496#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
497
498/* external interrupt control... */
499/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
500 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
501 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
502 *
503 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
504 *
505 * Samsung datasheet p9-25
506*/
507#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
508#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
509#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
510
511#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
512#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
513#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
514
515/* interrupt filtering conrrol for EINT16..EINT23 */
516#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
517#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
518#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
519#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
520
521#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
522#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
523#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
524#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
525
526/* values for interrupt filtering */
527#define S3C2410_EINTFLT_PCLK (0x00)
528#define S3C2410_EINTFLT_EXTCLK (1<<7)
529#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
530
531/* removed EINTxxxx defs from here, not meant for this */
532
533/* GSTATUS have miscellaneous information in them
534 *
535 * These move between s3c2410 and s3c2412 style systems.
536 */
537
538#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
539#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
540#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
541#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
542#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
543
544#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
545#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
546#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
547#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
548#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
549
550#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
551#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
552#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
553#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
554#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
555
556#define S3C2410_GSTATUS0_nWAIT (1<<3)
557#define S3C2410_GSTATUS0_NCON (1<<2)
558#define S3C2410_GSTATUS0_RnB (1<<1)
559#define S3C2410_GSTATUS0_nBATTFLT (1<<0)
560
561#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
562#define S3C2410_GSTATUS1_2410 (0x32410000)
563#define S3C2410_GSTATUS1_2412 (0x32412001)
564#define S3C2410_GSTATUS1_2416 (0x32416003)
565#define S3C2410_GSTATUS1_2440 (0x32440000)
566#define S3C2410_GSTATUS1_2442 (0x32440aaa)
567/* some 2416 CPUs report this value also */
568#define S3C2410_GSTATUS1_2450 (0x32450003)
569
570#define S3C2410_GSTATUS2_WTRESET (1<<2)
571#define S3C2410_GSTATUS2_OFFRESET (1<<1)
572#define S3C2410_GSTATUS2_PONRESET (1<<0)
573
574/* 2412/2413 sleep configuration registers */
575
576#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
577#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
578#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
579#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
580#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
581#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
582
583/* definitions for each pin bit */
584#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )
585#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
586#define S3C2412_GPIO_SLPCON_IN ( 0x02 )
587#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )
588
589#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
590#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))
591#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
592#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))
593#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */
594#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
595
596#define S3C2412_SLPCON_ALL_LOW (0x0)
597#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)
598#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)
599#define S3C2412_SLPCON_ALL_PULL (0x33333333)
600
601#endif /* __ASM_ARCH_REGS_GPIO_H */
602
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
deleted file mode 100644
index 19575e061114..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 GPIO J register definitions
11*/
12
13
14#ifndef __ASM_ARCH_REGS_GPIOJ_H
15#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
16
17/* Port J consists of 13 GPIO/Camera pins
18 *
19 * GPJCON has 2 bits for each of the input pins on port F
20 * 00 = 0 input, 1 output, 2 Camera
21 *
22 * pull up works like all other ports.
23*/
24
25#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)
26#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)
27#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)
28#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)
29
30#define S3C2440_GPJ0_OUTP (0x01 << 0)
31#define S3C2440_GPJ0_CAMDATA0 (0x02 << 0)
32
33#define S3C2440_GPJ1_OUTP (0x01 << 2)
34#define S3C2440_GPJ1_CAMDATA1 (0x02 << 2)
35
36#define S3C2440_GPJ2_OUTP (0x01 << 4)
37#define S3C2440_GPJ2_CAMDATA2 (0x02 << 4)
38
39#define S3C2440_GPJ3_OUTP (0x01 << 6)
40#define S3C2440_GPJ3_CAMDATA3 (0x02 << 6)
41
42#define S3C2440_GPJ4_OUTP (0x01 << 8)
43#define S3C2440_GPJ4_CAMDATA4 (0x02 << 8)
44
45#define S3C2440_GPJ5_OUTP (0x01 << 10)
46#define S3C2440_GPJ5_CAMDATA5 (0x02 << 10)
47
48#define S3C2440_GPJ6_OUTP (0x01 << 12)
49#define S3C2440_GPJ6_CAMDATA6 (0x02 << 12)
50
51#define S3C2440_GPJ7_OUTP (0x01 << 14)
52#define S3C2440_GPJ7_CAMDATA7 (0x02 << 14)
53
54#define S3C2440_GPJ8_OUTP (0x01 << 16)
55#define S3C2440_GPJ8_CAMPCLK (0x02 << 16)
56
57#define S3C2440_GPJ9_OUTP (0x01 << 18)
58#define S3C2440_GPJ9_CAMVSYNC (0x02 << 18)
59
60#define S3C2440_GPJ10_OUTP (0x01 << 20)
61#define S3C2440_GPJ10_CAMHREF (0x02 << 20)
62
63#define S3C2440_GPJ11_OUTP (0x01 << 22)
64#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
65
66#define S3C2440_GPJ12_OUTP (0x01 << 24)
67#define S3C2440_GPJ12_CAMRESET (0x02 << 24)
68
69#endif /* __ASM_ARCH_REGS_GPIOJ_H */
70
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c2410/include/mach/regs-irq.h
deleted file mode 100644
index 0f07ba30b1fb..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_REGS_IRQ_H
13#define ___ASM_ARCH_REGS_IRQ_H
14
15/* interrupt controller */
16
17#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
18#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
19#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
20
21#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
22#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
23#define S3C2410_INTMSK S3C2410_IRQREG(0x008)
24#define S3C2410_PRIORITY S3C2410_IRQREG(0x00C)
25#define S3C2410_INTPND S3C2410_IRQREG(0x010)
26#define S3C2410_INTOFFSET S3C2410_IRQREG(0x014)
27#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
28#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
29
30#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030)
31#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034)
32#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040)
33#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044)
34#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048)
35#define S3C2416_INTPND2 S3C2410_IRQREG(0x050)
36#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054)
37#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070)
38#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074)
39
40/* mask: 0=enable, 1=disable
41 * 1 bit EINT, 4=EINT4, 23=EINT23
42 * EINT0,1,2,3 are not handled here.
43*/
44
45#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
46#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
47#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
48#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
49
50#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
51#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
52
53#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c2410/include/mach/regs-lcd.h
deleted file mode 100644
index ee8f040aff5f..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h
+++ /dev/null
@@ -1,162 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-lcd.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_REGS_LCD_H
13#define ___ASM_ARCH_REGS_LCD_H
14
15#define S3C2410_LCDREG(x) (x)
16
17/* LCD control registers */
18#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
19#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
20#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
21#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
22#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
23
24#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
25#define S3C2410_LCDCON1_MMODE (1<<7)
26#define S3C2410_LCDCON1_DSCAN4 (0<<5)
27#define S3C2410_LCDCON1_STN4 (1<<5)
28#define S3C2410_LCDCON1_STN8 (2<<5)
29#define S3C2410_LCDCON1_TFT (3<<5)
30
31#define S3C2410_LCDCON1_STN1BPP (0<<1)
32#define S3C2410_LCDCON1_STN2GREY (1<<1)
33#define S3C2410_LCDCON1_STN4GREY (2<<1)
34#define S3C2410_LCDCON1_STN8BPP (3<<1)
35#define S3C2410_LCDCON1_STN12BPP (4<<1)
36
37#define S3C2410_LCDCON1_TFT1BPP (8<<1)
38#define S3C2410_LCDCON1_TFT2BPP (9<<1)
39#define S3C2410_LCDCON1_TFT4BPP (10<<1)
40#define S3C2410_LCDCON1_TFT8BPP (11<<1)
41#define S3C2410_LCDCON1_TFT16BPP (12<<1)
42#define S3C2410_LCDCON1_TFT24BPP (13<<1)
43
44#define S3C2410_LCDCON1_ENVID (1)
45
46#define S3C2410_LCDCON1_MODEMASK 0x1E
47
48#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
49#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
50#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
51#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
52
53#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
54#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
55#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
56
57#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
58#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
59#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
60#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
61#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
62
63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
65
66/* LDCCON4 changes for STN mode on the S3C2412 */
67
68#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
69#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
70#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
71
72#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
73
74#define S3C2410_LCDCON5_BPP24BL (1<<12)
75#define S3C2410_LCDCON5_FRM565 (1<<11)
76#define S3C2410_LCDCON5_INVVCLK (1<<10)
77#define S3C2410_LCDCON5_INVVLINE (1<<9)
78#define S3C2410_LCDCON5_INVVFRAME (1<<8)
79#define S3C2410_LCDCON5_INVVD (1<<7)
80#define S3C2410_LCDCON5_INVVDEN (1<<6)
81#define S3C2410_LCDCON5_INVPWREN (1<<5)
82#define S3C2410_LCDCON5_INVLEND (1<<4)
83#define S3C2410_LCDCON5_PWREN (1<<3)
84#define S3C2410_LCDCON5_ENLEND (1<<2)
85#define S3C2410_LCDCON5_BSWP (1<<1)
86#define S3C2410_LCDCON5_HWSWP (1<<0)
87
88/* framebuffer start addressed */
89#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
90#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
91#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
92
93#define S3C2410_LCDBANK(x) ((x) << 21)
94#define S3C2410_LCDBASEU(x) (x)
95
96#define S3C2410_OFFSIZE(x) ((x) << 11)
97#define S3C2410_PAGEWIDTH(x) (x)
98
99/* colour lookup and miscellaneous controls */
100
101#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
102#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
103#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
104
105#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
106#define S3C2410_TPAL S3C2410_LCDREG(0x50)
107
108#define S3C2410_TPAL_EN (1<<24)
109
110/* interrupt info */
111#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
112#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
113#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
114#define S3C2410_LCDINT_FIWSEL (1<<2)
115#define S3C2410_LCDINT_FRSYNC (1<<1)
116#define S3C2410_LCDINT_FICNT (1<<0)
117
118/* s3c2442 extra stn registers */
119
120#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
121#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
122#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
123#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
124
125#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
126
127#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
128
129/* S3C2412 registers */
130
131#define S3C2412_TPAL S3C2410_LCDREG(0x20)
132
133#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
134#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
135#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
136
137#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
138
139#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
140#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
141#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
142#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
143
144#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
145#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
146#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
147
148#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
149
150/* general registers */
151
152/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
153 * are available. */
154
155#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54)
156#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24)
157
158#define S3C24XX_LCDINTPND (0x00)
159#define S3C24XX_LCDSRCPND (0x04)
160#define S3C24XX_LCDINTMSK (0x08)
161
162#endif /* ___ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Memory Control register definitions
11*/
12
13#ifndef __ASM_ARM_MEMREGS_H
14#define __ASM_ARM_MEMREGS_H
15
16#ifndef S3C2410_MEMREG
17#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#endif
19
20/* bus width, and wait state control */
21#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
22
23/* bank zero config - note, pinstrapped from OM pins! */
24#define S3C2410_BWSCON_DW0_16 (1<<1)
25#define S3C2410_BWSCON_DW0_32 (2<<1)
26
27/* bank one configs */
28#define S3C2410_BWSCON_DW1_8 (0<<4)
29#define S3C2410_BWSCON_DW1_16 (1<<4)
30#define S3C2410_BWSCON_DW1_32 (2<<4)
31#define S3C2410_BWSCON_WS1 (1<<6)
32#define S3C2410_BWSCON_ST1 (1<<7)
33
34/* bank 2 configurations */
35#define S3C2410_BWSCON_DW2_8 (0<<8)
36#define S3C2410_BWSCON_DW2_16 (1<<8)
37#define S3C2410_BWSCON_DW2_32 (2<<8)
38#define S3C2410_BWSCON_WS2 (1<<10)
39#define S3C2410_BWSCON_ST2 (1<<11)
40
41/* bank 3 configurations */
42#define S3C2410_BWSCON_DW3_8 (0<<12)
43#define S3C2410_BWSCON_DW3_16 (1<<12)
44#define S3C2410_BWSCON_DW3_32 (2<<12)
45#define S3C2410_BWSCON_WS3 (1<<14)
46#define S3C2410_BWSCON_ST3 (1<<15)
47
48/* bank 4 configurations */
49#define S3C2410_BWSCON_DW4_8 (0<<16)
50#define S3C2410_BWSCON_DW4_16 (1<<16)
51#define S3C2410_BWSCON_DW4_32 (2<<16)
52#define S3C2410_BWSCON_WS4 (1<<18)
53#define S3C2410_BWSCON_ST4 (1<<19)
54
55/* bank 5 configurations */
56#define S3C2410_BWSCON_DW5_8 (0<<20)
57#define S3C2410_BWSCON_DW5_16 (1<<20)
58#define S3C2410_BWSCON_DW5_32 (2<<20)
59#define S3C2410_BWSCON_WS5 (1<<22)
60#define S3C2410_BWSCON_ST5 (1<<23)
61
62/* bank 6 configurations */
63#define S3C2410_BWSCON_DW6_8 (0<<24)
64#define S3C2410_BWSCON_DW6_16 (1<<24)
65#define S3C2410_BWSCON_DW6_32 (2<<24)
66#define S3C2410_BWSCON_WS6 (1<<26)
67#define S3C2410_BWSCON_ST6 (1<<27)
68
69/* bank 7 configurations */
70#define S3C2410_BWSCON_DW7_8 (0<<28)
71#define S3C2410_BWSCON_DW7_16 (1<<28)
72#define S3C2410_BWSCON_DW7_32 (2<<28)
73#define S3C2410_BWSCON_WS7 (1<<30)
74#define S3C2410_BWSCON_ST7 (1<<31)
75
76/* accesor functions for getting BANK(n) configuration. (n != 0) */
77
78#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79
80#define S3C2410_BWSCON_DW8 (0)
81#define S3C2410_BWSCON_DW16 (1)
82#define S3C2410_BWSCON_DW32 (2)
83#define S3C2410_BWSCON_WS (1 << 2)
84#define S3C2410_BWSCON_ST (1 << 3)
85
86/* memory set (rom, ram) */
87#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
88#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
89#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
90#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
91#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
92#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
93#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
94#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
95
96/* bank configuration registers */
97
98#define S3C2410_BANKCON_PMCnorm (0x00)
99#define S3C2410_BANKCON_PMC4 (0x01)
100#define S3C2410_BANKCON_PMC8 (0x02)
101#define S3C2410_BANKCON_PMC16 (0x03)
102
103/* bank configurations for banks 0..7, note banks
104 * 6 and 7 have different configurations depending on
105 * the memory type bits */
106
107#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
108#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
109#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
110#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
111#define S3C2410_BANKCON_Tacp_SHIFT (2)
112
113#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
114#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
115#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
116#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
117#define S3C2410_BANKCON_Tcah_SHIFT (4)
118
119#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
120#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
121#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
122#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
123#define S3C2410_BANKCON_Tcoh_SHIFT (6)
124
125#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
126#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
127#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
128#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
129#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
130#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
131#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
132#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
133#define S3C2410_BANKCON_Tacc_SHIFT (8)
134
135#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
136#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
137#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
138#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
139#define S3C2410_BANKCON_Tcos_SHIFT (11)
140
141#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
142#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
143#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
144#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
145#define S3C2410_BANKCON_Tacs_SHIFT (13)
146
147#define S3C2410_BANKCON_SRAM (0x0 << 15)
148#define S3C2410_BANKCON_SDRAM (0x3 << 15)
149
150/* next bits only for SDRAM in 6,7 */
151#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
152#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
153#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
154
155/* control column address select */
156#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
157#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
158#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
159
160#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
161#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
162#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
163#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
164
165/* refresh control */
166
167#define S3C2410_REFRESH_REFEN (1<<23)
168#define S3C2410_REFRESH_SELF (1<<22)
169#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
170
171#define S3C2410_REFRESH_TRP_MASK (3<<20)
172#define S3C2410_REFRESH_TRP_2clk (0<<20)
173#define S3C2410_REFRESH_TRP_3clk (1<<20)
174#define S3C2410_REFRESH_TRP_4clk (2<<20)
175
176#define S3C2410_REFRESH_TSRC_MASK (3<<18)
177#define S3C2410_REFRESH_TSRC_4clk (0<<18)
178#define S3C2410_REFRESH_TSRC_5clk (1<<18)
179#define S3C2410_REFRESH_TSRC_6clk (2<<18)
180#define S3C2410_REFRESH_TSRC_7clk (3<<18)
181
182
183/* mode select register(s) */
184
185#define S3C2410_MRSRB_CL1 (0x00 << 4)
186#define S3C2410_MRSRB_CL2 (0x02 << 4)
187#define S3C2410_MRSRB_CL3 (0x03 << 4)
188
189/* bank size register */
190#define S3C2410_BANKSIZE_128M (0x2 << 0)
191#define S3C2410_BANKSIZE_64M (0x1 << 0)
192#define S3C2410_BANKSIZE_32M (0x0 << 0)
193#define S3C2410_BANKSIZE_16M (0x7 << 0)
194#define S3C2410_BANKSIZE_8M (0x6 << 0)
195#define S3C2410_BANKSIZE_4M (0x5 << 0)
196#define S3C2410_BANKSIZE_2M (0x4 << 0)
197#define S3C2410_BANKSIZE_MASK (0x7 << 0)
198#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
199#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
200#define S3C2410_BANKSIZE_BURST (1<<7)
201
202#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h
deleted file mode 100644
index 4932b87bdf3d..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-power.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24XX power control register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
19#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
20
21#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
22#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
25
26#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
27#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
28#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
29#define S3C2412_PWRCFG_BATF_MASK (3<<0)
30
31#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6)
32#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6)
33#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6)
34#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6)
35#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6)
36
37#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8)
38#define S3C2412_PWRCFG_NAND_NORST (1<<9)
39
40#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
deleted file mode 100644
index fb6352515090..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2412 memory register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2412_MEM
15#define __ASM_ARM_REGS_S3C2412_MEM
16
17#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
19
20#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
21#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
22
23#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
24#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
25#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08)
26#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C)
27
28#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
29#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
30
31/* EBI control registers */
32
33#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
34#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
35
36/* SSMC control registers */
37
38#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
39#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
40#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
41#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
42#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
43#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
44#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
45#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
46#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
47
48#endif /* __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
deleted file mode 100644
index aa69dc79bc38..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
2 *
3 * Copyright 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2412 specific register definitions
12*/
13
14#ifndef __ASM_ARCH_REGS_S3C2412_H
15#define __ASM_ARCH_REGS_S3C2412_H "s3c2412"
16
17#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
18#define S3C2412_SWRST_RESET (0x533C2412)
19
20/* see regs-power.h for the other registers in the power block. */
21
22#endif /* __ASM_ARCH_REGS_S3C2412_H */
23
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
deleted file mode 100644
index 2f31b74974af..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2416 memory register definitions
13*/
14
15#ifndef __ASM_ARM_REGS_S3C2416_MEM
16#define __ASM_ARM_REGS_S3C2416_MEM
17
18#ifndef S3C2416_MEMREG
19#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
20#endif
21
22#define S3C2416_BANKCFG S3C2416_MEMREG(0x00)
23#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04)
24#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08)
25#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C)
26
27#define S3C2416_REFRESH S3C2416_MEMREG(0x10)
28#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14)
29
30#endif /* __ASM_ARM_REGS_S3C2416_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
deleted file mode 100644
index e443167efb87..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * S3C2416 specific register definitions
13*/
14
15#ifndef __ASM_ARCH_REGS_S3C2416_H
16#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
17
18#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44)
19#define S3C2416_SWRST_RESET (0x533C2416)
20
21/* see regs-power.h for the other registers in the power block. */
22
23#endif /* __ASM_ARCH_REGS_S3C2416_H */
24
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
deleted file mode 100644
index c3feff3c0488..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ /dev/null
@@ -1,194 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2443 clock register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
15#define __ASM_ARM_REGS_S3C2443_CLOCK
16
17#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
18
19#define S3C2443_PLLCON_MDIVSHIFT 16
20#define S3C2443_PLLCON_PDIVSHIFT 8
21#define S3C2443_PLLCON_SDIVSHIFT 0
22#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
23#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
24#define S3C2443_PLLCON_SDIVMASK (3)
25
26#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
27#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
28#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
29#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
30#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
31#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
32#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
33#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
34#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
35#define S3C2443_SWRST S3C2443_CLKREG(0x44)
36#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
37#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
38#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
39#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
40#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
41#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
42#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
43#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
44
45#define S3C2443_SWRST_RESET (0x533c2443)
46
47#define S3C2443_PLLCON_OFF (1<<24)
48
49#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
50#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
51#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
52#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
53#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
54
55#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
56
57#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
58#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
59
60#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
61
62#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
63#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
64
65#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
66#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
67
68#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
69#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
70#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
71#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
72#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
73#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
74#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
75#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
76#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
77#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
78#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
79
80/* S3C2443_CLKDIV1 removed, only used in clock.c code */
81
82#define S3C2443_CLKCON_NAND
83
84#define S3C2443_HCLKCON_DMA0 (1<<0)
85#define S3C2443_HCLKCON_DMA1 (1<<1)
86#define S3C2443_HCLKCON_DMA2 (1<<2)
87#define S3C2443_HCLKCON_DMA3 (1<<3)
88#define S3C2443_HCLKCON_DMA4 (1<<4)
89#define S3C2443_HCLKCON_DMA5 (1<<5)
90#define S3C2443_HCLKCON_CAMIF (1<<8)
91#define S3C2443_HCLKCON_LCDC (1<<9)
92#define S3C2443_HCLKCON_USBH (1<<11)
93#define S3C2443_HCLKCON_USBD (1<<12)
94#define S3C2416_HCLKCON_HSMMC0 (1<<15)
95#define S3C2443_HCLKCON_HSMMC (1<<16)
96#define S3C2443_HCLKCON_CFC (1<<17)
97#define S3C2443_HCLKCON_SSMC (1<<18)
98#define S3C2443_HCLKCON_DRAMC (1<<19)
99
100#define S3C2443_PCLKCON_UART0 (1<<0)
101#define S3C2443_PCLKCON_UART1 (1<<1)
102#define S3C2443_PCLKCON_UART2 (1<<2)
103#define S3C2443_PCLKCON_UART3 (1<<3)
104#define S3C2443_PCLKCON_IIC (1<<4)
105#define S3C2443_PCLKCON_SDI (1<<5)
106#define S3C2443_PCLKCON_HSSPI (1<<6)
107#define S3C2443_PCLKCON_ADC (1<<7)
108#define S3C2443_PCLKCON_AC97 (1<<8)
109#define S3C2443_PCLKCON_IIS (1<<9)
110#define S3C2443_PCLKCON_PWMT (1<<10)
111#define S3C2443_PCLKCON_WDT (1<<11)
112#define S3C2443_PCLKCON_RTC (1<<12)
113#define S3C2443_PCLKCON_GPIO (1<<13)
114#define S3C2443_PCLKCON_SPI0 (1<<14)
115#define S3C2443_PCLKCON_SPI1 (1<<15)
116
117#define S3C2443_SCLKCON_DDRCLK (1<<16)
118#define S3C2443_SCLKCON_SSMCCLK (1<<15)
119#define S3C2443_SCLKCON_HSSPICLK (1<<14)
120#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
121#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
122#define S3C2443_SCLKCON_CAMCLK (1<<11)
123#define S3C2443_SCLKCON_DISPCLK (1<<10)
124#define S3C2443_SCLKCON_I2SCLK (1<<9)
125#define S3C2443_SCLKCON_UARTCLK (1<<8)
126#define S3C2443_SCLKCON_USBHOST (1<<1)
127
128#define S3C2443_PWRCFG_SLEEP (1<<15)
129
130#define S3C2443_PWRCFG_USBPHY (1 << 4)
131
132#define S3C2443_URSTCON_FUNCRST (1 << 2)
133#define S3C2443_URSTCON_PHYRST (1 << 0)
134
135#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
136#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
137#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
138#define S3C2443_PHYCTRL_DSPORT (1 << 0)
139
140#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
141#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
142#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
143#define S3C2443_PHYPWR_XO_ON (1 << 2)
144#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
145#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
146
147#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
148#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
149#define S3C2443_UCLKCON_TCLKEN (1 << 0)
150
151#include <asm/div64.h>
152
153static inline unsigned int
154s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
155{
156 unsigned int mdiv, pdiv, sdiv;
157 uint64_t fvco;
158
159 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
160 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
161 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
162
163 mdiv &= S3C2443_PLLCON_MDIVMASK;
164 pdiv &= S3C2443_PLLCON_PDIVMASK;
165 sdiv &= S3C2443_PLLCON_SDIVMASK;
166
167 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
168 do_div(fvco, pdiv << sdiv);
169
170 return (unsigned int)fvco;
171}
172
173static inline unsigned int
174s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
175{
176 unsigned int mdiv, pdiv, sdiv;
177 uint64_t fvco;
178
179 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
180 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
181 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
182
183 mdiv &= S3C2443_PLLCON_MDIVMASK;
184 pdiv &= S3C2443_PLLCON_PDIVMASK;
185 sdiv &= S3C2443_PLLCON_SDIVMASK;
186
187 fvco = (uint64_t)baseclk * (mdiv + 8);
188 do_div(fvco, (pdiv + 2) << sdiv);
189
190 return (unsigned int)fvco;
191}
192
193#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
194
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
deleted file mode 100644
index cbf2d8884e30..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 MMC/SDIO register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_SDI
14#define __ASM_ARM_REGS_SDI "regs-sdi.h"
15
16#define S3C2410_SDICON (0x00)
17#define S3C2410_SDIPRE (0x04)
18#define S3C2410_SDICMDARG (0x08)
19#define S3C2410_SDICMDCON (0x0C)
20#define S3C2410_SDICMDSTAT (0x10)
21#define S3C2410_SDIRSP0 (0x14)
22#define S3C2410_SDIRSP1 (0x18)
23#define S3C2410_SDIRSP2 (0x1C)
24#define S3C2410_SDIRSP3 (0x20)
25#define S3C2410_SDITIMER (0x24)
26#define S3C2410_SDIBSIZE (0x28)
27#define S3C2410_SDIDCON (0x2C)
28#define S3C2410_SDIDCNT (0x30)
29#define S3C2410_SDIDSTA (0x34)
30#define S3C2410_SDIFSTA (0x38)
31
32#define S3C2410_SDIDATA (0x3C)
33#define S3C2410_SDIIMSK (0x40)
34
35#define S3C2440_SDIDATA (0x40)
36#define S3C2440_SDIIMSK (0x3C)
37
38#define S3C2440_SDICON_SDRESET (1<<8)
39#define S3C2440_SDICON_MMCCLOCK (1<<5)
40#define S3C2410_SDICON_BYTEORDER (1<<4)
41#define S3C2410_SDICON_SDIOIRQ (1<<3)
42#define S3C2410_SDICON_RWAITEN (1<<2)
43#define S3C2410_SDICON_FIFORESET (1<<1)
44#define S3C2410_SDICON_CLOCKTYPE (1<<0)
45
46#define S3C2410_SDICMDCON_ABORT (1<<12)
47#define S3C2410_SDICMDCON_WITHDATA (1<<11)
48#define S3C2410_SDICMDCON_LONGRSP (1<<10)
49#define S3C2410_SDICMDCON_WAITRSP (1<<9)
50#define S3C2410_SDICMDCON_CMDSTART (1<<8)
51#define S3C2410_SDICMDCON_SENDERHOST (1<<6)
52#define S3C2410_SDICMDCON_INDEX (0x3f)
53
54#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12)
55#define S3C2410_SDICMDSTAT_CMDSENT (1<<11)
56#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
57#define S3C2410_SDICMDSTAT_RSPFIN (1<<9)
58#define S3C2410_SDICMDSTAT_XFERING (1<<8)
59#define S3C2410_SDICMDSTAT_INDEX (0xff)
60
61#define S3C2440_SDIDCON_DS_BYTE (0<<22)
62#define S3C2440_SDIDCON_DS_HALFWORD (1<<22)
63#define S3C2440_SDIDCON_DS_WORD (2<<22)
64#define S3C2410_SDIDCON_IRQPERIOD (1<<21)
65#define S3C2410_SDIDCON_TXAFTERRESP (1<<20)
66#define S3C2410_SDIDCON_RXAFTERCMD (1<<19)
67#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18)
68#define S3C2410_SDIDCON_BLOCKMODE (1<<17)
69#define S3C2410_SDIDCON_WIDEBUS (1<<16)
70#define S3C2410_SDIDCON_DMAEN (1<<15)
71#define S3C2410_SDIDCON_STOP (1<<14)
72#define S3C2440_SDIDCON_DATSTART (1<<14)
73#define S3C2410_SDIDCON_DATMODE (3<<12)
74#define S3C2410_SDIDCON_BLKNUM (0x7ff)
75
76/* constants for S3C2410_SDIDCON_DATMODE */
77#define S3C2410_SDIDCON_XFER_READY (0<<12)
78#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
79#define S3C2410_SDIDCON_XFER_RXSTART (2<<12)
80#define S3C2410_SDIDCON_XFER_TXSTART (3<<12)
81
82#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
83#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12)
84
85#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10)
86#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
87#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */
88#define S3C2410_SDIDSTA_CRCFAIL (1<<7)
89#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6)
90#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5)
91#define S3C2410_SDIDSTA_XFERFINISH (1<<4)
92#define S3C2410_SDIDSTA_BUSYFINISH (1<<3)
93#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */
94#define S3C2410_SDIDSTA_TXDATAON (1<<1)
95#define S3C2410_SDIDSTA_RXDATAON (1<<0)
96
97#define S3C2440_SDIFSTA_FIFORESET (1<<16)
98#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */
99#define S3C2410_SDIFSTA_TFDET (1<<13)
100#define S3C2410_SDIFSTA_RFDET (1<<12)
101#define S3C2410_SDIFSTA_TFHALF (1<<11)
102#define S3C2410_SDIFSTA_TFEMPTY (1<<10)
103#define S3C2410_SDIFSTA_RFLAST (1<<9)
104#define S3C2410_SDIFSTA_RFFULL (1<<8)
105#define S3C2410_SDIFSTA_RFHALF (1<<7)
106#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
107
108#define S3C2410_SDIIMSK_RESPONSECRC (1<<17)
109#define S3C2410_SDIIMSK_CMDSENT (1<<16)
110#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15)
111#define S3C2410_SDIIMSK_RESPONSEND (1<<14)
112#define S3C2410_SDIIMSK_READWAIT (1<<13)
113#define S3C2410_SDIIMSK_SDIOIRQ (1<<12)
114#define S3C2410_SDIIMSK_FIFOFAIL (1<<11)
115#define S3C2410_SDIIMSK_CRCSTATUS (1<<10)
116#define S3C2410_SDIIMSK_DATACRC (1<<9)
117#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8)
118#define S3C2410_SDIIMSK_DATAFINISH (1<<7)
119#define S3C2410_SDIIMSK_BUSYFINISH (1<<6)
120#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */
121#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4)
122#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3)
123#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2)
124#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1)
125#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0)
126
127#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
deleted file mode 100644
index 5e215c1a5c8f..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/system.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/system.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System function defines and includes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <mach/hardware.h>
15
16#include <mach/map.h>
17#include <mach/idle.h>
18
19#include <mach/regs-clock.h>
20
21void (*s3c24xx_idle)(void);
22
23void s3c24xx_default_idle(void)
24{
25 unsigned long tmp;
26 int i;
27
28 /* idle the system by using the idle mode which will wait for an
29 * interrupt to happen before restarting the system.
30 */
31
32 /* Warning: going into idle state upsets jtag scanning */
33
34 __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
35 S3C2410_CLKCON);
36
37 /* the samsung port seems to do a loop and then unset idle.. */
38 for (i = 0; i < 50; i++) {
39 tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
40 }
41
42 /* this bit is not cleared on re-start... */
43
44 __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
45 S3C2410_CLKCON);
46}
47
48static void arch_idle(void)
49{
50 if (s3c24xx_idle != NULL)
51 (s3c24xx_idle)();
52 else
53 s3c24xx_default_idle();
54}
diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c2410/include/mach/tick.h
deleted file mode 100644
index 544da41979db..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/tick.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C2410 - timer tick support
8 */
9
10#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
11
12static inline int s3c24xx_ostimer_pending(void)
13{
14 return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
15}
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c2410/include/mach/timex.h
deleted file mode 100644
index fe9ca1ffd51b..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/timex.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
17 * a variable is useless. It seems as long as we make our timers an
18 * exact multiple of HZ, any value that makes a 1->1 correspondence
19 * for the time conversion functions to/from jiffies is acceptable.
20*/
21
22#define CLOCK_TICK_RATE 12000000
23
24#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
deleted file mode 100644
index 8b283f847daa..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/uncompress.h
2 *
3 * Copyright (c) 2003-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2410 - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_UNCOMPRESS_H
15#define __ASM_ARCH_UNCOMPRESS_H
16
17#include <mach/regs-gpio.h>
18#include <mach/map.h>
19
20/* working in physical space... */
21#undef S3C2410_GPIOREG
22#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
23
24#include <plat/uncompress.h>
25
26static inline int is_arm926(void)
27{
28 unsigned int cpuid;
29
30 asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
31
32 return ((cpuid & 0xff0) == 0x260);
33}
34
35static void arch_detect_cpu(void)
36{
37 unsigned int cpuid;
38
39 cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
40 cpuid &= S3C2410_GSTATUS1_IDMASK;
41
42 if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
43 cpuid == S3C2410_GSTATUS1_2442 ||
44 cpuid == S3C2410_GSTATUS1_2416 ||
45 cpuid == S3C2410_GSTATUS1_2450) {
46 fifo_mask = S3C2440_UFSTAT_TXMASK;
47 fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
48 } else {
49 fifo_mask = S3C2410_UFSTAT_TXMASK;
50 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
51 }
52}
53
54#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
deleted file mode 100644
index e4119913d7c5..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * VR1000 - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_VR1000CPLD_H
14#define __ASM_ARCH_VR1000CPLD_H
15
16#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
17
18#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
deleted file mode 100644
index 47add133b8ee..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_VR1000IRQ_H
14#define __ASM_ARCH_VR1000IRQ_H
15
16/* irq numbers to onboard peripherals */
17
18#define IRQ_USBOC IRQ_EINT19
19#define IRQ_IDE0 IRQ_EINT16
20#define IRQ_IDE1 IRQ_EINT17
21#define IRQ_VR1000_SERIAL IRQ_EINT12
22#define IRQ_VR1000_DM9000A IRQ_EINT10
23#define IRQ_VR1000_DM9000N IRQ_EINT9
24#define IRQ_SMALERT IRQ_EINT8
25
26#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c2410/include/mach/vr1000-map.h
deleted file mode 100644
index 99612fcc4eb2..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h
+++ /dev/null
@@ -1,110 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x13000000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space. We also have the board's CPLD to find register space
18 * for.
19 */
20
21#ifndef __ASM_ARCH_VR1000MAP_H
22#define __ASM_ARCH_VR1000MAP_H
23
24#include <mach/bast-map.h>
25
26#define VR1000_IOADDR(x) BAST_IOADDR(x)
27
28/* we put the CPLD registers next, to get them out of the way */
29
30#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
31#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
32
33#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
34#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
35
36#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
37#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
38
39#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
40#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
41
42/* next, we have the PC104 ISA interrupt registers */
43
44#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
45#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
46
47#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
48#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
49
50#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
51#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
52
53/* 0xE0000000 contains the IO space that is split by speed and
54 * wether the access is for 8 or 16bit IO... this ensures that
55 * the correct access is made
56 *
57 * 0x10000000 of space, partitioned as so:
58 *
59 * 0x00000000 to 0x04000000 8bit, slow
60 * 0x04000000 to 0x08000000 16bit, slow
61 * 0x08000000 to 0x0C000000 16bit, net
62 * 0x0C000000 to 0x10000000 16bit, fast
63 *
64 * each of these spaces has the following in:
65 *
66 * 0x02000000 to 0x02100000 1MB IDE primary channel
67 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
68 * 0x02200000 to 0x02400000 1MB IDE secondary channel
69 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
70 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
71 * 0x02600000 to 0x02700000 1MB
72 *
73 * the phyiscal layout of the zones are:
74 * nGCS2 - 8bit, slow
75 * nGCS3 - 16bit, slow
76 * nGCS4 - 16bit, net
77 * nGCS5 - 16bit, fast
78 */
79
80#define VR1000_VA_MULTISPACE (0xE0000000)
81
82#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
83#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
84#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
85#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
86#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
87#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
88#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
89#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
90#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
91
92/* physical offset addresses for the peripherals */
93
94#define VR1000_PA_IDEPRI (0x02000000)
95#define VR1000_PA_IDEPRIAUX (0x02800000)
96#define VR1000_PA_IDESEC (0x03000000)
97#define VR1000_PA_IDESECAUX (0x03800000)
98#define VR1000_PA_DM9000 (0x05000000)
99
100#define VR1000_PA_SERIAL (0x11800000)
101#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
102
103/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
104#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
105
106/* some configurations for the peripherals */
107
108#define VR1000_DM9000_CS VR1000_VAM_CS4
109
110#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
deleted file mode 100644
index 4220cc60de3c..000000000000
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-amlm5900.c
2 *
3 * linux/arch/arm/mach-s3c2410/mach-amlm5900.c
4 *
5 * Copyright (c) 2006 American Microsystems Limited
6 * David Anders <danders@amltd.com>
7
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * @History:
24 * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
25 * Ben Dooks <ben@simtec.co.uk>
26 *
27 ***********************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/types.h>
31#include <linux/interrupt.h>
32#include <linux/list.h>
33#include <linux/timer.h>
34#include <linux/init.h>
35#include <linux/gpio.h>
36#include <linux/device.h>
37#include <linux/platform_device.h>
38#include <linux/proc_fs.h>
39#include <linux/serial_core.h>
40#include <linux/io.h>
41
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/flash.h>
46
47#include <mach/hardware.h>
48#include <asm/irq.h>
49#include <asm/mach-types.h>
50#include <mach/fb.h>
51
52#include <plat/regs-serial.h>
53#include <mach/regs-lcd.h>
54#include <mach/regs-gpio.h>
55
56#include <plat/iic.h>
57#include <plat/devs.h>
58#include <plat/cpu.h>
59#include <plat/gpio-cfg.h>
60
61#include <linux/mtd/mtd.h>
62#include <linux/mtd/partitions.h>
63#include <linux/mtd/map.h>
64#include <linux/mtd/physmap.h>
65
66#include "common.h"
67
68static struct resource amlm5900_nor_resource = {
69 .start = 0x00000000,
70 .end = 0x01000000 - 1,
71 .flags = IORESOURCE_MEM,
72};
73
74
75
76static struct mtd_partition amlm5900_mtd_partitions[] = {
77 {
78 .name = "System",
79 .size = 0x240000,
80 .offset = 0,
81 .mask_flags = MTD_WRITEABLE, /* force read-only */
82 }, {
83 .name = "Kernel",
84 .size = 0x100000,
85 .offset = MTDPART_OFS_APPEND,
86 }, {
87 .name = "Ramdisk",
88 .size = 0x300000,
89 .offset = MTDPART_OFS_APPEND,
90 }, {
91 .name = "JFFS2",
92 .size = 0x9A0000,
93 .offset = MTDPART_OFS_APPEND,
94 }, {
95 .name = "Settings",
96 .size = MTDPART_SIZ_FULL,
97 .offset = MTDPART_OFS_APPEND,
98 }
99};
100
101static struct physmap_flash_data amlm5900_flash_data = {
102 .width = 2,
103 .parts = amlm5900_mtd_partitions,
104 .nr_parts = ARRAY_SIZE(amlm5900_mtd_partitions),
105};
106
107static struct platform_device amlm5900_device_nor = {
108 .name = "physmap-flash",
109 .id = 0,
110 .dev = {
111 .platform_data = &amlm5900_flash_data,
112 },
113 .num_resources = 1,
114 .resource = &amlm5900_nor_resource,
115};
116
117static struct map_desc amlm5900_iodesc[] __initdata = {
118};
119
120#define UCON S3C2410_UCON_DEFAULT
121#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
122#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
123
124static struct s3c2410_uartcfg amlm5900_uartcfgs[] = {
125 [0] = {
126 .hwport = 0,
127 .flags = 0,
128 .ucon = UCON,
129 .ulcon = ULCON,
130 .ufcon = UFCON,
131 },
132 [1] = {
133 .hwport = 1,
134 .flags = 0,
135 .ucon = UCON,
136 .ulcon = ULCON,
137 .ufcon = UFCON,
138 },
139 [2] = {
140 .hwport = 2,
141 .flags = 0,
142 .ucon = UCON,
143 .ulcon = ULCON,
144 .ufcon = UFCON,
145 }
146};
147
148
149static struct platform_device *amlm5900_devices[] __initdata = {
150#ifdef CONFIG_FB_S3C2410
151 &s3c_device_lcd,
152#endif
153 &s3c_device_adc,
154 &s3c_device_wdt,
155 &s3c_device_i2c0,
156 &s3c_device_ohci,
157 &s3c_device_rtc,
158 &s3c_device_usbgadget,
159 &s3c_device_sdi,
160 &amlm5900_device_nor,
161};
162
163static void __init amlm5900_map_io(void)
164{
165 s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
166 s3c24xx_init_clocks(0);
167 s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
168}
169
170#ifdef CONFIG_FB_S3C2410
171static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
172 .width = 160,
173 .height = 160,
174
175 .type = S3C2410_LCDCON1_STN4,
176
177 .pixclock = 680000, /* HCLK = 100MHz */
178 .xres = 160,
179 .yres = 160,
180 .bpp = 4,
181 .left_margin = 1 << (4 + 3),
182 .right_margin = 8 << 3,
183 .hsync_len = 48,
184 .upper_margin = 0,
185 .lower_margin = 0,
186
187 .lcdcon5 = 0x00000001,
188};
189
190static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = {
191
192 .displays = &amlm5900_lcd_info,
193 .num_displays = 1,
194 .default_display = 0,
195
196 .gpccon = 0xaaaaaaaa,
197 .gpccon_mask = 0xffffffff,
198 .gpcup = 0x0000ffff,
199 .gpcup_mask = 0xffffffff,
200
201 .gpdcon = 0xaaaaaaaa,
202 .gpdcon_mask = 0xffffffff,
203 .gpdup = 0x0000ffff,
204 .gpdup_mask = 0xffffffff,
205};
206#endif
207
208static irqreturn_t
209amlm5900_wake_interrupt(int irq, void *ignored)
210{
211 return IRQ_HANDLED;
212}
213
214static void amlm5900_init_pm(void)
215{
216 int ret = 0;
217
218 ret = request_irq(IRQ_EINT9, &amlm5900_wake_interrupt,
219 IRQF_TRIGGER_RISING | IRQF_SHARED,
220 "amlm5900_wakeup", &amlm5900_wake_interrupt);
221 if (ret != 0) {
222 printk(KERN_ERR "AML-M5900: no wakeup irq, %d?\n", ret);
223 } else {
224 enable_irq_wake(IRQ_EINT9);
225 /* configure the suspend/resume status pin */
226 s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
227 s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_UP);
228 }
229}
230static void __init amlm5900_init(void)
231{
232 amlm5900_init_pm();
233#ifdef CONFIG_FB_S3C2410
234 s3c24xx_fb_set_platdata(&amlm5900_fb_info);
235#endif
236 s3c_i2c0_set_platdata(NULL);
237 platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
238}
239
240MACHINE_START(AML_M5900, "AML_M5900")
241 .atag_offset = 0x100,
242 .map_io = amlm5900_map_io,
243 .init_irq = s3c24xx_init_irq,
244 .init_machine = amlm5900_init,
245 .timer = &s3c24xx_timer,
246 .restart = s3c2410_restart,
247MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
deleted file mode 100644
index feeaf73933dc..000000000000
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ /dev/null
@@ -1,645 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright 2003-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/syscore_ops.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/dm9000.h>
24#include <linux/ata_platform.h>
25#include <linux/i2c.h>
26#include <linux/io.h>
27
28#include <net/ax88796.h>
29
30#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
34#include <mach/bast-map.h>
35#include <mach/bast-irq.h>
36#include <mach/bast-cpld.h>
37
38#include <mach/hardware.h>
39#include <asm/irq.h>
40#include <asm/mach-types.h>
41
42//#include <asm/debug-ll.h>
43#include <plat/regs-serial.h>
44#include <mach/regs-gpio.h>
45#include <mach/regs-mem.h>
46#include <mach/regs-lcd.h>
47
48#include <plat/hwmon.h>
49#include <plat/nand.h>
50#include <plat/iic.h>
51#include <mach/fb.h>
52
53#include <linux/mtd/mtd.h>
54#include <linux/mtd/nand.h>
55#include <linux/mtd/nand_ecc.h>
56#include <linux/mtd/partitions.h>
57
58#include <linux/serial_8250.h>
59
60#include <plat/clock.h>
61#include <plat/devs.h>
62#include <plat/cpu.h>
63#include <plat/cpu-freq.h>
64#include <plat/gpio-cfg.h>
65#include <plat/audio-simtec.h>
66
67#include "usb-simtec.h"
68#include "nor-simtec.h"
69#include "common.h"
70
71#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
72
73/* macros for virtual address mods for the io space entries */
74#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
75#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
76#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
77#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
78
79/* macros to modify the physical addresses for io space */
80
81#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
82#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
83#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
84#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
85
86static struct map_desc bast_iodesc[] __initdata = {
87 /* ISA IO areas */
88 {
89 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
90 .pfn = PA_CS2(BAST_PA_ISAIO),
91 .length = SZ_16M,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (u32)S3C24XX_VA_ISA_WORD,
95 .pfn = PA_CS3(BAST_PA_ISAIO),
96 .length = SZ_16M,
97 .type = MT_DEVICE,
98 },
99 /* bast CPLD control registers, and external interrupt controls */
100 {
101 .virtual = (u32)BAST_VA_CTRL1,
102 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
103 .length = SZ_1M,
104 .type = MT_DEVICE,
105 }, {
106 .virtual = (u32)BAST_VA_CTRL2,
107 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
108 .length = SZ_1M,
109 .type = MT_DEVICE,
110 }, {
111 .virtual = (u32)BAST_VA_CTRL3,
112 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
113 .length = SZ_1M,
114 .type = MT_DEVICE,
115 }, {
116 .virtual = (u32)BAST_VA_CTRL4,
117 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
118 .length = SZ_1M,
119 .type = MT_DEVICE,
120 },
121 /* PC104 IRQ mux */
122 {
123 .virtual = (u32)BAST_VA_PC104_IRQREQ,
124 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
125 .length = SZ_1M,
126 .type = MT_DEVICE,
127 }, {
128 .virtual = (u32)BAST_VA_PC104_IRQRAW,
129 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
130 .length = SZ_1M,
131 .type = MT_DEVICE,
132 }, {
133 .virtual = (u32)BAST_VA_PC104_IRQMASK,
134 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
135 .length = SZ_1M,
136 .type = MT_DEVICE,
137 },
138
139 /* peripheral space... one for each of fast/slow/byte/16bit */
140 /* note, ide is only decoded in word space, even though some registers
141 * are only 8bit */
142
143 /* slow, byte */
144 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
145 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
146 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
147
148 /* slow, word */
149 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
150 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
151 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
152
153 /* fast, byte */
154 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
155 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
156 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
157
158 /* fast, word */
159 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
160 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
161 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
162};
163
164#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
165#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
166#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
167
168static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
169 [0] = {
170 .hwport = 0,
171 .flags = 0,
172 .ucon = UCON,
173 .ulcon = ULCON,
174 .ufcon = UFCON,
175 },
176 [1] = {
177 .hwport = 1,
178 .flags = 0,
179 .ucon = UCON,
180 .ulcon = ULCON,
181 .ufcon = UFCON,
182 },
183 /* port 2 is not actually used */
184 [2] = {
185 .hwport = 2,
186 .flags = 0,
187 .ucon = UCON,
188 .ulcon = ULCON,
189 .ufcon = UFCON,
190 }
191};
192
193/* NAND Flash on BAST board */
194
195#ifdef CONFIG_PM
196static int bast_pm_suspend(void)
197{
198 /* ensure that an nRESET is not generated on resume. */
199 gpio_direction_output(S3C2410_GPA(21), 1);
200 return 0;
201}
202
203static void bast_pm_resume(void)
204{
205 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
206}
207
208#else
209#define bast_pm_suspend NULL
210#define bast_pm_resume NULL
211#endif
212
213static struct syscore_ops bast_pm_syscore_ops = {
214 .suspend = bast_pm_suspend,
215 .resume = bast_pm_resume,
216};
217
218static int smartmedia_map[] = { 0 };
219static int chip0_map[] = { 1 };
220static int chip1_map[] = { 2 };
221static int chip2_map[] = { 3 };
222
223static struct mtd_partition __initdata bast_default_nand_part[] = {
224 [0] = {
225 .name = "Boot Agent",
226 .size = SZ_16K,
227 .offset = 0,
228 },
229 [1] = {
230 .name = "/boot",
231 .size = SZ_4M - SZ_16K,
232 .offset = SZ_16K,
233 },
234 [2] = {
235 .name = "user",
236 .offset = SZ_4M,
237 .size = MTDPART_SIZ_FULL,
238 }
239};
240
241/* the bast has 4 selectable slots for nand-flash, the three
242 * on-board chip areas, as well as the external SmartMedia
243 * slot.
244 *
245 * Note, there is no current hot-plug support for the SmartMedia
246 * socket.
247*/
248
249static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
250 [0] = {
251 .name = "SmartMedia",
252 .nr_chips = 1,
253 .nr_map = smartmedia_map,
254 .options = NAND_SCAN_SILENT_NODEV,
255 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
256 .partitions = bast_default_nand_part,
257 },
258 [1] = {
259 .name = "chip0",
260 .nr_chips = 1,
261 .nr_map = chip0_map,
262 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
263 .partitions = bast_default_nand_part,
264 },
265 [2] = {
266 .name = "chip1",
267 .nr_chips = 1,
268 .nr_map = chip1_map,
269 .options = NAND_SCAN_SILENT_NODEV,
270 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
271 .partitions = bast_default_nand_part,
272 },
273 [3] = {
274 .name = "chip2",
275 .nr_chips = 1,
276 .nr_map = chip2_map,
277 .options = NAND_SCAN_SILENT_NODEV,
278 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
279 .partitions = bast_default_nand_part,
280 }
281};
282
283static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
284{
285 unsigned int tmp;
286
287 slot = set->nr_map[slot] & 3;
288
289 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
290 slot, set, set->nr_map);
291
292 tmp = __raw_readb(BAST_VA_CTRL2);
293 tmp &= BAST_CPLD_CTLR2_IDERST;
294 tmp |= slot;
295 tmp |= BAST_CPLD_CTRL2_WNAND;
296
297 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
298
299 __raw_writeb(tmp, BAST_VA_CTRL2);
300}
301
302static struct s3c2410_platform_nand __initdata bast_nand_info = {
303 .tacls = 30,
304 .twrph0 = 60,
305 .twrph1 = 60,
306 .nr_sets = ARRAY_SIZE(bast_nand_sets),
307 .sets = bast_nand_sets,
308 .select_chip = bast_nand_select,
309};
310
311/* DM9000 */
312
313static struct resource bast_dm9k_resource[] = {
314 [0] = {
315 .start = S3C2410_CS5 + BAST_PA_DM9000,
316 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
317 .flags = IORESOURCE_MEM,
318 },
319 [1] = {
320 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
321 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
322 .flags = IORESOURCE_MEM,
323 },
324 [2] = {
325 .start = IRQ_DM9000,
326 .end = IRQ_DM9000,
327 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
328 }
329
330};
331
332/* for the moment we limit ourselves to 16bit IO until some
333 * better IO routines can be written and tested
334*/
335
336static struct dm9000_plat_data bast_dm9k_platdata = {
337 .flags = DM9000_PLATF_16BITONLY,
338};
339
340static struct platform_device bast_device_dm9k = {
341 .name = "dm9000",
342 .id = 0,
343 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
344 .resource = bast_dm9k_resource,
345 .dev = {
346 .platform_data = &bast_dm9k_platdata,
347 }
348};
349
350/* serial devices */
351
352#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
353#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
354#define SERIAL_CLK (1843200)
355
356static struct plat_serial8250_port bast_sio_data[] = {
357 [0] = {
358 .mapbase = SERIAL_BASE + 0x2f8,
359 .irq = IRQ_PCSERIAL1,
360 .flags = SERIAL_FLAGS,
361 .iotype = UPIO_MEM,
362 .regshift = 0,
363 .uartclk = SERIAL_CLK,
364 },
365 [1] = {
366 .mapbase = SERIAL_BASE + 0x3f8,
367 .irq = IRQ_PCSERIAL2,
368 .flags = SERIAL_FLAGS,
369 .iotype = UPIO_MEM,
370 .regshift = 0,
371 .uartclk = SERIAL_CLK,
372 },
373 { }
374};
375
376static struct platform_device bast_sio = {
377 .name = "serial8250",
378 .id = PLAT8250_DEV_PLATFORM,
379 .dev = {
380 .platform_data = &bast_sio_data,
381 },
382};
383
384/* we have devices on the bus which cannot work much over the
385 * standard 100KHz i2c bus frequency
386*/
387
388static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
389 .flags = 0,
390 .slave_addr = 0x10,
391 .frequency = 100*1000,
392};
393
394/* Asix AX88796 10/100 ethernet controller */
395
396static struct ax_plat_data bast_asix_platdata = {
397 .flags = AXFLG_MAC_FROMDEV,
398 .wordlength = 2,
399 .dcr_val = 0x48,
400 .rcr_val = 0x40,
401};
402
403static struct resource bast_asix_resource[] = {
404 [0] = {
405 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
406 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
407 .flags = IORESOURCE_MEM,
408 },
409 [1] = {
410 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
411 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
412 .flags = IORESOURCE_MEM,
413 },
414 [2] = {
415 .start = IRQ_ASIX,
416 .end = IRQ_ASIX,
417 .flags = IORESOURCE_IRQ
418 }
419};
420
421static struct platform_device bast_device_asix = {
422 .name = "ax88796",
423 .id = 0,
424 .num_resources = ARRAY_SIZE(bast_asix_resource),
425 .resource = bast_asix_resource,
426 .dev = {
427 .platform_data = &bast_asix_platdata
428 }
429};
430
431/* Asix AX88796 10/100 ethernet controller parallel port */
432
433static struct resource bast_asixpp_resource[] = {
434 [0] = {
435 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
436 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
437 .flags = IORESOURCE_MEM,
438 }
439};
440
441static struct platform_device bast_device_axpp = {
442 .name = "ax88796-pp",
443 .id = 0,
444 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
445 .resource = bast_asixpp_resource,
446};
447
448/* LCD/VGA controller */
449
450static struct s3c2410fb_display __initdata bast_lcd_info[] = {
451 {
452 .type = S3C2410_LCDCON1_TFT,
453 .width = 640,
454 .height = 480,
455
456 .pixclock = 33333,
457 .xres = 640,
458 .yres = 480,
459 .bpp = 4,
460 .left_margin = 40,
461 .right_margin = 20,
462 .hsync_len = 88,
463 .upper_margin = 30,
464 .lower_margin = 32,
465 .vsync_len = 3,
466
467 .lcdcon5 = 0x00014b02,
468 },
469 {
470 .type = S3C2410_LCDCON1_TFT,
471 .width = 640,
472 .height = 480,
473
474 .pixclock = 33333,
475 .xres = 640,
476 .yres = 480,
477 .bpp = 8,
478 .left_margin = 40,
479 .right_margin = 20,
480 .hsync_len = 88,
481 .upper_margin = 30,
482 .lower_margin = 32,
483 .vsync_len = 3,
484
485 .lcdcon5 = 0x00014b02,
486 },
487 {
488 .type = S3C2410_LCDCON1_TFT,
489 .width = 640,
490 .height = 480,
491
492 .pixclock = 33333,
493 .xres = 640,
494 .yres = 480,
495 .bpp = 16,
496 .left_margin = 40,
497 .right_margin = 20,
498 .hsync_len = 88,
499 .upper_margin = 30,
500 .lower_margin = 32,
501 .vsync_len = 3,
502
503 .lcdcon5 = 0x00014b02,
504 },
505};
506
507/* LCD/VGA controller */
508
509static struct s3c2410fb_mach_info __initdata bast_fb_info = {
510
511 .displays = bast_lcd_info,
512 .num_displays = ARRAY_SIZE(bast_lcd_info),
513 .default_display = 1,
514};
515
516/* I2C devices fitted. */
517
518static struct i2c_board_info bast_i2c_devs[] __initdata = {
519 {
520 I2C_BOARD_INFO("tlv320aic23", 0x1a),
521 }, {
522 I2C_BOARD_INFO("simtec-pmu", 0x6b),
523 }, {
524 I2C_BOARD_INFO("ch7013", 0x75),
525 },
526};
527
528static struct s3c_hwmon_pdata bast_hwmon_info = {
529 /* LCD contrast (0-6.6V) */
530 .in[0] = &(struct s3c_hwmon_chcfg) {
531 .name = "lcd-contrast",
532 .mult = 3300,
533 .div = 512,
534 },
535 /* LED current feedback */
536 .in[1] = &(struct s3c_hwmon_chcfg) {
537 .name = "led-feedback",
538 .mult = 3300,
539 .div = 1024,
540 },
541 /* LCD feedback (0-6.6V) */
542 .in[2] = &(struct s3c_hwmon_chcfg) {
543 .name = "lcd-feedback",
544 .mult = 3300,
545 .div = 512,
546 },
547 /* Vcore (1.8-2.0V), Vref 3.3V */
548 .in[3] = &(struct s3c_hwmon_chcfg) {
549 .name = "vcore",
550 .mult = 3300,
551 .div = 1024,
552 },
553};
554
555/* Standard BAST devices */
556// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
557
558static struct platform_device *bast_devices[] __initdata = {
559 &s3c_device_ohci,
560 &s3c_device_lcd,
561 &s3c_device_wdt,
562 &s3c_device_i2c0,
563 &s3c_device_rtc,
564 &s3c_device_nand,
565 &s3c_device_adc,
566 &s3c_device_hwmon,
567 &bast_device_dm9k,
568 &bast_device_asix,
569 &bast_device_axpp,
570 &bast_sio,
571};
572
573static struct clk *bast_clocks[] __initdata = {
574 &s3c24xx_dclk0,
575 &s3c24xx_dclk1,
576 &s3c24xx_clkout0,
577 &s3c24xx_clkout1,
578 &s3c24xx_uclk,
579};
580
581static struct s3c_cpufreq_board __initdata bast_cpufreq = {
582 .refresh = 7800, /* 7.8usec */
583 .auto_io = 1,
584 .need_io = 1,
585};
586
587static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
588 .have_mic = 1,
589 .have_lout = 1,
590};
591
592static void __init bast_map_io(void)
593{
594 /* initialise the clocks */
595
596 s3c24xx_dclk0.parent = &clk_upll;
597 s3c24xx_dclk0.rate = 12*1000*1000;
598
599 s3c24xx_dclk1.parent = &clk_upll;
600 s3c24xx_dclk1.rate = 24*1000*1000;
601
602 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
603 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
604
605 s3c24xx_uclk.parent = &s3c24xx_clkout1;
606
607 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
608
609 s3c_hwmon_set_platdata(&bast_hwmon_info);
610
611 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
612 s3c24xx_init_clocks(0);
613 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
614}
615
616static void __init bast_init(void)
617{
618 register_syscore_ops(&bast_pm_syscore_ops);
619
620 s3c_i2c0_set_platdata(&bast_i2c_info);
621 s3c_nand_set_platdata(&bast_nand_info);
622 s3c24xx_fb_set_platdata(&bast_fb_info);
623 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
624
625 i2c_register_board_info(0, bast_i2c_devs,
626 ARRAY_SIZE(bast_i2c_devs));
627
628 usb_simtec_init();
629 nor_simtec_init();
630 simtec_audio_add(NULL, true, &bast_audio);
631
632 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
633
634 s3c_cpufreq_setboard(&bast_cpufreq);
635}
636
637MACHINE_START(BAST, "Simtec-BAST")
638 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
639 .atag_offset = 0x100,
640 .map_io = bast_map_io,
641 .init_irq = s3c24xx_init_irq,
642 .init_machine = bast_init,
643 .timer = &s3c24xx_timer,
644 .restart = s3c2410_restart,
645MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
deleted file mode 100644
index 41245a603981..000000000000
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ /dev/null
@@ -1,757 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-h1940.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.handhelds.org/projects/h1940.html
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/memblock.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/device.h>
22#include <linux/serial_core.h>
23#include <linux/platform_device.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
26#include <linux/input.h>
27#include <linux/gpio_keys.h>
28#include <linux/pwm_backlight.h>
29#include <linux/i2c.h>
30#include <linux/leds.h>
31#include <linux/pda_power.h>
32#include <linux/s3c_adc_battery.h>
33#include <linux/delay.h>
34
35#include <video/platform_lcd.h>
36
37#include <linux/mmc/host.h>
38#include <linux/export.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43
44#include <mach/hardware.h>
45#include <asm/irq.h>
46#include <asm/mach-types.h>
47
48#include <plat/regs-serial.h>
49#include <mach/regs-lcd.h>
50#include <mach/regs-clock.h>
51
52#include <mach/regs-gpio.h>
53#include <mach/gpio-fns.h>
54#include <mach/gpio-nrs.h>
55
56#include <mach/h1940.h>
57#include <mach/h1940-latch.h>
58#include <mach/fb.h>
59#include <plat/udc.h>
60#include <plat/iic.h>
61
62#include <plat/gpio-cfg.h>
63#include <plat/clock.h>
64#include <plat/devs.h>
65#include <plat/cpu.h>
66#include <plat/pll.h>
67#include <plat/pm.h>
68#include <plat/mci.h>
69#include <plat/ts.h>
70
71#include <sound/uda1380.h>
72
73#include "common.h"
74
75#define H1940_LATCH ((void __force __iomem *)0xF8000000)
76
77#define H1940_PA_LATCH S3C2410_CS2
78
79#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END))
80
81static struct map_desc h1940_iodesc[] __initdata = {
82 [0] = {
83 .virtual = (unsigned long)H1940_LATCH,
84 .pfn = __phys_to_pfn(H1940_PA_LATCH),
85 .length = SZ_16K,
86 .type = MT_DEVICE
87 },
88};
89
90#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
91#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
92#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
93
94static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
95 [0] = {
96 .hwport = 0,
97 .flags = 0,
98 .ucon = 0x3c5,
99 .ulcon = 0x03,
100 .ufcon = 0x51,
101 },
102 [1] = {
103 .hwport = 1,
104 .flags = 0,
105 .ucon = 0x245,
106 .ulcon = 0x03,
107 .ufcon = 0x00,
108 },
109 /* IR port */
110 [2] = {
111 .hwport = 2,
112 .flags = 0,
113 .uart_flags = UPF_CONS_FLOW,
114 .ucon = 0x3c5,
115 .ulcon = 0x43,
116 .ufcon = 0x51,
117 }
118};
119
120/* Board control latch control */
121
122static unsigned int latch_state;
123
124static void h1940_latch_control(unsigned int clear, unsigned int set)
125{
126 unsigned long flags;
127
128 local_irq_save(flags);
129
130 latch_state &= ~clear;
131 latch_state |= set;
132
133 __raw_writel(latch_state, H1940_LATCH);
134
135 local_irq_restore(flags);
136}
137
138static inline int h1940_gpiolib_to_latch(int offset)
139{
140 return 1 << (offset + 16);
141}
142
143static void h1940_gpiolib_latch_set(struct gpio_chip *chip,
144 unsigned offset, int value)
145{
146 int latch_bit = h1940_gpiolib_to_latch(offset);
147
148 h1940_latch_control(value ? 0 : latch_bit,
149 value ? latch_bit : 0);
150}
151
152static int h1940_gpiolib_latch_output(struct gpio_chip *chip,
153 unsigned offset, int value)
154{
155 h1940_gpiolib_latch_set(chip, offset, value);
156 return 0;
157}
158
159static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
160 unsigned offset)
161{
162 return (latch_state >> (offset + 16)) & 1;
163}
164
165struct gpio_chip h1940_latch_gpiochip = {
166 .base = H1940_LATCH_GPIO(0),
167 .owner = THIS_MODULE,
168 .label = "H1940_LATCH",
169 .ngpio = 16,
170 .direction_output = h1940_gpiolib_latch_output,
171 .set = h1940_gpiolib_latch_set,
172 .get = h1940_gpiolib_latch_get,
173};
174
175static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
176 .vbus_pin = S3C2410_GPG(5),
177 .vbus_pin_inverted = 1,
178 .pullup_pin = H1940_LATCH_USB_DP,
179};
180
181static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
182 .delay = 10000,
183 .presc = 49,
184 .oversampling_shift = 2,
185 .cfg_gpio = s3c24xx_ts_cfg_gpio,
186};
187
188/**
189 * Set lcd on or off
190 **/
191static struct s3c2410fb_display h1940_lcd __initdata = {
192 .lcdcon5= S3C2410_LCDCON5_FRM565 | \
193 S3C2410_LCDCON5_INVVLINE | \
194 S3C2410_LCDCON5_HWSWP,
195
196 .type = S3C2410_LCDCON1_TFT,
197 .width = 240,
198 .height = 320,
199 .pixclock = 260000,
200 .xres = 240,
201 .yres = 320,
202 .bpp = 16,
203 .left_margin = 8,
204 .right_margin = 20,
205 .hsync_len = 4,
206 .upper_margin = 8,
207 .lower_margin = 7,
208 .vsync_len = 1,
209};
210
211static struct s3c2410fb_mach_info h1940_fb_info __initdata = {
212 .displays = &h1940_lcd,
213 .num_displays = 1,
214 .default_display = 0,
215
216 .lpcsel = 0x02,
217 .gpccon = 0xaa940659,
218 .gpccon_mask = 0xffffc0f0,
219 .gpcup = 0x0000ffff,
220 .gpcup_mask = 0xffffffff,
221 .gpdcon = 0xaa84aaa0,
222 .gpdcon_mask = 0xffffffff,
223 .gpdup = 0x0000faff,
224 .gpdup_mask = 0xffffffff,
225};
226
227static int power_supply_init(struct device *dev)
228{
229 return gpio_request(S3C2410_GPF(2), "cable plugged");
230}
231
232static int h1940_is_ac_online(void)
233{
234 return !gpio_get_value(S3C2410_GPF(2));
235}
236
237static void power_supply_exit(struct device *dev)
238{
239 gpio_free(S3C2410_GPF(2));
240}
241
242static char *h1940_supplicants[] = {
243 "main-battery",
244 "backup-battery",
245};
246
247static struct pda_power_pdata power_supply_info = {
248 .init = power_supply_init,
249 .is_ac_online = h1940_is_ac_online,
250 .exit = power_supply_exit,
251 .supplied_to = h1940_supplicants,
252 .num_supplicants = ARRAY_SIZE(h1940_supplicants),
253};
254
255static struct resource power_supply_resources[] = {
256 [0] = {
257 .name = "ac",
258 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
259 IORESOURCE_IRQ_HIGHEDGE,
260 .start = IRQ_EINT2,
261 .end = IRQ_EINT2,
262 },
263};
264
265static struct platform_device power_supply = {
266 .name = "pda-power",
267 .id = -1,
268 .dev = {
269 .platform_data =
270 &power_supply_info,
271 },
272 .resource = power_supply_resources,
273 .num_resources = ARRAY_SIZE(power_supply_resources),
274};
275
276static const struct s3c_adc_bat_thresh bat_lut_noac[] = {
277 { .volt = 4070, .cur = 162, .level = 100},
278 { .volt = 4040, .cur = 165, .level = 95},
279 { .volt = 4016, .cur = 164, .level = 90},
280 { .volt = 3996, .cur = 166, .level = 85},
281 { .volt = 3971, .cur = 168, .level = 80},
282 { .volt = 3951, .cur = 168, .level = 75},
283 { .volt = 3931, .cur = 170, .level = 70},
284 { .volt = 3903, .cur = 172, .level = 65},
285 { .volt = 3886, .cur = 172, .level = 60},
286 { .volt = 3858, .cur = 176, .level = 55},
287 { .volt = 3842, .cur = 176, .level = 50},
288 { .volt = 3818, .cur = 176, .level = 45},
289 { .volt = 3789, .cur = 180, .level = 40},
290 { .volt = 3769, .cur = 180, .level = 35},
291 { .volt = 3749, .cur = 184, .level = 30},
292 { .volt = 3732, .cur = 184, .level = 25},
293 { .volt = 3716, .cur = 184, .level = 20},
294 { .volt = 3708, .cur = 184, .level = 15},
295 { .volt = 3716, .cur = 96, .level = 10},
296 { .volt = 3700, .cur = 96, .level = 5},
297 { .volt = 3684, .cur = 96, .level = 0},
298};
299
300static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
301 { .volt = 4130, .cur = 0, .level = 100},
302 { .volt = 3982, .cur = 0, .level = 50},
303 { .volt = 3854, .cur = 0, .level = 10},
304 { .volt = 3841, .cur = 0, .level = 0},
305};
306
307int h1940_bat_init(void)
308{
309 int ret;
310
311 ret = gpio_request(H1940_LATCH_SM803_ENABLE, "h1940-charger-enable");
312 if (ret)
313 return ret;
314 gpio_direction_output(H1940_LATCH_SM803_ENABLE, 0);
315
316 return 0;
317
318}
319
320void h1940_bat_exit(void)
321{
322 gpio_free(H1940_LATCH_SM803_ENABLE);
323}
324
325void h1940_enable_charger(void)
326{
327 gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
328}
329
330void h1940_disable_charger(void)
331{
332 gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
333}
334
335static struct s3c_adc_bat_pdata h1940_bat_cfg = {
336 .init = h1940_bat_init,
337 .exit = h1940_bat_exit,
338 .enable_charger = h1940_enable_charger,
339 .disable_charger = h1940_disable_charger,
340 .gpio_charge_finished = S3C2410_GPF(3),
341 .gpio_inverted = 1,
342 .lut_noac = bat_lut_noac,
343 .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac),
344 .lut_acin = bat_lut_acin,
345 .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin),
346 .volt_channel = 0,
347 .current_channel = 1,
348 .volt_mult = 4056,
349 .current_mult = 1893,
350 .internal_impedance = 200,
351 .backup_volt_channel = 3,
352 /* TODO Check backup volt multiplier */
353 .backup_volt_mult = 4056,
354 .backup_volt_min = 0,
355 .backup_volt_max = 4149288
356};
357
358static struct platform_device h1940_battery = {
359 .name = "s3c-adc-battery",
360 .id = -1,
361 .dev = {
362 .parent = &s3c_device_adc.dev,
363 .platform_data = &h1940_bat_cfg,
364 },
365};
366
367DEFINE_SPINLOCK(h1940_blink_spin);
368
369int h1940_led_blink_set(unsigned gpio, int state,
370 unsigned long *delay_on, unsigned long *delay_off)
371{
372 int blink_gpio, check_gpio1, check_gpio2;
373
374 switch (gpio) {
375 case H1940_LATCH_LED_GREEN:
376 blink_gpio = S3C2410_GPA(7);
377 check_gpio1 = S3C2410_GPA(1);
378 check_gpio2 = S3C2410_GPA(3);
379 break;
380 case H1940_LATCH_LED_RED:
381 blink_gpio = S3C2410_GPA(1);
382 check_gpio1 = S3C2410_GPA(7);
383 check_gpio2 = S3C2410_GPA(3);
384 break;
385 default:
386 blink_gpio = S3C2410_GPA(3);
387 check_gpio1 = S3C2410_GPA(1);
388 check_gpio1 = S3C2410_GPA(7);
389 break;
390 }
391
392 if (delay_on && delay_off && !*delay_on && !*delay_off)
393 *delay_on = *delay_off = 500;
394
395 spin_lock(&h1940_blink_spin);
396
397 switch (state) {
398 case GPIO_LED_NO_BLINK_LOW:
399 case GPIO_LED_NO_BLINK_HIGH:
400 if (!gpio_get_value(check_gpio1) &&
401 !gpio_get_value(check_gpio2))
402 gpio_set_value(H1940_LATCH_LED_FLASH, 0);
403 gpio_set_value(blink_gpio, 0);
404 if (gpio_is_valid(gpio))
405 gpio_set_value(gpio, state);
406 break;
407 case GPIO_LED_BLINK:
408 if (gpio_is_valid(gpio))
409 gpio_set_value(gpio, 0);
410 gpio_set_value(H1940_LATCH_LED_FLASH, 1);
411 gpio_set_value(blink_gpio, 1);
412 break;
413 }
414
415 spin_unlock(&h1940_blink_spin);
416
417 return 0;
418}
419EXPORT_SYMBOL(h1940_led_blink_set);
420
421static struct gpio_led h1940_leds_desc[] = {
422 {
423 .name = "Green",
424 .default_trigger = "main-battery-full",
425 .gpio = H1940_LATCH_LED_GREEN,
426 .retain_state_suspended = 1,
427 },
428 {
429 .name = "Red",
430 .default_trigger
431 = "main-battery-charging-blink-full-solid",
432 .gpio = H1940_LATCH_LED_RED,
433 .retain_state_suspended = 1,
434 },
435};
436
437static struct gpio_led_platform_data h1940_leds_pdata = {
438 .num_leds = ARRAY_SIZE(h1940_leds_desc),
439 .leds = h1940_leds_desc,
440 .gpio_blink_set = h1940_led_blink_set,
441};
442
443static struct platform_device h1940_device_leds = {
444 .name = "leds-gpio",
445 .id = -1,
446 .dev = {
447 .platform_data = &h1940_leds_pdata,
448 },
449};
450
451static struct platform_device h1940_device_bluetooth = {
452 .name = "h1940-bt",
453 .id = -1,
454};
455
456static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
457{
458 switch (power_mode) {
459 case MMC_POWER_OFF:
460 gpio_set_value(H1940_LATCH_SD_POWER, 0);
461 break;
462 case MMC_POWER_UP:
463 case MMC_POWER_ON:
464 gpio_set_value(H1940_LATCH_SD_POWER, 1);
465 break;
466 default:
467 break;
468 };
469}
470
471static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
472 .gpio_detect = S3C2410_GPF(5),
473 .gpio_wprotect = S3C2410_GPH(8),
474 .set_power = h1940_set_mmc_power,
475 .ocr_avail = MMC_VDD_32_33,
476};
477
478static int h1940_backlight_init(struct device *dev)
479{
480 gpio_request(S3C2410_GPB(0), "Backlight");
481
482 gpio_direction_output(S3C2410_GPB(0), 0);
483 s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
484 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
485 gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
486
487 return 0;
488}
489
490static int h1940_backlight_notify(struct device *dev, int brightness)
491{
492 if (!brightness) {
493 gpio_direction_output(S3C2410_GPB(0), 1);
494 gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
495 } else {
496 gpio_direction_output(S3C2410_GPB(0), 0);
497 s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
498 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
499 gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
500 }
501 return brightness;
502}
503
504static void h1940_backlight_exit(struct device *dev)
505{
506 gpio_direction_output(S3C2410_GPB(0), 1);
507 gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
508}
509
510
511static struct platform_pwm_backlight_data backlight_data = {
512 .pwm_id = 0,
513 .max_brightness = 100,
514 .dft_brightness = 50,
515 /* tcnt = 0x31 */
516 .pwm_period_ns = 36296,
517 .init = h1940_backlight_init,
518 .notify = h1940_backlight_notify,
519 .exit = h1940_backlight_exit,
520};
521
522static struct platform_device h1940_backlight = {
523 .name = "pwm-backlight",
524 .dev = {
525 .parent = &s3c_device_timer[0].dev,
526 .platform_data = &backlight_data,
527 },
528 .id = -1,
529};
530
531static void h1940_lcd_power_set(struct plat_lcd_data *pd,
532 unsigned int power)
533{
534 int value, retries = 100;
535
536 if (!power) {
537 gpio_set_value(S3C2410_GPC(0), 0);
538 /* wait for 3ac */
539 do {
540 value = gpio_get_value(S3C2410_GPC(6));
541 } while (value && retries--);
542
543 gpio_set_value(H1940_LATCH_LCD_P2, 0);
544 gpio_set_value(H1940_LATCH_LCD_P3, 0);
545 gpio_set_value(H1940_LATCH_LCD_P4, 0);
546
547 gpio_direction_output(S3C2410_GPC(1), 0);
548 gpio_direction_output(S3C2410_GPC(4), 0);
549
550 gpio_set_value(H1940_LATCH_LCD_P1, 0);
551 gpio_set_value(H1940_LATCH_LCD_P0, 0);
552
553 gpio_set_value(S3C2410_GPC(5), 0);
554
555 } else {
556 gpio_set_value(H1940_LATCH_LCD_P0, 1);
557 gpio_set_value(H1940_LATCH_LCD_P1, 1);
558
559 gpio_direction_input(S3C2410_GPC(1));
560 gpio_direction_input(S3C2410_GPC(4));
561 mdelay(10);
562 s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2));
563 s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2));
564
565 gpio_set_value(S3C2410_GPC(5), 1);
566 gpio_set_value(S3C2410_GPC(0), 1);
567
568 gpio_set_value(H1940_LATCH_LCD_P3, 1);
569 gpio_set_value(H1940_LATCH_LCD_P2, 1);
570 gpio_set_value(H1940_LATCH_LCD_P4, 1);
571 }
572}
573
574static struct plat_lcd_data h1940_lcd_power_data = {
575 .set_power = h1940_lcd_power_set,
576};
577
578static struct platform_device h1940_lcd_powerdev = {
579 .name = "platform-lcd",
580 .dev.parent = &s3c_device_lcd.dev,
581 .dev.platform_data = &h1940_lcd_power_data,
582};
583
584static struct uda1380_platform_data uda1380_info = {
585 .gpio_power = H1940_LATCH_UDA_POWER,
586 .gpio_reset = S3C2410_GPA(12),
587 .dac_clk = UDA1380_DAC_CLK_SYSCLK,
588};
589
590static struct i2c_board_info h1940_i2c_devices[] = {
591 {
592 I2C_BOARD_INFO("uda1380", 0x1a),
593 .platform_data = &uda1380_info,
594 },
595};
596
597#define DECLARE_BUTTON(p, k, n, w) \
598 { \
599 .gpio = p, \
600 .code = k, \
601 .desc = n, \
602 .wakeup = w, \
603 .active_low = 1, \
604 }
605
606static struct gpio_keys_button h1940_buttons[] = {
607 DECLARE_BUTTON(S3C2410_GPF(0), KEY_POWER, "Power", 1),
608 DECLARE_BUTTON(S3C2410_GPF(6), KEY_ENTER, "Select", 1),
609 DECLARE_BUTTON(S3C2410_GPF(7), KEY_RECORD, "Record", 0),
610 DECLARE_BUTTON(S3C2410_GPG(0), KEY_F11, "Calendar", 0),
611 DECLARE_BUTTON(S3C2410_GPG(2), KEY_F12, "Contacts", 0),
612 DECLARE_BUTTON(S3C2410_GPG(3), KEY_MAIL, "Mail", 0),
613 DECLARE_BUTTON(S3C2410_GPG(6), KEY_LEFT, "Left_arrow", 0),
614 DECLARE_BUTTON(S3C2410_GPG(7), KEY_HOMEPAGE, "Home", 0),
615 DECLARE_BUTTON(S3C2410_GPG(8), KEY_RIGHT, "Right_arrow", 0),
616 DECLARE_BUTTON(S3C2410_GPG(9), KEY_UP, "Up_arrow", 0),
617 DECLARE_BUTTON(S3C2410_GPG(10), KEY_DOWN, "Down_arrow", 0),
618};
619
620static struct gpio_keys_platform_data h1940_buttons_data = {
621 .buttons = h1940_buttons,
622 .nbuttons = ARRAY_SIZE(h1940_buttons),
623};
624
625static struct platform_device h1940_dev_buttons = {
626 .name = "gpio-keys",
627 .id = -1,
628 .dev = {
629 .platform_data = &h1940_buttons_data,
630 }
631};
632
633static struct platform_device *h1940_devices[] __initdata = {
634 &h1940_dev_buttons,
635 &s3c_device_ohci,
636 &s3c_device_lcd,
637 &s3c_device_wdt,
638 &s3c_device_i2c0,
639 &s3c_device_iis,
640 &samsung_asoc_dma,
641 &s3c_device_usbgadget,
642 &h1940_device_leds,
643 &h1940_device_bluetooth,
644 &s3c_device_sdi,
645 &s3c_device_rtc,
646 &s3c_device_timer[0],
647 &h1940_backlight,
648 &h1940_lcd_powerdev,
649 &s3c_device_adc,
650 &s3c_device_ts,
651 &power_supply,
652 &h1940_battery,
653};
654
655static void __init h1940_map_io(void)
656{
657 s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
658 s3c24xx_init_clocks(0);
659 s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
660
661 /* setup PM */
662
663#ifdef CONFIG_PM_H1940
664 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
665#endif
666 s3c_pm_init();
667
668 /* Add latch gpio chip, set latch initial value */
669 h1940_latch_control(0, 0);
670 WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
671}
672
673/* H1940 and RX3715 need to reserve this for suspend */
674static void __init h1940_reserve(void)
675{
676 memblock_reserve(0x30003000, 0x1000);
677 memblock_reserve(0x30081000, 0x1000);
678}
679
680static void __init h1940_init_irq(void)
681{
682 s3c24xx_init_irq();
683}
684
685static void __init h1940_init(void)
686{
687 u32 tmp;
688
689 s3c24xx_fb_set_platdata(&h1940_fb_info);
690 s3c24xx_mci_set_platdata(&h1940_mmc_cfg);
691 s3c24xx_udc_set_platdata(&h1940_udc_cfg);
692 s3c24xx_ts_set_platdata(&h1940_ts_cfg);
693 s3c_i2c0_set_platdata(NULL);
694
695 /* Turn off suspend on both USB ports, and switch the
696 * selectable USB port to USB device mode. */
697
698 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
699 S3C2410_MISCCR_USBSUSPND0 |
700 S3C2410_MISCCR_USBSUSPND1, 0x0);
701
702 tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT)
703 | (0x02 << S3C24XX_PLL_PDIV_SHIFT)
704 | (0x03 << S3C24XX_PLL_SDIV_SHIFT);
705 writel(tmp, S3C2410_UPLLCON);
706
707 gpio_request(S3C2410_GPC(0), "LCD power");
708 gpio_request(S3C2410_GPC(1), "LCD power");
709 gpio_request(S3C2410_GPC(4), "LCD power");
710 gpio_request(S3C2410_GPC(5), "LCD power");
711 gpio_request(S3C2410_GPC(6), "LCD power");
712 gpio_request(H1940_LATCH_LCD_P0, "LCD power");
713 gpio_request(H1940_LATCH_LCD_P1, "LCD power");
714 gpio_request(H1940_LATCH_LCD_P2, "LCD power");
715 gpio_request(H1940_LATCH_LCD_P3, "LCD power");
716 gpio_request(H1940_LATCH_LCD_P4, "LCD power");
717 gpio_request(H1940_LATCH_MAX1698_nSHUTDOWN, "LCD power");
718 gpio_direction_output(S3C2410_GPC(0), 0);
719 gpio_direction_output(S3C2410_GPC(1), 0);
720 gpio_direction_output(S3C2410_GPC(4), 0);
721 gpio_direction_output(S3C2410_GPC(5), 0);
722 gpio_direction_input(S3C2410_GPC(6));
723 gpio_direction_output(H1940_LATCH_LCD_P0, 0);
724 gpio_direction_output(H1940_LATCH_LCD_P1, 0);
725 gpio_direction_output(H1940_LATCH_LCD_P2, 0);
726 gpio_direction_output(H1940_LATCH_LCD_P3, 0);
727 gpio_direction_output(H1940_LATCH_LCD_P4, 0);
728 gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
729
730 gpio_request(H1940_LATCH_SD_POWER, "SD power");
731 gpio_direction_output(H1940_LATCH_SD_POWER, 0);
732
733 platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
734
735 gpio_request(S3C2410_GPA(1), "Red LED blink");
736 gpio_request(S3C2410_GPA(3), "Blue LED blink");
737 gpio_request(S3C2410_GPA(7), "Green LED blink");
738 gpio_request(H1940_LATCH_LED_FLASH, "LED blink");
739 gpio_direction_output(S3C2410_GPA(1), 0);
740 gpio_direction_output(S3C2410_GPA(3), 0);
741 gpio_direction_output(S3C2410_GPA(7), 0);
742 gpio_direction_output(H1940_LATCH_LED_FLASH, 0);
743
744 i2c_register_board_info(0, h1940_i2c_devices,
745 ARRAY_SIZE(h1940_i2c_devices));
746}
747
748MACHINE_START(H1940, "IPAQ-H1940")
749 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
750 .atag_offset = 0x100,
751 .map_io = h1940_map_io,
752 .reserve = h1940_reserve,
753 .init_irq = h1940_init_irq,
754 .init_machine = h1940_init,
755 .timer = &s3c24xx_timer,
756 .restart = s3c2410_restart,
757MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
deleted file mode 100644
index 383d00ca8f60..000000000000
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ /dev/null
@@ -1,608 +0,0 @@
1/* Machine specific code for the Acer n30, Acer N35, Navman PiN 570,
2 * Yakumo AlphaX and Airis NC05 PDAs.
3 *
4 * Copyright (c) 2003-2005 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se>
8 *
9 * There is a wiki with more information about the n30 port at
10 * http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19
20#include <linux/gpio_keys.h>
21#include <linux/init.h>
22#include <linux/gpio.h>
23#include <linux/input.h>
24#include <linux/interrupt.h>
25#include <linux/platform_device.h>
26#include <linux/serial_core.h>
27#include <linux/timer.h>
28#include <linux/io.h>
29#include <linux/mmc/host.h>
30
31#include <mach/hardware.h>
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34
35#include <mach/fb.h>
36#include <mach/leds-gpio.h>
37#include <mach/regs-gpio.h>
38#include <mach/regs-lcd.h>
39
40#include <asm/mach/arch.h>
41#include <asm/mach/irq.h>
42#include <asm/mach/map.h>
43
44#include <plat/iic.h>
45#include <plat/regs-serial.h>
46
47#include <plat/clock.h>
48#include <plat/cpu.h>
49#include <plat/devs.h>
50#include <plat/mci.h>
51#include <plat/s3c2410.h>
52#include <plat/udc.h>
53
54#include "common.h"
55
56static struct map_desc n30_iodesc[] __initdata = {
57 /* nothing here yet */
58};
59
60static struct s3c2410_uartcfg n30_uartcfgs[] = {
61 /* Normal serial port */
62 [0] = {
63 .hwport = 0,
64 .flags = 0,
65 .ucon = 0x2c5,
66 .ulcon = 0x03,
67 .ufcon = 0x51,
68 },
69 /* IR port */
70 [1] = {
71 .hwport = 1,
72 .flags = 0,
73 .uart_flags = UPF_CONS_FLOW,
74 .ucon = 0x2c5,
75 .ulcon = 0x43,
76 .ufcon = 0x51,
77 },
78 /* On the N30 the bluetooth controller is connected here.
79 * On the N35 and variants the GPS receiver is connected here. */
80 [2] = {
81 .hwport = 2,
82 .flags = 0,
83 .ucon = 0x2c5,
84 .ulcon = 0x03,
85 .ufcon = 0x51,
86 },
87};
88
89static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
90 .vbus_pin = S3C2410_GPG(1),
91 .vbus_pin_inverted = 0,
92 .pullup_pin = S3C2410_GPB(3),
93};
94
95static struct gpio_keys_button n30_buttons[] = {
96 {
97 .gpio = S3C2410_GPF(0),
98 .code = KEY_POWER,
99 .desc = "Power",
100 .active_low = 0,
101 },
102 {
103 .gpio = S3C2410_GPG(9),
104 .code = KEY_UP,
105 .desc = "Thumbwheel Up",
106 .active_low = 0,
107 },
108 {
109 .gpio = S3C2410_GPG(8),
110 .code = KEY_DOWN,
111 .desc = "Thumbwheel Down",
112 .active_low = 0,
113 },
114 {
115 .gpio = S3C2410_GPG(7),
116 .code = KEY_ENTER,
117 .desc = "Thumbwheel Press",
118 .active_low = 0,
119 },
120 {
121 .gpio = S3C2410_GPF(7),
122 .code = KEY_HOMEPAGE,
123 .desc = "Home",
124 .active_low = 0,
125 },
126 {
127 .gpio = S3C2410_GPF(6),
128 .code = KEY_CALENDAR,
129 .desc = "Calendar",
130 .active_low = 0,
131 },
132 {
133 .gpio = S3C2410_GPF(5),
134 .code = KEY_ADDRESSBOOK,
135 .desc = "Contacts",
136 .active_low = 0,
137 },
138 {
139 .gpio = S3C2410_GPF(4),
140 .code = KEY_MAIL,
141 .desc = "Mail",
142 .active_low = 0,
143 },
144};
145
146static struct gpio_keys_platform_data n30_button_data = {
147 .buttons = n30_buttons,
148 .nbuttons = ARRAY_SIZE(n30_buttons),
149};
150
151static struct platform_device n30_button_device = {
152 .name = "gpio-keys",
153 .id = -1,
154 .dev = {
155 .platform_data = &n30_button_data,
156 }
157};
158
159static struct gpio_keys_button n35_buttons[] = {
160 {
161 .gpio = S3C2410_GPF(0),
162 .code = KEY_POWER,
163 .type = EV_PWR,
164 .desc = "Power",
165 .active_low = 0,
166 .wakeup = 1,
167 },
168 {
169 .gpio = S3C2410_GPG(9),
170 .code = KEY_UP,
171 .desc = "Joystick Up",
172 .active_low = 0,
173 },
174 {
175 .gpio = S3C2410_GPG(8),
176 .code = KEY_DOWN,
177 .desc = "Joystick Down",
178 .active_low = 0,
179 },
180 {
181 .gpio = S3C2410_GPG(6),
182 .code = KEY_DOWN,
183 .desc = "Joystick Left",
184 .active_low = 0,
185 },
186 {
187 .gpio = S3C2410_GPG(5),
188 .code = KEY_DOWN,
189 .desc = "Joystick Right",
190 .active_low = 0,
191 },
192 {
193 .gpio = S3C2410_GPG(7),
194 .code = KEY_ENTER,
195 .desc = "Joystick Press",
196 .active_low = 0,
197 },
198 {
199 .gpio = S3C2410_GPF(7),
200 .code = KEY_HOMEPAGE,
201 .desc = "Home",
202 .active_low = 0,
203 },
204 {
205 .gpio = S3C2410_GPF(6),
206 .code = KEY_CALENDAR,
207 .desc = "Calendar",
208 .active_low = 0,
209 },
210 {
211 .gpio = S3C2410_GPF(5),
212 .code = KEY_ADDRESSBOOK,
213 .desc = "Contacts",
214 .active_low = 0,
215 },
216 {
217 .gpio = S3C2410_GPF(4),
218 .code = KEY_MAIL,
219 .desc = "Mail",
220 .active_low = 0,
221 },
222 {
223 .gpio = S3C2410_GPF(3),
224 .code = SW_RADIO,
225 .desc = "GPS Antenna",
226 .active_low = 0,
227 },
228 {
229 .gpio = S3C2410_GPG(2),
230 .code = SW_HEADPHONE_INSERT,
231 .desc = "Headphone",
232 .active_low = 0,
233 },
234};
235
236static struct gpio_keys_platform_data n35_button_data = {
237 .buttons = n35_buttons,
238 .nbuttons = ARRAY_SIZE(n35_buttons),
239};
240
241static struct platform_device n35_button_device = {
242 .name = "gpio-keys",
243 .id = -1,
244 .num_resources = 0,
245 .dev = {
246 .platform_data = &n35_button_data,
247 }
248};
249
250/* This is the bluetooth LED on the device. */
251static struct s3c24xx_led_platdata n30_blue_led_pdata = {
252 .name = "blue_led",
253 .gpio = S3C2410_GPG(6),
254 .def_trigger = "",
255};
256
257/* This is the blue LED on the device. Originally used to indicate GPS activity
258 * by flashing. */
259static struct s3c24xx_led_platdata n35_blue_led_pdata = {
260 .name = "blue_led",
261 .gpio = S3C2410_GPD(8),
262 .def_trigger = "",
263};
264
265/* This LED is driven by the battery microcontroller, and is blinking
266 * red, blinking green or solid green when the battery is low,
267 * charging or full respectively. By driving GPD9 low, it's possible
268 * to force the LED to blink red, so call that warning LED. */
269static struct s3c24xx_led_platdata n30_warning_led_pdata = {
270 .name = "warning_led",
271 .flags = S3C24XX_LEDF_ACTLOW,
272 .gpio = S3C2410_GPD(9),
273 .def_trigger = "",
274};
275
276static struct s3c24xx_led_platdata n35_warning_led_pdata = {
277 .name = "warning_led",
278 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
279 .gpio = S3C2410_GPD(9),
280 .def_trigger = "",
281};
282
283static struct platform_device n30_blue_led = {
284 .name = "s3c24xx_led",
285 .id = 1,
286 .dev = {
287 .platform_data = &n30_blue_led_pdata,
288 },
289};
290
291static struct platform_device n35_blue_led = {
292 .name = "s3c24xx_led",
293 .id = 1,
294 .dev = {
295 .platform_data = &n35_blue_led_pdata,
296 },
297};
298
299static struct platform_device n30_warning_led = {
300 .name = "s3c24xx_led",
301 .id = 2,
302 .dev = {
303 .platform_data = &n30_warning_led_pdata,
304 },
305};
306
307static struct platform_device n35_warning_led = {
308 .name = "s3c24xx_led",
309 .id = 2,
310 .dev = {
311 .platform_data = &n35_warning_led_pdata,
312 },
313};
314
315static struct s3c2410fb_display n30_display __initdata = {
316 .type = S3C2410_LCDCON1_TFT,
317 .width = 240,
318 .height = 320,
319 .pixclock = 170000,
320
321 .xres = 240,
322 .yres = 320,
323 .bpp = 16,
324 .left_margin = 3,
325 .right_margin = 40,
326 .hsync_len = 40,
327 .upper_margin = 2,
328 .lower_margin = 3,
329 .vsync_len = 2,
330
331 .lcdcon5 = S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME,
332};
333
334static struct s3c2410fb_mach_info n30_fb_info __initdata = {
335 .displays = &n30_display,
336 .num_displays = 1,
337 .default_display = 0,
338 .lpcsel = 0x06,
339};
340
341static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
342{
343 switch (power_mode) {
344 case MMC_POWER_ON:
345 case MMC_POWER_UP:
346 gpio_set_value(S3C2410_GPG(4), 1);
347 break;
348 case MMC_POWER_OFF:
349 default:
350 gpio_set_value(S3C2410_GPG(4), 0);
351 break;
352 }
353}
354
355static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = {
356 .gpio_detect = S3C2410_GPF(1),
357 .gpio_wprotect = S3C2410_GPG(10),
358 .ocr_avail = MMC_VDD_32_33,
359 .set_power = n30_sdi_set_power,
360};
361
362static struct platform_device *n30_devices[] __initdata = {
363 &s3c_device_lcd,
364 &s3c_device_wdt,
365 &s3c_device_i2c0,
366 &s3c_device_iis,
367 &s3c_device_ohci,
368 &s3c_device_rtc,
369 &s3c_device_usbgadget,
370 &s3c_device_sdi,
371 &n30_button_device,
372 &n30_blue_led,
373 &n30_warning_led,
374};
375
376static struct platform_device *n35_devices[] __initdata = {
377 &s3c_device_lcd,
378 &s3c_device_wdt,
379 &s3c_device_i2c0,
380 &s3c_device_iis,
381 &s3c_device_rtc,
382 &s3c_device_usbgadget,
383 &s3c_device_sdi,
384 &n35_button_device,
385 &n35_blue_led,
386 &n35_warning_led,
387};
388
389static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
390 .flags = 0,
391 .slave_addr = 0x10,
392 .frequency = 10*1000,
393};
394
395/* Lots of hardcoded stuff, but it sets up the hardware in a useful
396 * state so that we can boot Linux directly from flash. */
397static void __init n30_hwinit(void)
398{
399 /* GPA0-11 special functions -- unknown what they do
400 * GPA12 N30 special function -- unknown what it does
401 * N35/PiN output -- unknown what it does
402 *
403 * A12 is nGCS1 on the N30 and an output on the N35/PiN. I
404 * don't think it does anything useful on the N30, so I ought
405 * to make it an output there too since it always driven to 0
406 * as far as I can tell. */
407 if (machine_is_n30())
408 __raw_writel(0x007fffff, S3C2410_GPACON);
409 if (machine_is_n35())
410 __raw_writel(0x007fefff, S3C2410_GPACON);
411 __raw_writel(0x00000000, S3C2410_GPADAT);
412
413 /* GPB0 TOUT0 backlight level
414 * GPB1 output 1=backlight on
415 * GPB2 output IrDA enable 0=transceiver enabled, 1=disabled
416 * GPB3 output USB D+ pull up 0=disabled, 1=enabled
417 * GPB4 N30 output -- unknown function
418 * N30/PiN GPS control 0=GPS enabled, 1=GPS disabled
419 * GPB5 output -- unknown function
420 * GPB6 input -- unknown function
421 * GPB7 output -- unknown function
422 * GPB8 output -- probably LCD driver enable
423 * GPB9 output -- probably LCD VSYNC driver enable
424 * GPB10 output -- probably LCD HSYNC driver enable
425 */
426 __raw_writel(0x00154556, S3C2410_GPBCON);
427 __raw_writel(0x00000750, S3C2410_GPBDAT);
428 __raw_writel(0x00000073, S3C2410_GPBUP);
429
430 /* GPC0 input RS232 DCD/DSR/RI
431 * GPC1 LCD
432 * GPC2 output RS232 DTR?
433 * GPC3 input RS232 DCD/DSR/RI
434 * GPC4 LCD
435 * GPC5 output 0=NAND write enabled, 1=NAND write protect
436 * GPC6 input -- unknown function
437 * GPC7 input charger status 0=charger connected
438 * this input can be triggered by power on the USB device
439 * port too, but will go back to disconnected soon after.
440 * GPC8 N30/N35 output -- unknown function, always driven to 1
441 * PiN input -- unknown function, always read as 1
442 * Make it an input with a pull up for all models.
443 * GPC9-15 LCD
444 */
445 __raw_writel(0xaaa80618, S3C2410_GPCCON);
446 __raw_writel(0x0000014c, S3C2410_GPCDAT);
447 __raw_writel(0x0000fef2, S3C2410_GPCUP);
448
449 /* GPD0 input -- unknown function
450 * GPD1-D7 LCD
451 * GPD8 N30 output -- unknown function
452 * N35/PiN output 1=GPS LED on
453 * GPD9 output 0=power led blinks red, 1=normal power led function
454 * GPD10 output -- unknown function
455 * GPD11-15 LCD drivers
456 */
457 __raw_writel(0xaa95aaa4, S3C2410_GPDCON);
458 __raw_writel(0x00000601, S3C2410_GPDDAT);
459 __raw_writel(0x0000fbfe, S3C2410_GPDUP);
460
461 /* GPE0-4 I2S audio bus
462 * GPE5-10 SD/MMC bus
463 * E11-13 outputs -- unknown function, probably power management
464 * E14-15 I2C bus connected to the battery controller
465 */
466 __raw_writel(0xa56aaaaa, S3C2410_GPECON);
467 __raw_writel(0x0000efc5, S3C2410_GPEDAT);
468 __raw_writel(0x0000f81f, S3C2410_GPEUP);
469
470 /* GPF0 input 0=power button pressed
471 * GPF1 input SD/MMC switch 0=card present
472 * GPF2 N30 1=reset button pressed (inverted compared to the rest)
473 * N35/PiN 0=reset button pressed
474 * GPF3 N30/PiN input -- unknown function
475 * N35 input GPS antenna position, 0=antenna closed, 1=open
476 * GPF4 input 0=button 4 pressed
477 * GPF5 input 0=button 3 pressed
478 * GPF6 input 0=button 2 pressed
479 * GPF7 input 0=button 1 pressed
480 */
481 __raw_writel(0x0000aaaa, S3C2410_GPFCON);
482 __raw_writel(0x00000000, S3C2410_GPFDAT);
483 __raw_writel(0x000000ff, S3C2410_GPFUP);
484
485 /* GPG0 input RS232 DCD/DSR/RI
486 * GPG1 input 1=USB gadget port has power from a host
487 * GPG2 N30 input -- unknown function
488 * N35/PiN input 0=headphones plugged in, 1=not plugged in
489 * GPG3 N30 output -- unknown function
490 * N35/PiN input with unknown function
491 * GPG4 N30 output 0=MMC enabled, 1=MMC disabled
492 * GPG5 N30 output 0=BlueTooth chip disabled, 1=enabled
493 * N35/PiN input joystick right
494 * GPG6 N30 output 0=blue led on, 1=off
495 * N35/PiN input joystick left
496 * GPG7 input 0=thumbwheel pressed
497 * GPG8 input 0=thumbwheel down
498 * GPG9 input 0=thumbwheel up
499 * GPG10 input SD/MMC write protect switch
500 * GPG11 N30 input -- unknown function
501 * N35 output 0=GPS antenna powered, 1=not powered
502 * PiN output -- unknown function
503 * GPG12-15 touch screen functions
504 *
505 * The pullups differ between the models, so enable all
506 * pullups that are enabled on any of the models.
507 */
508 if (machine_is_n30())
509 __raw_writel(0xff0a956a, S3C2410_GPGCON);
510 if (machine_is_n35())
511 __raw_writel(0xff4aa92a, S3C2410_GPGCON);
512 __raw_writel(0x0000e800, S3C2410_GPGDAT);
513 __raw_writel(0x0000f86f, S3C2410_GPGUP);
514
515 /* GPH0/1/2/3 RS232 serial port
516 * GPH4/5 IrDA serial port
517 * GPH6/7 N30 BlueTooth serial port
518 * N35/PiN GPS receiver
519 * GPH8 input -- unknown function
520 * GPH9 CLKOUT0 HCLK -- unknown use
521 * GPH10 CLKOUT1 FCLK -- unknown use
522 *
523 * The pull ups for H6/H7 are enabled on N30 but not on the
524 * N35/PiN. I suppose is useful for a budget model of the N30
525 * with no bluetooh. It doesn't hurt to have the pull ups
526 * enabled on the N35, so leave them enabled for all models.
527 */
528 __raw_writel(0x0028aaaa, S3C2410_GPHCON);
529 __raw_writel(0x000005ef, S3C2410_GPHDAT);
530 __raw_writel(0x0000063f, S3C2410_GPHUP);
531}
532
533static void __init n30_map_io(void)
534{
535 s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
536 n30_hwinit();
537 s3c24xx_init_clocks(0);
538 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
539}
540
541/* GPB3 is the line that controls the pull-up for the USB D+ line */
542
543static void __init n30_init(void)
544{
545 WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power"));
546
547 s3c24xx_fb_set_platdata(&n30_fb_info);
548 s3c24xx_udc_set_platdata(&n30_udc_cfg);
549 s3c24xx_mci_set_platdata(&n30_mci_cfg);
550 s3c_i2c0_set_platdata(&n30_i2ccfg);
551
552 /* Turn off suspend on both USB ports, and switch the
553 * selectable USB port to USB device mode. */
554
555 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
556 S3C2410_MISCCR_USBSUSPND0 |
557 S3C2410_MISCCR_USBSUSPND1, 0x0);
558
559 if (machine_is_n30()) {
560 /* Turn off suspend on both USB ports, and switch the
561 * selectable USB port to USB device mode. */
562 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
563 S3C2410_MISCCR_USBSUSPND0 |
564 S3C2410_MISCCR_USBSUSPND1, 0x0);
565
566 platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
567 }
568
569 if (machine_is_n35()) {
570 /* Turn off suspend and switch the selectable USB port
571 * to USB device mode. Turn on suspend for the host
572 * port since it is not connected on the N35.
573 *
574 * Actually, the host port is available at some pads
575 * on the back of the device, so it would actually be
576 * possible to add a USB device inside the N35 if you
577 * are willing to do some hardware modifications. */
578 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
579 S3C2410_MISCCR_USBSUSPND0 |
580 S3C2410_MISCCR_USBSUSPND1,
581 S3C2410_MISCCR_USBSUSPND0);
582
583 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
584 }
585}
586
587MACHINE_START(N30, "Acer-N30")
588 /* Maintainer: Christer Weinigel <christer@weinigel.se>,
589 Ben Dooks <ben-linux@fluff.org>
590 */
591 .atag_offset = 0x100,
592 .timer = &s3c24xx_timer,
593 .init_machine = n30_init,
594 .init_irq = s3c24xx_init_irq,
595 .map_io = n30_map_io,
596 .restart = s3c2410_restart,
597MACHINE_END
598
599MACHINE_START(N35, "Acer-N35")
600 /* Maintainer: Christer Weinigel <christer@weinigel.se>
601 */
602 .atag_offset = 0x100,
603 .timer = &s3c24xx_timer,
604 .init_machine = n30_init,
605 .init_irq = s3c24xx_init_irq,
606 .map_io = n30_map_io,
607 .restart = s3c2410_restart,
608MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
deleted file mode 100644
index 5f1e0eeb38a9..000000000000
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ /dev/null
@@ -1,127 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-otom.c
2 *
3 * Copyright (c) 2004 Nex Vision
4 * Guillaume GOURAT <guillaume.gourat@nexvision.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21
22#include <asm/mach/arch.h>
23#include <asm/mach/map.h>
24#include <asm/mach/irq.h>
25
26#include <mach/otom-map.h>
27
28#include <mach/hardware.h>
29#include <asm/irq.h>
30#include <asm/mach-types.h>
31
32#include <plat/regs-serial.h>
33#include <mach/regs-gpio.h>
34
35#include <plat/s3c2410.h>
36#include <plat/clock.h>
37#include <plat/devs.h>
38#include <plat/iic.h>
39#include <plat/cpu.h>
40
41#include "common.h"
42
43static struct map_desc otom11_iodesc[] __initdata = {
44 /* Device area */
45 { (u32)OTOM_VA_CS8900A_BASE, OTOM_PA_CS8900A_BASE, SZ_16M, MT_DEVICE },
46};
47
48#define UCON S3C2410_UCON_DEFAULT
49#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
50#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
51
52static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
53 [0] = {
54 .hwport = 0,
55 .flags = 0,
56 .ucon = UCON,
57 .ulcon = ULCON,
58 .ufcon = UFCON,
59 },
60 [1] = {
61 .hwport = 1,
62 .flags = 0,
63 .ucon = UCON,
64 .ulcon = ULCON,
65 .ufcon = UFCON,
66 },
67 /* port 2 is not actually used */
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 }
75};
76
77/* NOR Flash on NexVision OTOM board */
78
79static struct resource otom_nor_resource[] = {
80 [0] = {
81 .start = S3C2410_CS0,
82 .end = S3C2410_CS0 + (4*1024*1024) - 1,
83 .flags = IORESOURCE_MEM,
84 }
85};
86
87static struct platform_device otom_device_nor = {
88 .name = "mtd-flash",
89 .id = -1,
90 .num_resources = ARRAY_SIZE(otom_nor_resource),
91 .resource = otom_nor_resource,
92};
93
94/* Standard OTOM devices */
95
96static struct platform_device *otom11_devices[] __initdata = {
97 &s3c_device_ohci,
98 &s3c_device_lcd,
99 &s3c_device_wdt,
100 &s3c_device_i2c0,
101 &s3c_device_iis,
102 &s3c_device_rtc,
103 &otom_device_nor,
104};
105
106static void __init otom11_map_io(void)
107{
108 s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
109 s3c24xx_init_clocks(0);
110 s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
111}
112
113static void __init otom11_init(void)
114{
115 s3c_i2c0_set_platdata(NULL);
116 platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
117}
118
119MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
120 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
121 .atag_offset = 0x100,
122 .map_io = otom11_map_io,
123 .init_machine = otom11_init,
124 .init_irq = s3c24xx_init_irq,
125 .timer = &s3c24xx_timer,
126 .restart = s3c2410_restart,
127MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
deleted file mode 100644
index 91c16d9d2459..000000000000
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ /dev/null
@@ -1,356 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
2 *
3 * Copyright (C) 2006 by OpenMoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/list.h>
28#include <linux/timer.h>
29#include <linux/init.h>
30#include <linux/gpio.h>
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/serial_core.h>
34#include <linux/spi/spi.h>
35#include <linux/spi/spi_gpio.h>
36#include <linux/io.h>
37#include <linux/mtd/mtd.h>
38#include <linux/mtd/nand.h>
39#include <linux/mtd/nand_ecc.h>
40#include <linux/mtd/partitions.h>
41
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45
46#include <mach/hardware.h>
47#include <asm/irq.h>
48#include <asm/mach-types.h>
49
50#include <mach/regs-gpio.h>
51#include <mach/leds-gpio.h>
52#include <mach/regs-lcd.h>
53#include <plat/regs-serial.h>
54#include <mach/fb.h>
55#include <plat/nand.h>
56#include <plat/udc.h>
57#include <plat/iic.h>
58
59#include <plat/common-smdk.h>
60#include <plat/gpio-cfg.h>
61#include <plat/devs.h>
62#include <plat/cpu.h>
63#include <plat/pm.h>
64
65#include "common.h"
66
67static struct map_desc qt2410_iodesc[] __initdata = {
68 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
69};
70
71#define UCON S3C2410_UCON_DEFAULT
72#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
73#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
74
75static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
76 [0] = {
77 .hwport = 0,
78 .flags = 0,
79 .ucon = UCON,
80 .ulcon = ULCON,
81 .ufcon = UFCON,
82 },
83 [1] = {
84 .hwport = 1,
85 .flags = 0,
86 .ucon = UCON,
87 .ulcon = ULCON,
88 .ufcon = UFCON,
89 },
90 [2] = {
91 .hwport = 2,
92 .flags = 0,
93 .ucon = UCON,
94 .ulcon = ULCON,
95 .ufcon = UFCON,
96 }
97};
98
99/* LCD driver info */
100
101static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
102 {
103 /* Configuration for 640x480 SHARP LQ080V3DG01 */
104 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
105 S3C2410_LCDCON5_INVVLINE |
106 S3C2410_LCDCON5_INVVFRAME |
107 S3C2410_LCDCON5_PWREN |
108 S3C2410_LCDCON5_HWSWP,
109
110 .type = S3C2410_LCDCON1_TFT,
111 .width = 640,
112 .height = 480,
113
114 .pixclock = 40000, /* HCLK/4 */
115 .xres = 640,
116 .yres = 480,
117 .bpp = 16,
118 .left_margin = 44,
119 .right_margin = 116,
120 .hsync_len = 96,
121 .upper_margin = 19,
122 .lower_margin = 11,
123 .vsync_len = 15,
124 },
125 {
126 /* Configuration for 480x640 toppoly TD028TTEC1 */
127 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
128 S3C2410_LCDCON5_INVVLINE |
129 S3C2410_LCDCON5_INVVFRAME |
130 S3C2410_LCDCON5_PWREN |
131 S3C2410_LCDCON5_HWSWP,
132
133 .type = S3C2410_LCDCON1_TFT,
134 .width = 480,
135 .height = 640,
136 .pixclock = 40000, /* HCLK/4 */
137 .xres = 480,
138 .yres = 640,
139 .bpp = 16,
140 .left_margin = 8,
141 .right_margin = 24,
142 .hsync_len = 8,
143 .upper_margin = 2,
144 .lower_margin = 4,
145 .vsync_len = 2,
146 },
147 {
148 /* Config for 240x320 LCD */
149 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
150 S3C2410_LCDCON5_INVVLINE |
151 S3C2410_LCDCON5_INVVFRAME |
152 S3C2410_LCDCON5_PWREN |
153 S3C2410_LCDCON5_HWSWP,
154
155 .type = S3C2410_LCDCON1_TFT,
156 .width = 240,
157 .height = 320,
158 .pixclock = 100000, /* HCLK/10 */
159 .xres = 240,
160 .yres = 320,
161 .bpp = 16,
162 .left_margin = 13,
163 .right_margin = 8,
164 .hsync_len = 4,
165 .upper_margin = 2,
166 .lower_margin = 7,
167 .vsync_len = 4,
168 },
169};
170
171
172static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
173 .displays = qt2410_lcd_cfg,
174 .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
175 .default_display = 0,
176
177 .lpcsel = ((0xCE6) & ~7) | 1<<4,
178};
179
180/* CS8900 */
181
182static struct resource qt2410_cs89x0_resources[] = {
183 [0] = {
184 .start = 0x19000000,
185 .end = 0x19000000 + 16,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = IRQ_EINT9,
190 .end = IRQ_EINT9,
191 .flags = IORESOURCE_IRQ,
192 },
193};
194
195static struct platform_device qt2410_cs89x0 = {
196 .name = "cirrus-cs89x0",
197 .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
198 .resource = qt2410_cs89x0_resources,
199};
200
201/* LED */
202
203static struct s3c24xx_led_platdata qt2410_pdata_led = {
204 .gpio = S3C2410_GPB(0),
205 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
206 .name = "led",
207 .def_trigger = "timer",
208};
209
210static struct platform_device qt2410_led = {
211 .name = "s3c24xx_led",
212 .id = 0,
213 .dev = {
214 .platform_data = &qt2410_pdata_led,
215 },
216};
217
218/* SPI */
219
220static struct spi_gpio_platform_data spi_gpio_cfg = {
221 .sck = S3C2410_GPG(7),
222 .mosi = S3C2410_GPG(6),
223 .miso = S3C2410_GPG(5),
224};
225
226static struct platform_device qt2410_spi = {
227 .name = "spi-gpio",
228 .id = 1,
229 .dev.platform_data = &spi_gpio_cfg,
230};
231
232/* Board devices */
233
234static struct platform_device *qt2410_devices[] __initdata = {
235 &s3c_device_ohci,
236 &s3c_device_lcd,
237 &s3c_device_wdt,
238 &s3c_device_i2c0,
239 &s3c_device_iis,
240 &s3c_device_sdi,
241 &s3c_device_usbgadget,
242 &qt2410_spi,
243 &qt2410_cs89x0,
244 &qt2410_led,
245};
246
247static struct mtd_partition __initdata qt2410_nand_part[] = {
248 [0] = {
249 .name = "U-Boot",
250 .size = 0x30000,
251 .offset = 0,
252 },
253 [1] = {
254 .name = "U-Boot environment",
255 .offset = 0x30000,
256 .size = 0x4000,
257 },
258 [2] = {
259 .name = "kernel",
260 .offset = 0x34000,
261 .size = SZ_2M,
262 },
263 [3] = {
264 .name = "initrd",
265 .offset = 0x234000,
266 .size = SZ_4M,
267 },
268 [4] = {
269 .name = "jffs2",
270 .offset = 0x634000,
271 .size = 0x39cc000,
272 },
273};
274
275static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
276 [0] = {
277 .name = "NAND",
278 .nr_chips = 1,
279 .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
280 .partitions = qt2410_nand_part,
281 },
282};
283
284/* choose a set of timings which should suit most 512Mbit
285 * chips and beyond.
286 */
287
288static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
289 .tacls = 20,
290 .twrph0 = 60,
291 .twrph1 = 20,
292 .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
293 .sets = qt2410_nand_sets,
294};
295
296/* UDC */
297
298static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
299};
300
301static char tft_type = 's';
302
303static int __init qt2410_tft_setup(char *str)
304{
305 tft_type = str[0];
306 return 1;
307}
308
309__setup("tft=", qt2410_tft_setup);
310
311static void __init qt2410_map_io(void)
312{
313 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
314 s3c24xx_init_clocks(12*1000*1000);
315 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
316}
317
318static void __init qt2410_machine_init(void)
319{
320 s3c_nand_set_platdata(&qt2410_nand_info);
321
322 switch (tft_type) {
323 case 'p': /* production */
324 qt2410_fb_info.default_display = 1;
325 break;
326 case 'b': /* big */
327 qt2410_fb_info.default_display = 0;
328 break;
329 case 's': /* small */
330 default:
331 qt2410_fb_info.default_display = 2;
332 break;
333 }
334 s3c24xx_fb_set_platdata(&qt2410_fb_info);
335
336 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
337 s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
338
339 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
340 s3c_i2c0_set_platdata(NULL);
341
342 WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
343 gpio_direction_output(S3C2410_GPB(5), 1);
344
345 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
346 s3c_pm_init();
347}
348
349MACHINE_START(QT2410, "QT2410")
350 .atag_offset = 0x100,
351 .map_io = qt2410_map_io,
352 .init_irq = s3c24xx_init_irq,
353 .init_machine = qt2410_machine_init,
354 .timer = &s3c24xx_timer,
355 .restart = s3c2410_restart,
356MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
deleted file mode 100644
index bdc27e772876..000000000000
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-smdk2410.c
2 *
3 * linux/arch/arm/mach-s3c2410/mach-smdk2410.c
4 *
5 * Copyright (C) 2004 by FS Forth-Systeme GmbH
6 * All rights reserved.
7 *
8 * @Author: Jonas Dietsche
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * @History:
26 * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
27 * Ben Dooks <ben@simtec.co.uk>
28 *
29 ***********************************************************************/
30
31#include <linux/kernel.h>
32#include <linux/types.h>
33#include <linux/interrupt.h>
34#include <linux/list.h>
35#include <linux/timer.h>
36#include <linux/init.h>
37#include <linux/serial_core.h>
38#include <linux/platform_device.h>
39#include <linux/io.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44
45#include <mach/hardware.h>
46#include <asm/irq.h>
47#include <asm/mach-types.h>
48
49#include <plat/regs-serial.h>
50#include <plat/iic.h>
51
52#include <plat/devs.h>
53#include <plat/cpu.h>
54
55#include <plat/common-smdk.h>
56
57#include "common.h"
58
59static struct map_desc smdk2410_iodesc[] __initdata = {
60 /* nothing here yet */
61};
62
63#define UCON S3C2410_UCON_DEFAULT
64#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
65#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
66
67static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = {
68 [0] = {
69 .hwport = 0,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75 [1] = {
76 .hwport = 1,
77 .flags = 0,
78 .ucon = UCON,
79 .ulcon = ULCON,
80 .ufcon = UFCON,
81 },
82 [2] = {
83 .hwport = 2,
84 .flags = 0,
85 .ucon = UCON,
86 .ulcon = ULCON,
87 .ufcon = UFCON,
88 }
89};
90
91static struct platform_device *smdk2410_devices[] __initdata = {
92 &s3c_device_ohci,
93 &s3c_device_lcd,
94 &s3c_device_wdt,
95 &s3c_device_i2c0,
96 &s3c_device_iis,
97};
98
99static void __init smdk2410_map_io(void)
100{
101 s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
102 s3c24xx_init_clocks(0);
103 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
104}
105
106static void __init smdk2410_init(void)
107{
108 s3c_i2c0_set_platdata(NULL);
109 platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
110 smdk_machine_init();
111}
112
113MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
114 * to SMDK2410 */
115 /* Maintainer: Jonas Dietsche */
116 .atag_offset = 0x100,
117 .map_io = smdk2410_map_io,
118 .init_irq = s3c24xx_init_irq,
119 .init_machine = smdk2410_init,
120 .timer = &s3c24xx_timer,
121 .restart = s3c2410_restart,
122MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
deleted file mode 100644
index 1114666f0efb..000000000000
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-tct_hammer.c
2 *
3 * Copyright (c) 2007 TinCanTools
4 * David Anders <danders@amltd.com>
5
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 *
21 * @History:
22 * derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
23 * Ben Dooks <ben@simtec.co.uk>
24 *
25 ***********************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/types.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/timer.h>
32#include <linux/init.h>
33#include <linux/device.h>
34#include <linux/platform_device.h>
35#include <linux/serial_core.h>
36#include <linux/io.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41#include <asm/mach/flash.h>
42
43#include <mach/hardware.h>
44#include <asm/irq.h>
45#include <asm/mach-types.h>
46
47#include <plat/regs-serial.h>
48#include <plat/iic.h>
49#include <plat/devs.h>
50#include <plat/cpu.h>
51
52#include <linux/mtd/mtd.h>
53#include <linux/mtd/partitions.h>
54#include <linux/mtd/map.h>
55#include <linux/mtd/physmap.h>
56
57#include "common.h"
58
59static struct resource tct_hammer_nor_resource = {
60 .start = 0x00000000,
61 .end = 0x01000000 - 1,
62 .flags = IORESOURCE_MEM,
63};
64
65static struct mtd_partition tct_hammer_mtd_partitions[] = {
66 {
67 .name = "System",
68 .size = 0x240000,
69 .offset = 0,
70 .mask_flags = MTD_WRITEABLE, /* force read-only */
71 }, {
72 .name = "JFFS2",
73 .size = MTDPART_SIZ_FULL,
74 .offset = MTDPART_OFS_APPEND,
75 }
76};
77
78static struct physmap_flash_data tct_hammer_flash_data = {
79 .width = 2,
80 .parts = tct_hammer_mtd_partitions,
81 .nr_parts = ARRAY_SIZE(tct_hammer_mtd_partitions),
82};
83
84static struct platform_device tct_hammer_device_nor = {
85 .name = "physmap-flash",
86 .id = 0,
87 .dev = {
88 .platform_data = &tct_hammer_flash_data,
89 },
90 .num_resources = 1,
91 .resource = &tct_hammer_nor_resource,
92};
93
94static struct map_desc tct_hammer_iodesc[] __initdata = {
95};
96
97#define UCON S3C2410_UCON_DEFAULT
98#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
99#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
100
101static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
102 [0] = {
103 .hwport = 0,
104 .flags = 0,
105 .ucon = UCON,
106 .ulcon = ULCON,
107 .ufcon = UFCON,
108 },
109 [1] = {
110 .hwport = 1,
111 .flags = 0,
112 .ucon = UCON,
113 .ulcon = ULCON,
114 .ufcon = UFCON,
115 },
116 [2] = {
117 .hwport = 2,
118 .flags = 0,
119 .ucon = UCON,
120 .ulcon = ULCON,
121 .ufcon = UFCON,
122 }
123};
124
125
126static struct platform_device *tct_hammer_devices[] __initdata = {
127 &s3c_device_adc,
128 &s3c_device_wdt,
129 &s3c_device_i2c0,
130 &s3c_device_ohci,
131 &s3c_device_rtc,
132 &s3c_device_usbgadget,
133 &s3c_device_sdi,
134 &tct_hammer_device_nor,
135};
136
137static void __init tct_hammer_map_io(void)
138{
139 s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
140 s3c24xx_init_clocks(0);
141 s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
142}
143
144static void __init tct_hammer_init(void)
145{
146 s3c_i2c0_set_platdata(NULL);
147 platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
148}
149
150MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
151 .atag_offset = 0x100,
152 .map_io = tct_hammer_map_io,
153 .init_irq = s3c24xx_init_irq,
154 .init_machine = tct_hammer_init,
155 .timer = &s3c24xx_timer,
156 .restart = s3c2410_restart,
157MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
deleted file mode 100644
index dbe668a803ef..000000000000
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ /dev/null
@@ -1,386 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
2 *
3 * Copyright (c) 2003-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
7 * Simtec Electronics, http://www.simtec.co.uk/
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
22#include <linux/dm9000.h>
23#include <linux/i2c.h>
24
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/serial_8250.h>
28#include <linux/serial_reg.h>
29#include <linux/io.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <mach/bast-map.h>
36#include <mach/vr1000-map.h>
37#include <mach/vr1000-irq.h>
38#include <mach/vr1000-cpld.h>
39
40#include <mach/hardware.h>
41#include <asm/irq.h>
42#include <asm/mach-types.h>
43
44#include <plat/regs-serial.h>
45#include <mach/regs-gpio.h>
46#include <mach/leds-gpio.h>
47
48#include <plat/clock.h>
49#include <plat/devs.h>
50#include <plat/cpu.h>
51#include <plat/iic.h>
52#include <plat/audio-simtec.h>
53
54#include "usb-simtec.h"
55#include "nor-simtec.h"
56#include "common.h"
57
58/* macros for virtual address mods for the io space entries */
59#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
60#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
61#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
62#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
63
64/* macros to modify the physical addresses for io space */
65
66#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
67#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
68#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
69#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
70
71static struct map_desc vr1000_iodesc[] __initdata = {
72 /* ISA IO areas */
73 {
74 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
75 .pfn = PA_CS2(BAST_PA_ISAIO),
76 .length = SZ_16M,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (u32)S3C24XX_VA_ISA_WORD,
80 .pfn = PA_CS3(BAST_PA_ISAIO),
81 .length = SZ_16M,
82 .type = MT_DEVICE,
83 },
84
85 /* CPLD control registers, and external interrupt controls */
86 {
87 .virtual = (u32)VR1000_VA_CTRL1,
88 .pfn = __phys_to_pfn(VR1000_PA_CTRL1),
89 .length = SZ_1M,
90 .type = MT_DEVICE,
91 }, {
92 .virtual = (u32)VR1000_VA_CTRL2,
93 .pfn = __phys_to_pfn(VR1000_PA_CTRL2),
94 .length = SZ_1M,
95 .type = MT_DEVICE,
96 }, {
97 .virtual = (u32)VR1000_VA_CTRL3,
98 .pfn = __phys_to_pfn(VR1000_PA_CTRL3),
99 .length = SZ_1M,
100 .type = MT_DEVICE,
101 }, {
102 .virtual = (u32)VR1000_VA_CTRL4,
103 .pfn = __phys_to_pfn(VR1000_PA_CTRL4),
104 .length = SZ_1M,
105 .type = MT_DEVICE,
106 },
107};
108
109#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
110#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
111#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
112
113static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
114 [0] = {
115 .hwport = 0,
116 .flags = 0,
117 .ucon = UCON,
118 .ulcon = ULCON,
119 .ufcon = UFCON,
120 },
121 [1] = {
122 .hwport = 1,
123 .flags = 0,
124 .ucon = UCON,
125 .ulcon = ULCON,
126 .ufcon = UFCON,
127 },
128 /* port 2 is not actually used */
129 [2] = {
130 .hwport = 2,
131 .flags = 0,
132 .ucon = UCON,
133 .ulcon = ULCON,
134 .ufcon = UFCON,
135 }
136};
137
138/* definitions for the vr1000 extra 16550 serial ports */
139
140#define VR1000_BAUDBASE (3692307)
141
142#define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5))
143
144static struct plat_serial8250_port serial_platform_data[] = {
145 [0] = {
146 .mapbase = VR1000_SERIAL_MAPBASE(0),
147 .irq = IRQ_VR1000_SERIAL + 0,
148 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
149 .iotype = UPIO_MEM,
150 .regshift = 0,
151 .uartclk = VR1000_BAUDBASE,
152 },
153 [1] = {
154 .mapbase = VR1000_SERIAL_MAPBASE(1),
155 .irq = IRQ_VR1000_SERIAL + 1,
156 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
157 .iotype = UPIO_MEM,
158 .regshift = 0,
159 .uartclk = VR1000_BAUDBASE,
160 },
161 [2] = {
162 .mapbase = VR1000_SERIAL_MAPBASE(2),
163 .irq = IRQ_VR1000_SERIAL + 2,
164 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
165 .iotype = UPIO_MEM,
166 .regshift = 0,
167 .uartclk = VR1000_BAUDBASE,
168 },
169 [3] = {
170 .mapbase = VR1000_SERIAL_MAPBASE(3),
171 .irq = IRQ_VR1000_SERIAL + 3,
172 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
173 .iotype = UPIO_MEM,
174 .regshift = 0,
175 .uartclk = VR1000_BAUDBASE,
176 },
177 { },
178};
179
180static struct platform_device serial_device = {
181 .name = "serial8250",
182 .id = PLAT8250_DEV_PLATFORM,
183 .dev = {
184 .platform_data = serial_platform_data,
185 },
186};
187
188/* DM9000 ethernet devices */
189
190static struct resource vr1000_dm9k0_resource[] = {
191 [0] = {
192 .start = S3C2410_CS5 + VR1000_PA_DM9000,
193 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 3,
194 .flags = IORESOURCE_MEM
195 },
196 [1] = {
197 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40,
198 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f,
199 .flags = IORESOURCE_MEM
200 },
201 [2] = {
202 .start = IRQ_VR1000_DM9000A,
203 .end = IRQ_VR1000_DM9000A,
204 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
205 }
206
207};
208
209static struct resource vr1000_dm9k1_resource[] = {
210 [0] = {
211 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80,
212 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83,
213 .flags = IORESOURCE_MEM
214 },
215 [1] = {
216 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0,
217 .end = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF,
218 .flags = IORESOURCE_MEM
219 },
220 [2] = {
221 .start = IRQ_VR1000_DM9000N,
222 .end = IRQ_VR1000_DM9000N,
223 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
224 }
225};
226
227/* for the moment we limit ourselves to 16bit IO until some
228 * better IO routines can be written and tested
229*/
230
231static struct dm9000_plat_data vr1000_dm9k_platdata = {
232 .flags = DM9000_PLATF_16BITONLY,
233};
234
235static struct platform_device vr1000_dm9k0 = {
236 .name = "dm9000",
237 .id = 0,
238 .num_resources = ARRAY_SIZE(vr1000_dm9k0_resource),
239 .resource = vr1000_dm9k0_resource,
240 .dev = {
241 .platform_data = &vr1000_dm9k_platdata,
242 }
243};
244
245static struct platform_device vr1000_dm9k1 = {
246 .name = "dm9000",
247 .id = 1,
248 .num_resources = ARRAY_SIZE(vr1000_dm9k1_resource),
249 .resource = vr1000_dm9k1_resource,
250 .dev = {
251 .platform_data = &vr1000_dm9k_platdata,
252 }
253};
254
255/* LEDS */
256
257static struct s3c24xx_led_platdata vr1000_led1_pdata = {
258 .name = "led1",
259 .gpio = S3C2410_GPB(0),
260 .def_trigger = "",
261};
262
263static struct s3c24xx_led_platdata vr1000_led2_pdata = {
264 .name = "led2",
265 .gpio = S3C2410_GPB(1),
266 .def_trigger = "",
267};
268
269static struct s3c24xx_led_platdata vr1000_led3_pdata = {
270 .name = "led3",
271 .gpio = S3C2410_GPB(2),
272 .def_trigger = "",
273};
274
275static struct platform_device vr1000_led1 = {
276 .name = "s3c24xx_led",
277 .id = 1,
278 .dev = {
279 .platform_data = &vr1000_led1_pdata,
280 },
281};
282
283static struct platform_device vr1000_led2 = {
284 .name = "s3c24xx_led",
285 .id = 2,
286 .dev = {
287 .platform_data = &vr1000_led2_pdata,
288 },
289};
290
291static struct platform_device vr1000_led3 = {
292 .name = "s3c24xx_led",
293 .id = 3,
294 .dev = {
295 .platform_data = &vr1000_led3_pdata,
296 },
297};
298
299/* I2C devices. */
300
301static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
302 {
303 I2C_BOARD_INFO("tlv320aic23", 0x1a),
304 }, {
305 I2C_BOARD_INFO("tmp101", 0x48),
306 }, {
307 I2C_BOARD_INFO("m41st87", 0x68),
308 },
309};
310
311/* devices for this board */
312
313static struct platform_device *vr1000_devices[] __initdata = {
314 &s3c_device_ohci,
315 &s3c_device_lcd,
316 &s3c_device_wdt,
317 &s3c_device_i2c0,
318 &s3c_device_adc,
319 &serial_device,
320 &vr1000_dm9k0,
321 &vr1000_dm9k1,
322 &vr1000_led1,
323 &vr1000_led2,
324 &vr1000_led3,
325};
326
327static struct clk *vr1000_clocks[] __initdata = {
328 &s3c24xx_dclk0,
329 &s3c24xx_dclk1,
330 &s3c24xx_clkout0,
331 &s3c24xx_clkout1,
332 &s3c24xx_uclk,
333};
334
335static void vr1000_power_off(void)
336{
337 gpio_direction_output(S3C2410_GPB(9), 1);
338}
339
340static void __init vr1000_map_io(void)
341{
342 /* initialise clock sources */
343
344 s3c24xx_dclk0.parent = &clk_upll;
345 s3c24xx_dclk0.rate = 12*1000*1000;
346
347 s3c24xx_dclk1.parent = NULL;
348 s3c24xx_dclk1.rate = 3692307;
349
350 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
351 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
352
353 s3c24xx_uclk.parent = &s3c24xx_clkout1;
354
355 s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
356
357 pm_power_off = vr1000_power_off;
358
359 s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
360 s3c24xx_init_clocks(0);
361 s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
362}
363
364static void __init vr1000_init(void)
365{
366 s3c_i2c0_set_platdata(NULL);
367 platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
368
369 i2c_register_board_info(0, vr1000_i2c_devs,
370 ARRAY_SIZE(vr1000_i2c_devs));
371
372 nor_simtec_init();
373 simtec_audio_add(NULL, true, NULL);
374
375 WARN_ON(gpio_request(S3C2410_GPB(9), "power off"));
376}
377
378MACHINE_START(VR1000, "Thorcom-VR1000")
379 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
380 .atag_offset = 0x100,
381 .map_io = vr1000_map_io,
382 .init_machine = vr1000_init,
383 .init_irq = s3c24xx_init_irq,
384 .timer = &s3c24xx_timer,
385 .restart = s3c2410_restart,
386MACHINE_END
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
deleted file mode 100644
index ad9f750f1e55..000000000000
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/nor-simtec.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Simtec NOR mapping
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/map.h>
22#include <linux/mtd/physmap.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/map.h>
30#include <mach/bast-map.h>
31#include <mach/bast-cpld.h>
32
33#include "nor-simtec.h"
34
35static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
36{
37 unsigned int val;
38 unsigned long flags;
39
40 local_irq_save(flags);
41 val = __raw_readb(BAST_VA_CTRL3);
42
43 printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
44
45 if (vpp)
46 val |= BAST_CPLD_CTRL3_ROMWEN;
47 else
48 val &= ~BAST_CPLD_CTRL3_ROMWEN;
49
50 __raw_writeb(val, BAST_VA_CTRL3);
51 local_irq_restore(flags);
52}
53
54static struct physmap_flash_data simtec_nor_pdata = {
55 .width = 2,
56 .set_vpp = simtec_nor_vpp,
57 .nr_parts = 0,
58};
59
60static struct resource simtec_nor_resource[] = {
61 [0] = {
62 .start = S3C2410_CS1 + 0x4000000,
63 .end = S3C2410_CS1 + 0x4000000 + SZ_8M - 1,
64 .flags = IORESOURCE_MEM,
65 }
66};
67
68static struct platform_device simtec_device_nor = {
69 .name = "physmap-flash",
70 .id = -1,
71 .num_resources = ARRAY_SIZE(simtec_nor_resource),
72 .resource = simtec_nor_resource,
73 .dev = {
74 .platform_data = &simtec_nor_pdata,
75 },
76};
77
78void __init nor_simtec_init(void)
79{
80 int ret;
81
82 ret = platform_device_register(&simtec_device_nor);
83 if (ret < 0)
84 printk(KERN_ERR "failed to register physmap-flash device\n");
85 else
86 simtec_nor_vpp(NULL, 1);
87}
diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c2410/nor-simtec.h
deleted file mode 100644
index f619c1e0d0c8..000000000000
--- a/arch/arm/mach-s3c2410/nor-simtec.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/nor-simtec.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Simtec NOR mapping
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14extern void nor_simtec_init(void);
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c2410/pm-h1940.S
deleted file mode 100644
index c93bf2db9f4d..000000000000
--- a/arch/arm/mach-s3c2410/pm-h1940.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/pm-h1940.S
2 *
3 * Copyright (c) 2006 Ben Dooks <ben-linux@fluff.org>
4 *
5 * H1940 Suspend to RAM
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/linkage.h>
22#include <asm/assembler.h>
23#include <mach/hardware.h>
24#include <mach/map.h>
25
26#include <mach/regs-gpio.h>
27
28 .text
29 .global h1940_pm_return
30
31h1940_pm_return:
32 mov r0, #S3C2410_PA_GPIO
33 ldr pc, [ r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO ]
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
deleted file mode 100644
index fda5385deff6..000000000000
--- a/arch/arm/mach-s3c2410/pm.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/init.h>
24#include <linux/suspend.h>
25#include <linux/errno.h>
26#include <linux/time.h>
27#include <linux/device.h>
28#include <linux/syscore_ops.h>
29#include <linux/gpio.h>
30#include <linux/io.h>
31
32#include <mach/hardware.h>
33
34#include <asm/mach-types.h>
35
36#include <mach/regs-gpio.h>
37#include <mach/h1940.h>
38
39#include <plat/cpu.h>
40#include <plat/pm.h>
41
42static void s3c2410_pm_prepare(void)
43{
44 /* ensure at least GSTATUS3 has the resume address */
45
46 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
47
48 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
49 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
50
51 if (machine_is_h1940()) {
52 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
53 unsigned long ptr;
54 unsigned long calc = 0;
55
56 /* generate check for the bootloader to check on resume */
57
58 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
59 calc += __raw_readl(base+ptr);
60
61 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
62 }
63
64 /* RX3715 and RX1950 use similar to H1940 code and the
65 * same offsets for resume and checksum pointers */
66
67 if (machine_is_rx3715() || machine_is_rx1950()) {
68 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
69 unsigned long ptr;
70 unsigned long calc = 0;
71
72 /* generate check for the bootloader to check on resume */
73
74 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
75 calc += __raw_readl(base+ptr);
76
77 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
78 }
79
80 if ( machine_is_aml_m5900() )
81 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
82
83 if (machine_is_rx1950()) {
84 /* According to S3C2442 user's manual, page 7-17,
85 * when the system is operating in NAND boot mode,
86 * the hardware pin configuration - EINT[23:21] –
87 * must be set as input for starting up after
88 * wakeup from sleep mode
89 */
90 s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
91 s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
92 s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
93 }
94}
95
96static void s3c2410_pm_resume(void)
97{
98 unsigned long tmp;
99
100 /* unset the return-from-sleep flag, to ensure reset */
101
102 tmp = __raw_readl(S3C2410_GSTATUS2);
103 tmp &= S3C2410_GSTATUS2_OFFRESET;
104 __raw_writel(tmp, S3C2410_GSTATUS2);
105
106 if ( machine_is_aml_m5900() )
107 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
108}
109
110struct syscore_ops s3c2410_pm_syscore_ops = {
111 .resume = s3c2410_pm_resume,
112};
113
114static int s3c2410_pm_add(struct device *dev)
115{
116 pm_cpu_prep = s3c2410_pm_prepare;
117 pm_cpu_sleep = s3c2410_cpu_suspend;
118
119 return 0;
120}
121
122#if defined(CONFIG_CPU_S3C2410)
123static struct subsys_interface s3c2410_pm_interface = {
124 .name = "s3c2410_pm",
125 .subsys = &s3c2410_subsys,
126 .add_dev = s3c2410_pm_add,
127};
128
129/* register ourselves */
130
131static int __init s3c2410_pm_drvinit(void)
132{
133 return subsys_interface_register(&s3c2410_pm_interface);
134}
135
136arch_initcall(s3c2410_pm_drvinit);
137
138static struct subsys_interface s3c2410a_pm_interface = {
139 .name = "s3c2410a_pm",
140 .subsys = &s3c2410a_subsys,
141 .add_dev = s3c2410_pm_add,
142};
143
144static int __init s3c2410a_pm_drvinit(void)
145{
146 return subsys_interface_register(&s3c2410a_pm_interface);
147}
148
149arch_initcall(s3c2410a_pm_drvinit);
150#endif
151
152#if defined(CONFIG_CPU_S3C2440)
153static struct subsys_interface s3c2440_pm_interface = {
154 .name = "s3c2440_pm",
155 .subsys = &s3c2440_subsys,
156 .add_dev = s3c2410_pm_add,
157};
158
159static int __init s3c2440_pm_drvinit(void)
160{
161 return subsys_interface_register(&s3c2440_pm_interface);
162}
163
164arch_initcall(s3c2440_pm_drvinit);
165#endif
166
167#if defined(CONFIG_CPU_S3C2442)
168static struct subsys_interface s3c2442_pm_interface = {
169 .name = "s3c2442_pm",
170 .subsys = &s3c2442_subsys,
171 .add_dev = s3c2410_pm_add,
172};
173
174static int __init s3c2442_pm_drvinit(void)
175{
176 return subsys_interface_register(&s3c2442_pm_interface);
177}
178
179arch_initcall(s3c2442_pm_drvinit);
180#endif
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
deleted file mode 100644
index 061b6bb1a557..000000000000
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/s3c2410.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/clk.h>
21#include <linux/device.h>
22#include <linux/syscore_ops.h>
23#include <linux/serial_core.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/hardware.h>
32#include <asm/irq.h>
33
34#include <plat/cpu-freq.h>
35
36#include <mach/regs-clock.h>
37#include <plat/regs-serial.h>
38
39#include <plat/s3c2410.h>
40#include <plat/cpu.h>
41#include <plat/devs.h>
42#include <plat/clock.h>
43#include <plat/pll.h>
44#include <plat/pm.h>
45#include <plat/watchdog-reset.h>
46
47#include <plat/gpio-core.h>
48#include <plat/gpio-cfg.h>
49#include <plat/gpio-cfg-helpers.h>
50
51/* Initial IO mappings */
52
53static struct map_desc s3c2410_iodesc[] __initdata = {
54 IODESC_ENT(CLKPWR),
55 IODESC_ENT(TIMER),
56 IODESC_ENT(WATCHDOG),
57};
58
59/* our uart devices */
60
61/* uart registration process */
62
63void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
64{
65 s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no);
66}
67
68/* s3c2410_map_io
69 *
70 * register the standard cpu IO areas, and any passed in from the
71 * machine specific initialisation.
72*/
73
74void __init s3c2410_map_io(void)
75{
76 s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
77 s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
78
79 iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
80}
81
82void __init_or_cpufreq s3c2410_setup_clocks(void)
83{
84 struct clk *xtal_clk;
85 unsigned long tmp;
86 unsigned long xtal;
87 unsigned long fclk;
88 unsigned long hclk;
89 unsigned long pclk;
90
91 xtal_clk = clk_get(NULL, "xtal");
92 xtal = clk_get_rate(xtal_clk);
93 clk_put(xtal_clk);
94
95 /* now we've got our machine bits initialised, work out what
96 * clocks we've got */
97
98 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
99
100 tmp = __raw_readl(S3C2410_CLKDIVN);
101
102 /* work out clock scalings */
103
104 hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
105 pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
106
107 /* print brieft summary of clocks, etc */
108
109 printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
110 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
111
112 /* initialise the clocks here, to allow other things like the
113 * console to use them
114 */
115
116 s3c24xx_setup_clocks(fclk, hclk, pclk);
117}
118
119/* fake ARMCLK for use with cpufreq, etc. */
120
121static struct clk s3c2410_armclk = {
122 .name = "armclk",
123 .parent = &clk_f,
124 .id = -1,
125};
126
127static struct clk_lookup s3c2410_clk_lookup[] = {
128 CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
129 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
130};
131
132void __init s3c2410_init_clocks(int xtal)
133{
134 s3c24xx_register_baseclocks(xtal);
135 s3c2410_setup_clocks();
136 s3c2410_baseclk_add();
137 s3c24xx_register_clock(&s3c2410_armclk);
138 clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
139}
140
141struct bus_type s3c2410_subsys = {
142 .name = "s3c2410-core",
143 .dev_name = "s3c2410-core",
144};
145
146/* Note, we would have liked to name this s3c2410-core, but we cannot
147 * register two subsystems with the same name.
148 */
149struct bus_type s3c2410a_subsys = {
150 .name = "s3c2410a-core",
151 .dev_name = "s3c2410a-core",
152};
153
154static struct device s3c2410_dev = {
155 .bus = &s3c2410_subsys,
156};
157
158/* need to register the subsystem before we actually register the device, and
159 * we also need to ensure that it has been initialised before any of the
160 * drivers even try to use it (even if not on an s3c2410 based system)
161 * as a driver which may support both 2410 and 2440 may try and use it.
162*/
163
164static int __init s3c2410_core_init(void)
165{
166 return subsys_system_register(&s3c2410_subsys, NULL);
167}
168
169core_initcall(s3c2410_core_init);
170
171static int __init s3c2410a_core_init(void)
172{
173 return subsys_system_register(&s3c2410a_subsys, NULL);
174}
175
176core_initcall(s3c2410a_core_init);
177
178int __init s3c2410_init(void)
179{
180 printk("S3C2410: Initialising architecture\n");
181
182#ifdef CONFIG_PM
183 register_syscore_ops(&s3c2410_pm_syscore_ops);
184#endif
185 register_syscore_ops(&s3c24xx_irq_syscore_ops);
186
187 return device_register(&s3c2410_dev);
188}
189
190int __init s3c2410a_init(void)
191{
192 s3c2410_dev.bus = &s3c2410a_subsys;
193 return s3c2410_init();
194}
195
196void s3c2410_restart(char mode, const char *cmd)
197{
198 if (mode == 's') {
199 soft_restart(0);
200 }
201
202 arch_wdt_reset();
203
204 /* we'll take a jump through zero as a poor second */
205 soft_restart(0);
206}
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
deleted file mode 100644
index dd5b6388a5a5..000000000000
--- a/arch/arm/mach-s3c2410/sleep.S
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/sleep.S
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * Based on PXA/SA1100 sleep code by:
9 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
10 * Cliff Brake, (c) 2001
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25*/
26
27#include <linux/linkage.h>
28#include <asm/assembler.h>
29#include <mach/hardware.h>
30#include <mach/map.h>
31
32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h>
35#include <plat/regs-serial.h>
36
37 /* s3c2410_cpu_suspend
38 *
39 * put the cpu into sleep mode
40 */
41
42ENTRY(s3c2410_cpu_suspend)
43 @@ prepare cpu to sleep
44
45 ldr r4, =S3C2410_REFRESH
46 ldr r5, =S3C24XX_MISCCR
47 ldr r6, =S3C2410_CLKCON
48 ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
49 ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
50 ldr r9, [ r6 ] @ get CLKCON (and ensure in TLB)
51
52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
54 orr r9, r9, #S3C2410_CLKCON_POWER @ power down command
55
56 teq pc, #0 @ first as a trial-run to load cache
57 bl s3c2410_do_sleep
58 teq r0, r0 @ now do it for real
59 b s3c2410_do_sleep @
60
61 @@ align next bit of code to cache line
62 .align 5
63s3c2410_do_sleep:
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
66 streq r9, [ r6 ] @ CPU sleep
671: beq 1b
68 mov pc, r14
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
deleted file mode 100644
index 29bd3d987bec..000000000000
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ /dev/null
@@ -1,132 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/usb-simtec.c
2 *
3 * Copyright 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * Simtec BAST and Thorcom VR1000 USB port support functions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define DEBUG
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/list.h>
21#include <linux/gpio.h>
22#include <linux/timer.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/io.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/bast-map.h>
32#include <mach/bast-irq.h>
33
34#include <mach/hardware.h>
35#include <asm/irq.h>
36
37#include <plat/usb-control.h>
38#include <plat/devs.h>
39
40#include "usb-simtec.h"
41
42/* control power and monitor over-current events on various Simtec
43 * designed boards.
44*/
45
46static unsigned int power_state[2];
47
48static void
49usb_simtec_powercontrol(int port, int to)
50{
51 pr_debug("usb_simtec_powercontrol(%d,%d)\n", port, to);
52
53 power_state[port] = to;
54
55 if (power_state[0] && power_state[1])
56 gpio_set_value(S3C2410_GPB(4), 0);
57 else
58 gpio_set_value(S3C2410_GPB(4), 1);
59}
60
61static irqreturn_t
62usb_simtec_ocirq(int irq, void *pw)
63{
64 struct s3c2410_hcd_info *info = pw;
65
66 if (gpio_get_value(S3C2410_GPG(10)) == 0) {
67 pr_debug("usb_simtec: over-current irq (oc detected)\n");
68 s3c2410_usb_report_oc(info, 3);
69 } else {
70 pr_debug("usb_simtec: over-current irq (oc cleared)\n");
71 s3c2410_usb_report_oc(info, 0);
72 }
73
74 return IRQ_HANDLED;
75}
76
77static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on)
78{
79 int ret;
80
81 if (on) {
82 ret = request_irq(IRQ_USBOC, usb_simtec_ocirq,
83 IRQF_DISABLED | IRQF_TRIGGER_RISING |
84 IRQF_TRIGGER_FALLING,
85 "USB Over-current", info);
86 if (ret != 0) {
87 printk(KERN_ERR "failed to request usb oc irq\n");
88 }
89 } else {
90 free_irq(IRQ_USBOC, info);
91 }
92}
93
94static struct s3c2410_hcd_info usb_simtec_info __initdata = {
95 .port[0] = {
96 .flags = S3C_HCDFLG_USED
97 },
98 .port[1] = {
99 .flags = S3C_HCDFLG_USED
100 },
101
102 .power_control = usb_simtec_powercontrol,
103 .enable_oc = usb_simtec_enableoc,
104};
105
106
107int usb_simtec_init(void)
108{
109 int ret;
110
111 printk("USB Power Control, Copyright 2004 Simtec Electronics\n");
112
113 ret = gpio_request(S3C2410_GPB(4), "USB power control");
114 if (ret < 0) {
115 pr_err("%s: failed to get GPB4\n", __func__);
116 return ret;
117 }
118
119 ret = gpio_request(S3C2410_GPG(10), "USB overcurrent");
120 if (ret < 0) {
121 pr_err("%s: failed to get GPG10\n", __func__);
122 gpio_free(S3C2410_GPB(4));
123 return ret;
124 }
125
126 /* turn power on */
127 gpio_direction_output(S3C2410_GPB(4), 1);
128 gpio_direction_input(S3C2410_GPG(10));
129
130 s3c_ohci_set_platdata(&usb_simtec_info);
131 return 0;
132}
diff --git a/arch/arm/mach-s3c2410/usb-simtec.h b/arch/arm/mach-s3c2410/usb-simtec.h
deleted file mode 100644
index 03842ede9e71..000000000000
--- a/arch/arm/mach-s3c2410/usb-simtec.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/* linux/arch/arm/mach-s3c2410/usb-simtec.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * Simtec BAST and Thorcom VR1000 USB port support functions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern int usb_simtec_init(void);
16
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 11:12:28 -0500