aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-s3c2410
diff options
context:
space:
mode:
authorBen Dooks <ben-linux@fluff.org>2009-05-17 17:32:23 -0400
committerBen Dooks <ben-linux@fluff.org>2009-05-18 11:26:03 -0400
commit070276d5d049f385763dee19112bea08f56c9a0d (patch)
tree5a32a885de72f18476ff067a25d8a159ac01629d /arch/arm/mach-s3c2410
parent75cbcff3729fe2568dff38d16d6494f8fb7f59fe (diff)
[ARM] S3C24XX: GPIO: Change to macros for GPIO numbering
Prepare to remove the large number of S3C2410_GPxn defines by moving to S3C2410_GPx(n) in arch/arm. The following perl was used to change the files: perl -pi~ -e 's/S3C2410_GP([A-Z])([0-9]+)([^_^0-9])/S3C2410_GP\1\(\2\)\3/g' Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2410')
-rw-r--r--arch/arm/mach-s3c2410/gpio.c4
-rw-r--r--arch/arm/mach-s3c2410/h1940-bluetooth.c24
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-core.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-fns.h8
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h21
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h122
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c50
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c18
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c10
-rw-r--r--arch/arm/mach-s3c2410/pm.c4
-rw-r--r--arch/arm/mach-s3c2410/usb-simtec.c10
14 files changed, 92 insertions, 193 deletions
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
index 36a3132f39e7..bf7fbfe7e4d8 100644
--- a/arch/arm/mach-s3c2410/gpio.c
+++ b/arch/arm/mach-s3c2410/gpio.c
@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
39 unsigned long flags; 39 unsigned long flags;
40 unsigned long val; 40 unsigned long val;
41 41
42 if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) 42 if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
43 return -1; 43 return -1;
44 44
45 config &= 0xff; 45 config &= 0xff;
46 46
47 pin -= S3C2410_GPG8; 47 pin -= S3C2410_GPG(8);
48 reg += pin & ~3; 48 reg += pin & ~3;
49 49
50 local_irq_save(flags); 50 local_irq_save(flags);
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 9bbea8a73ddc..5aabf117cbb0 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -43,9 +43,9 @@ static void h1940bt_enable(int on)
43 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); 43 h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
44 /* Reset the chip */ 44 /* Reset the chip */
45 mdelay(10); 45 mdelay(10);
46 s3c2410_gpio_setpin(S3C2410_GPH1, 1); 46 s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
47 mdelay(10); 47 mdelay(10);
48 s3c2410_gpio_setpin(S3C2410_GPH1, 0); 48 s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
49 49
50 state = 1; 50 state = 1;
51 } 51 }
@@ -54,9 +54,9 @@ static void h1940bt_enable(int on)
54 led_trigger_event(bt_led_trigger, 0); 54 led_trigger_event(bt_led_trigger, 0);
55#endif 55#endif
56 56
57 s3c2410_gpio_setpin(S3C2410_GPH1, 1); 57 s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
58 mdelay(10); 58 mdelay(10);
59 s3c2410_gpio_setpin(S3C2410_GPH1, 0); 59 s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
60 mdelay(10); 60 mdelay(10);
61 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); 61 h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
62 62
@@ -89,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
89static int __init h1940bt_probe(struct platform_device *pdev) 89static int __init h1940bt_probe(struct platform_device *pdev)
90{ 90{
91 /* Configures BT serial port GPIOs */ 91 /* Configures BT serial port GPIOs */
92 s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); 92 s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
93 s3c2410_gpio_pullup(S3C2410_GPH0, 1); 93 s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
94 s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPIO_OUTPUT); 94 s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
95 s3c2410_gpio_pullup(S3C2410_GPH1, 1); 95 s3c2410_gpio_pullup(S3C2410_GPH(1), 1);
96 s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); 96 s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0);
97 s3c2410_gpio_pullup(S3C2410_GPH2, 1); 97 s3c2410_gpio_pullup(S3C2410_GPH(2), 1);
98 s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); 98 s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
99 s3c2410_gpio_pullup(S3C2410_GPH3, 1); 99 s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
100 100
101#ifdef CONFIG_LEDS_H1940 101#ifdef CONFIG_LEDS_H1940
102 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); 102 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
index 6c9fbb99ef14..8fe192081d3a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
24{ 24{
25 struct s3c_gpio_chip *chip; 25 struct s3c_gpio_chip *chip;
26 26
27 if (pin > S3C2410_GPG10) 27 if (pin > S3C2410_GPG(10))
28 return NULL; 28 return NULL;
29 29
30 chip = &s3c24xx_gpios[pin/32]; 30 chip = &s3c24xx_gpios[pin/32];
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index b4f39558beda..801dff13858d 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -30,8 +30,8 @@
30 * set the configuration of the given pin to the value passed. 30 * set the configuration of the given pin to the value passed.
31 * 31 *
32 * eg: 32 * eg:
33 * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); 33 * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
34 * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); 34 * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
35*/ 35*/
36 36
37extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); 37extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
@@ -80,8 +80,8 @@ extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
80 * 80 *
81 * eg; 81 * eg;
82 * 82 *
83 * s3c2410_gpio_pullup(S3C2410_GPB0, 0); 83 * s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
84 * s3c2410_gpio_pullup(S3C2410_GPE8, 0); 84 * s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
85*/ 85*/
86 86
87extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); 87extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index 5213e453df1c..2edbb9c88ab3 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -68,5 +68,26 @@ enum s3c_gpio_number {
68#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) 68#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
69#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) 69#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
70 70
71/* compatibility until drivers can be modified */
72
73#define S3C2410_GPA0 S3C2410_GPA(0)
74#define S3C2410_GPA1 S3C2410_GPA(1)
75#define S3C2410_GPA3 S3C2410_GPA(3)
76#define S3C2410_GPA7 S3C2410_GPA(7)
77
78#define S3C2410_GPE0 S3C2410_GPE(0)
79#define S3C2410_GPE1 S3C2410_GPE(1)
80#define S3C2410_GPE2 S3C2410_GPE(2)
81#define S3C2410_GPE3 S3C2410_GPE(3)
82#define S3C2410_GPE4 S3C2410_GPE(4)
83#define S3C2410_GPE5 S3C2410_GPE(5)
84#define S3C2410_GPE6 S3C2410_GPE(6)
85#define S3C2410_GPE7 S3C2410_GPE(7)
86#define S3C2410_GPE8 S3C2410_GPE(8)
87#define S3C2410_GPE9 S3C2410_GPE(9)
88#define S3C2410_GPE10 S3C2410_GPE(10)
89
90#define S3C2410_GPH10 S3C2410_GPH(10)
91
71#endif /* __MACH_GPIONRS_H */ 92#endif /* __MACH_GPIONRS_H */
72 93
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index 90cefebd2937..b278d0c45ccf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -69,81 +69,58 @@
69#define S3C2400_GPACON S3C2410_GPIOREG(0x00) 69#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
70#define S3C2400_GPADAT S3C2410_GPIOREG(0x04) 70#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
71 71
72#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
73#define S3C2410_GPA0_ADDR0 (1<<0) 72#define S3C2410_GPA0_ADDR0 (1<<0)
74 73
75#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
76#define S3C2410_GPA1_ADDR16 (1<<1) 74#define S3C2410_GPA1_ADDR16 (1<<1)
77 75
78#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
79#define S3C2410_GPA2_ADDR17 (1<<2) 76#define S3C2410_GPA2_ADDR17 (1<<2)
80 77
81#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
82#define S3C2410_GPA3_ADDR18 (1<<3) 78#define S3C2410_GPA3_ADDR18 (1<<3)
83 79
84#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
85#define S3C2410_GPA4_ADDR19 (1<<4) 80#define S3C2410_GPA4_ADDR19 (1<<4)
86 81
87#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
88#define S3C2410_GPA5_ADDR20 (1<<5) 82#define S3C2410_GPA5_ADDR20 (1<<5)
89 83
90#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
91#define S3C2410_GPA6_ADDR21 (1<<6) 84#define S3C2410_GPA6_ADDR21 (1<<6)
92 85
93#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
94#define S3C2410_GPA7_ADDR22 (1<<7) 86#define S3C2410_GPA7_ADDR22 (1<<7)
95 87
96#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
97#define S3C2410_GPA8_ADDR23 (1<<8) 88#define S3C2410_GPA8_ADDR23 (1<<8)
98 89
99#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
100#define S3C2410_GPA9_ADDR24 (1<<9) 90#define S3C2410_GPA9_ADDR24 (1<<9)
101 91
102#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
103#define S3C2410_GPA10_ADDR25 (1<<10) 92#define S3C2410_GPA10_ADDR25 (1<<10)
104#define S3C2400_GPA10_SCKE (1<<10) 93#define S3C2400_GPA10_SCKE (1<<10)
105 94
106#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
107#define S3C2410_GPA11_ADDR26 (1<<11) 95#define S3C2410_GPA11_ADDR26 (1<<11)
108#define S3C2400_GPA11_nCAS0 (1<<11) 96#define S3C2400_GPA11_nCAS0 (1<<11)
109 97
110#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
111#define S3C2410_GPA12_nGCS1 (1<<12) 98#define S3C2410_GPA12_nGCS1 (1<<12)
112#define S3C2400_GPA12_nCAS1 (1<<12) 99#define S3C2400_GPA12_nCAS1 (1<<12)
113 100
114#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
115#define S3C2410_GPA13_nGCS2 (1<<13) 101#define S3C2410_GPA13_nGCS2 (1<<13)
116#define S3C2400_GPA13_nGCS1 (1<<13) 102#define S3C2400_GPA13_nGCS1 (1<<13)
117 103
118#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
119#define S3C2410_GPA14_nGCS3 (1<<14) 104#define S3C2410_GPA14_nGCS3 (1<<14)
120#define S3C2400_GPA14_nGCS2 (1<<14) 105#define S3C2400_GPA14_nGCS2 (1<<14)
121 106
122#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
123#define S3C2410_GPA15_nGCS4 (1<<15) 107#define S3C2410_GPA15_nGCS4 (1<<15)
124#define S3C2400_GPA15_nGCS3 (1<<15) 108#define S3C2400_GPA15_nGCS3 (1<<15)
125 109
126#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
127#define S3C2410_GPA16_nGCS5 (1<<16) 110#define S3C2410_GPA16_nGCS5 (1<<16)
128#define S3C2400_GPA16_nGCS4 (1<<16) 111#define S3C2400_GPA16_nGCS4 (1<<16)
129 112
130#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
131#define S3C2410_GPA17_CLE (1<<17) 113#define S3C2410_GPA17_CLE (1<<17)
132#define S3C2400_GPA17_nGCS5 (1<<17) 114#define S3C2400_GPA17_nGCS5 (1<<17)
133 115
134#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
135#define S3C2410_GPA18_ALE (1<<18) 116#define S3C2410_GPA18_ALE (1<<18)
136 117
137#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
138#define S3C2410_GPA19_nFWE (1<<19) 118#define S3C2410_GPA19_nFWE (1<<19)
139 119
140#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
141#define S3C2410_GPA20_nFRE (1<<20) 120#define S3C2410_GPA20_nFRE (1<<20)
142 121
143#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
144#define S3C2410_GPA21_nRSTOUT (1<<21) 122#define S3C2410_GPA21_nRSTOUT (1<<21)
145 123
146#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
147#define S3C2410_GPA22_nFCE (1<<22) 124#define S3C2410_GPA22_nFCE (1<<22)
148 125
149/* 0x08 and 0x0c are reserved on S3C2410 */ 126/* 0x08 and 0x0c are reserved on S3C2410 */
@@ -171,85 +148,69 @@
171 148
172/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 149/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
173 150
174#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
175#define S3C2410_GPB0_TOUT0 (0x02 << 0) 151#define S3C2410_GPB0_TOUT0 (0x02 << 0)
176#define S3C2400_GPB0_DATA16 (0x02 << 0) 152#define S3C2400_GPB0_DATA16 (0x02 << 0)
177 153
178#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
179#define S3C2410_GPB1_TOUT1 (0x02 << 2) 154#define S3C2410_GPB1_TOUT1 (0x02 << 2)
180#define S3C2400_GPB1_DATA17 (0x02 << 2) 155#define S3C2400_GPB1_DATA17 (0x02 << 2)
181 156
182#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
183#define S3C2410_GPB2_TOUT2 (0x02 << 4) 157#define S3C2410_GPB2_TOUT2 (0x02 << 4)
184#define S3C2400_GPB2_DATA18 (0x02 << 4) 158#define S3C2400_GPB2_DATA18 (0x02 << 4)
185#define S3C2400_GPB2_TCLK1 (0x03 << 4) 159#define S3C2400_GPB2_TCLK1 (0x03 << 4)
186 160
187#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
188#define S3C2410_GPB3_TOUT3 (0x02 << 6) 161#define S3C2410_GPB3_TOUT3 (0x02 << 6)
189#define S3C2400_GPB3_DATA19 (0x02 << 6) 162#define S3C2400_GPB3_DATA19 (0x02 << 6)
190#define S3C2400_GPB3_TXD1 (0x03 << 6) 163#define S3C2400_GPB3_TXD1 (0x03 << 6)
191 164
192#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
193#define S3C2410_GPB4_TCLK0 (0x02 << 8) 165#define S3C2410_GPB4_TCLK0 (0x02 << 8)
194#define S3C2400_GPB4_DATA20 (0x02 << 8) 166#define S3C2400_GPB4_DATA20 (0x02 << 8)
195#define S3C2410_GPB4_MASK (0x03 << 8) 167#define S3C2410_GPB4_MASK (0x03 << 8)
196#define S3C2400_GPB4_RXD1 (0x03 << 8) 168#define S3C2400_GPB4_RXD1 (0x03 << 8)
197#define S3C2400_GPB4_MASK (0x03 << 8) 169#define S3C2400_GPB4_MASK (0x03 << 8)
198 170
199#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
200#define S3C2410_GPB5_nXBACK (0x02 << 10) 171#define S3C2410_GPB5_nXBACK (0x02 << 10)
201#define S3C2443_GPB5_XBACK (0x03 << 10) 172#define S3C2443_GPB5_XBACK (0x03 << 10)
202#define S3C2400_GPB5_DATA21 (0x02 << 10) 173#define S3C2400_GPB5_DATA21 (0x02 << 10)
203#define S3C2400_GPB5_nCTS1 (0x03 << 10) 174#define S3C2400_GPB5_nCTS1 (0x03 << 10)
204 175
205#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
206#define S3C2410_GPB6_nXBREQ (0x02 << 12) 176#define S3C2410_GPB6_nXBREQ (0x02 << 12)
207#define S3C2443_GPB6_XBREQ (0x03 << 12) 177#define S3C2443_GPB6_XBREQ (0x03 << 12)
208#define S3C2400_GPB6_DATA22 (0x02 << 12) 178#define S3C2400_GPB6_DATA22 (0x02 << 12)
209#define S3C2400_GPB6_nRTS1 (0x03 << 12) 179#define S3C2400_GPB6_nRTS1 (0x03 << 12)
210 180
211#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
212#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 181#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
213#define S3C2443_GPB7_XDACK1 (0x03 << 14) 182#define S3C2443_GPB7_XDACK1 (0x03 << 14)
214#define S3C2400_GPB7_DATA23 (0x02 << 14) 183#define S3C2400_GPB7_DATA23 (0x02 << 14)
215 184
216#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
217#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 185#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
218#define S3C2400_GPB8_DATA24 (0x02 << 16) 186#define S3C2400_GPB8_DATA24 (0x02 << 16)
219 187
220#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
221#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 188#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
222#define S3C2443_GPB9_XDACK0 (0x03 << 18) 189#define S3C2443_GPB9_XDACK0 (0x03 << 18)
223#define S3C2400_GPB9_DATA25 (0x02 << 18) 190#define S3C2400_GPB9_DATA25 (0x02 << 18)
224#define S3C2400_GPB9_I2SSDI (0x03 << 18) 191#define S3C2400_GPB9_I2SSDI (0x03 << 18)
225 192
226#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
227#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 193#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
228#define S3C2443_GPB10_XDREQ0 (0x03 << 20) 194#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
229#define S3C2400_GPB10_DATA26 (0x02 << 20) 195#define S3C2400_GPB10_DATA26 (0x02 << 20)
230#define S3C2400_GPB10_nSS (0x03 << 20) 196#define S3C2400_GPB10_nSS (0x03 << 20)
231 197
232#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
233#define S3C2400_GPB11_INP (0x00 << 22) 198#define S3C2400_GPB11_INP (0x00 << 22)
234#define S3C2400_GPB11_OUTP (0x01 << 22) 199#define S3C2400_GPB11_OUTP (0x01 << 22)
235#define S3C2400_GPB11_DATA27 (0x02 << 22) 200#define S3C2400_GPB11_DATA27 (0x02 << 22)
236 201
237#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
238#define S3C2400_GPB12_INP (0x00 << 24) 202#define S3C2400_GPB12_INP (0x00 << 24)
239#define S3C2400_GPB12_OUTP (0x01 << 24) 203#define S3C2400_GPB12_OUTP (0x01 << 24)
240#define S3C2400_GPB12_DATA28 (0x02 << 24) 204#define S3C2400_GPB12_DATA28 (0x02 << 24)
241 205
242#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
243#define S3C2400_GPB13_INP (0x00 << 26) 206#define S3C2400_GPB13_INP (0x00 << 26)
244#define S3C2400_GPB13_OUTP (0x01 << 26) 207#define S3C2400_GPB13_OUTP (0x01 << 26)
245#define S3C2400_GPB13_DATA29 (0x02 << 26) 208#define S3C2400_GPB13_DATA29 (0x02 << 26)
246 209
247#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
248#define S3C2400_GPB14_INP (0x00 << 28) 210#define S3C2400_GPB14_INP (0x00 << 28)
249#define S3C2400_GPB14_OUTP (0x01 << 28) 211#define S3C2400_GPB14_OUTP (0x01 << 28)
250#define S3C2400_GPB14_DATA30 (0x02 << 28) 212#define S3C2400_GPB14_DATA30 (0x02 << 28)
251 213
252#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
253#define S3C2400_GPB15_INP (0x00 << 30) 214#define S3C2400_GPB15_INP (0x00 << 30)
254#define S3C2400_GPB15_OUTP (0x01 << 30) 215#define S3C2400_GPB15_OUTP (0x01 << 30)
255#define S3C2400_GPB15_DATA31 (0x02 << 30) 216#define S3C2400_GPB15_DATA31 (0x02 << 30)
@@ -270,67 +231,51 @@
270#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) 231#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
271#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) 232#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
272 233
273#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
274#define S3C2410_GPC0_LEND (0x02 << 0) 234#define S3C2410_GPC0_LEND (0x02 << 0)
275#define S3C2400_GPC0_VD0 (0x02 << 0) 235#define S3C2400_GPC0_VD0 (0x02 << 0)
276 236
277#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
278#define S3C2410_GPC1_VCLK (0x02 << 2) 237#define S3C2410_GPC1_VCLK (0x02 << 2)
279#define S3C2400_GPC1_VD1 (0x02 << 2) 238#define S3C2400_GPC1_VD1 (0x02 << 2)
280 239
281#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
282#define S3C2410_GPC2_VLINE (0x02 << 4) 240#define S3C2410_GPC2_VLINE (0x02 << 4)
283#define S3C2400_GPC2_VD2 (0x02 << 4) 241#define S3C2400_GPC2_VD2 (0x02 << 4)
284 242
285#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
286#define S3C2410_GPC3_VFRAME (0x02 << 6) 243#define S3C2410_GPC3_VFRAME (0x02 << 6)
287#define S3C2400_GPC3_VD3 (0x02 << 6) 244#define S3C2400_GPC3_VD3 (0x02 << 6)
288 245
289#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
290#define S3C2410_GPC4_VM (0x02 << 8) 246#define S3C2410_GPC4_VM (0x02 << 8)
291#define S3C2400_GPC4_VD4 (0x02 << 8) 247#define S3C2400_GPC4_VD4 (0x02 << 8)
292 248
293#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
294#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 249#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
295#define S3C2400_GPC5_VD5 (0x02 << 10) 250#define S3C2400_GPC5_VD5 (0x02 << 10)
296 251
297#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
298#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 252#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
299#define S3C2400_GPC6_VD6 (0x02 << 12) 253#define S3C2400_GPC6_VD6 (0x02 << 12)
300 254
301#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
302#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 255#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
303#define S3C2400_GPC7_VD7 (0x02 << 14) 256#define S3C2400_GPC7_VD7 (0x02 << 14)
304 257
305#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
306#define S3C2410_GPC8_VD0 (0x02 << 16) 258#define S3C2410_GPC8_VD0 (0x02 << 16)
307#define S3C2400_GPC8_VD8 (0x02 << 16) 259#define S3C2400_GPC8_VD8 (0x02 << 16)
308 260
309#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
310#define S3C2410_GPC9_VD1 (0x02 << 18) 261#define S3C2410_GPC9_VD1 (0x02 << 18)
311#define S3C2400_GPC9_VD9 (0x02 << 18) 262#define S3C2400_GPC9_VD9 (0x02 << 18)
312 263
313#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
314#define S3C2410_GPC10_VD2 (0x02 << 20) 264#define S3C2410_GPC10_VD2 (0x02 << 20)
315#define S3C2400_GPC10_VD10 (0x02 << 20) 265#define S3C2400_GPC10_VD10 (0x02 << 20)
316 266
317#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
318#define S3C2410_GPC11_VD3 (0x02 << 22) 267#define S3C2410_GPC11_VD3 (0x02 << 22)
319#define S3C2400_GPC11_VD11 (0x02 << 22) 268#define S3C2400_GPC11_VD11 (0x02 << 22)
320 269
321#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
322#define S3C2410_GPC12_VD4 (0x02 << 24) 270#define S3C2410_GPC12_VD4 (0x02 << 24)
323#define S3C2400_GPC12_VD12 (0x02 << 24) 271#define S3C2400_GPC12_VD12 (0x02 << 24)
324 272
325#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
326#define S3C2410_GPC13_VD5 (0x02 << 26) 273#define S3C2410_GPC13_VD5 (0x02 << 26)
327#define S3C2400_GPC13_VD13 (0x02 << 26) 274#define S3C2400_GPC13_VD13 (0x02 << 26)
328 275
329#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
330#define S3C2410_GPC14_VD6 (0x02 << 28) 276#define S3C2410_GPC14_VD6 (0x02 << 28)
331#define S3C2400_GPC14_VD14 (0x02 << 28) 277#define S3C2400_GPC14_VD14 (0x02 << 28)
332 278
333#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
334#define S3C2410_GPC15_VD7 (0x02 << 30) 279#define S3C2410_GPC15_VD7 (0x02 << 30)
335#define S3C2400_GPC15_VD15 (0x02 << 30) 280#define S3C2400_GPC15_VD15 (0x02 << 30)
336 281
@@ -355,67 +300,51 @@
355#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) 300#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
356#define S3C2400_GPDUP S3C2410_GPIOREG(0x28) 301#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
357 302
358#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
359#define S3C2410_GPD0_VD8 (0x02 << 0) 303#define S3C2410_GPD0_VD8 (0x02 << 0)
360#define S3C2400_GPD0_VFRAME (0x02 << 0) 304#define S3C2400_GPD0_VFRAME (0x02 << 0)
361#define S3C2442_GPD0_nSPICS1 (0x03 << 0) 305#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
362 306
363#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
364#define S3C2410_GPD1_VD9 (0x02 << 2) 307#define S3C2410_GPD1_VD9 (0x02 << 2)
365#define S3C2400_GPD1_VM (0x02 << 2) 308#define S3C2400_GPD1_VM (0x02 << 2)
366#define S3C2442_GPD1_SPICLK1 (0x03 << 2) 309#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
367 310
368#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
369#define S3C2410_GPD2_VD10 (0x02 << 4) 311#define S3C2410_GPD2_VD10 (0x02 << 4)
370#define S3C2400_GPD2_VLINE (0x02 << 4) 312#define S3C2400_GPD2_VLINE (0x02 << 4)
371 313
372#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
373#define S3C2410_GPD3_VD11 (0x02 << 6) 314#define S3C2410_GPD3_VD11 (0x02 << 6)
374#define S3C2400_GPD3_VCLK (0x02 << 6) 315#define S3C2400_GPD3_VCLK (0x02 << 6)
375 316
376#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
377#define S3C2410_GPD4_VD12 (0x02 << 8) 317#define S3C2410_GPD4_VD12 (0x02 << 8)
378#define S3C2400_GPD4_LEND (0x02 << 8) 318#define S3C2400_GPD4_LEND (0x02 << 8)
379 319
380#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
381#define S3C2410_GPD5_VD13 (0x02 << 10) 320#define S3C2410_GPD5_VD13 (0x02 << 10)
382#define S3C2400_GPD5_TOUT0 (0x02 << 10) 321#define S3C2400_GPD5_TOUT0 (0x02 << 10)
383 322
384#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
385#define S3C2410_GPD6_VD14 (0x02 << 12) 323#define S3C2410_GPD6_VD14 (0x02 << 12)
386#define S3C2400_GPD6_TOUT1 (0x02 << 12) 324#define S3C2400_GPD6_TOUT1 (0x02 << 12)
387 325
388#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
389#define S3C2410_GPD7_VD15 (0x02 << 14) 326#define S3C2410_GPD7_VD15 (0x02 << 14)
390#define S3C2400_GPD7_TOUT2 (0x02 << 14) 327#define S3C2400_GPD7_TOUT2 (0x02 << 14)
391 328
392#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
393#define S3C2410_GPD8_VD16 (0x02 << 16) 329#define S3C2410_GPD8_VD16 (0x02 << 16)
394#define S3C2400_GPD8_TOUT3 (0x02 << 16) 330#define S3C2400_GPD8_TOUT3 (0x02 << 16)
395 331
396#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
397#define S3C2410_GPD9_VD17 (0x02 << 18) 332#define S3C2410_GPD9_VD17 (0x02 << 18)
398#define S3C2400_GPD9_TCLK0 (0x02 << 18) 333#define S3C2400_GPD9_TCLK0 (0x02 << 18)
399#define S3C2410_GPD9_MASK (0x03 << 18) 334#define S3C2410_GPD9_MASK (0x03 << 18)
400 335
401#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
402#define S3C2410_GPD10_VD18 (0x02 << 20) 336#define S3C2410_GPD10_VD18 (0x02 << 20)
403#define S3C2400_GPD10_nWAIT (0x02 << 20) 337#define S3C2400_GPD10_nWAIT (0x02 << 20)
404 338
405#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
406#define S3C2410_GPD11_VD19 (0x02 << 22) 339#define S3C2410_GPD11_VD19 (0x02 << 22)
407 340
408#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
409#define S3C2410_GPD12_VD20 (0x02 << 24) 341#define S3C2410_GPD12_VD20 (0x02 << 24)
410 342
411#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
412#define S3C2410_GPD13_VD21 (0x02 << 26) 343#define S3C2410_GPD13_VD21 (0x02 << 26)
413 344
414#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
415#define S3C2410_GPD14_VD22 (0x02 << 28) 345#define S3C2410_GPD14_VD22 (0x02 << 28)
416#define S3C2410_GPD14_nSS1 (0x03 << 28) 346#define S3C2410_GPD14_nSS1 (0x03 << 28)
417 347
418#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
419#define S3C2410_GPD15_VD23 (0x02 << 30) 348#define S3C2410_GPD15_VD23 (0x02 << 30)
420#define S3C2410_GPD15_nSS0 (0x03 << 30) 349#define S3C2410_GPD15_nSS0 (0x03 << 30)
421 350
@@ -441,26 +370,22 @@
441#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) 370#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
442#define S3C2400_GPEUP S3C2410_GPIOREG(0x34) 371#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
443 372
444#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
445#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 373#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
446#define S3C2443_GPE0_AC_nRESET (0x03 << 0) 374#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
447#define S3C2400_GPE0_EINT0 (0x02 << 0) 375#define S3C2400_GPE0_EINT0 (0x02 << 0)
448#define S3C2410_GPE0_MASK (0x03 << 0) 376#define S3C2410_GPE0_MASK (0x03 << 0)
449 377
450#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
451#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 378#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
452#define S3C2443_GPE1_AC_SYNC (0x03 << 2) 379#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
453#define S3C2400_GPE1_EINT1 (0x02 << 2) 380#define S3C2400_GPE1_EINT1 (0x02 << 2)
454#define S3C2400_GPE1_nSS (0x03 << 2) 381#define S3C2400_GPE1_nSS (0x03 << 2)
455#define S3C2410_GPE1_MASK (0x03 << 2) 382#define S3C2410_GPE1_MASK (0x03 << 2)
456 383
457#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
458#define S3C2410_GPE2_CDCLK (0x02 << 4) 384#define S3C2410_GPE2_CDCLK (0x02 << 4)
459#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 385#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
460#define S3C2400_GPE2_EINT2 (0x02 << 4) 386#define S3C2400_GPE2_EINT2 (0x02 << 4)
461#define S3C2400_GPE2_I2SSDI (0x03 << 4) 387#define S3C2400_GPE2_I2SSDI (0x03 << 4)
462 388
463#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
464#define S3C2410_GPE3_I2SSDI (0x02 << 6) 389#define S3C2410_GPE3_I2SSDI (0x02 << 6)
465#define S3C2443_GPE3_AC_SDI (0x03 << 6) 390#define S3C2443_GPE3_AC_SDI (0x03 << 6)
466#define S3C2400_GPE3_EINT3 (0x02 << 6) 391#define S3C2400_GPE3_EINT3 (0x02 << 6)
@@ -468,7 +393,6 @@
468#define S3C2410_GPE3_nSS0 (0x03 << 6) 393#define S3C2410_GPE3_nSS0 (0x03 << 6)
469#define S3C2410_GPE3_MASK (0x03 << 6) 394#define S3C2410_GPE3_MASK (0x03 << 6)
470 395
471#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
472#define S3C2410_GPE4_I2SSDO (0x02 << 8) 396#define S3C2410_GPE4_I2SSDO (0x02 << 8)
473#define S3C2443_GPE4_AC_SDO (0x03 << 8) 397#define S3C2443_GPE4_AC_SDO (0x03 << 8)
474#define S3C2400_GPE4_EINT4 (0x02 << 8) 398#define S3C2400_GPE4_EINT4 (0x02 << 8)
@@ -476,59 +400,48 @@
476#define S3C2410_GPE4_I2SSDI (0x03 << 8) 400#define S3C2410_GPE4_I2SSDI (0x03 << 8)
477#define S3C2410_GPE4_MASK (0x03 << 8) 401#define S3C2410_GPE4_MASK (0x03 << 8)
478 402
479#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
480#define S3C2410_GPE5_SDCLK (0x02 << 10) 403#define S3C2410_GPE5_SDCLK (0x02 << 10)
481#define S3C2443_GPE5_SD1_CLK (0x02 << 10) 404#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
482#define S3C2400_GPE5_EINT5 (0x02 << 10) 405#define S3C2400_GPE5_EINT5 (0x02 << 10)
483#define S3C2400_GPE5_TCLK1 (0x03 << 10) 406#define S3C2400_GPE5_TCLK1 (0x03 << 10)
484 407
485#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
486#define S3C2410_GPE6_SDCMD (0x02 << 12) 408#define S3C2410_GPE6_SDCMD (0x02 << 12)
487#define S3C2443_GPE6_SD1_CMD (0x02 << 12) 409#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
488#define S3C2443_GPE6_AC_BITCLK (0x03 << 12) 410#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
489#define S3C2400_GPE6_EINT6 (0x02 << 12) 411#define S3C2400_GPE6_EINT6 (0x02 << 12)
490 412
491#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
492#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 413#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
493#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 414#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
494#define S3C2443_GPE7_AC_SDI (0x03 << 14) 415#define S3C2443_GPE7_AC_SDI (0x03 << 14)
495#define S3C2400_GPE7_EINT7 (0x02 << 14) 416#define S3C2400_GPE7_EINT7 (0x02 << 14)
496 417
497#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
498#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 418#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
499#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 419#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
500#define S3C2443_GPE8_AC_SDO (0x03 << 16) 420#define S3C2443_GPE8_AC_SDO (0x03 << 16)
501#define S3C2400_GPE8_nXDACK0 (0x02 << 16) 421#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
502 422
503#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
504#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 423#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
505#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 424#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
506#define S3C2443_GPE9_AC_SYNC (0x03 << 18) 425#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
507#define S3C2400_GPE9_nXDACK1 (0x02 << 18) 426#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
508#define S3C2400_GPE9_nXBACK (0x03 << 18) 427#define S3C2400_GPE9_nXBACK (0x03 << 18)
509 428
510#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
511#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 429#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
512#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 430#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
513#define S3C2443_GPE10_AC_nRESET (0x03 << 20) 431#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
514#define S3C2400_GPE10_nXDREQ0 (0x02 << 20) 432#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
515 433
516#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
517#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 434#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
518#define S3C2400_GPE11_nXDREQ1 (0x02 << 22) 435#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
519#define S3C2400_GPE11_nXBREQ (0x03 << 22) 436#define S3C2400_GPE11_nXBREQ (0x03 << 22)
520 437
521#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
522#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 438#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
523 439
524#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
525#define S3C2410_GPE13_SPICLK0 (0x02 << 26) 440#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
526 441
527#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
528#define S3C2410_GPE14_IICSCL (0x02 << 28) 442#define S3C2410_GPE14_IICSCL (0x02 << 28)
529#define S3C2410_GPE14_MASK (0x03 << 28) 443#define S3C2410_GPE14_MASK (0x03 << 28)
530 444
531#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
532#define S3C2410_GPE15_IICSDA (0x02 << 30) 445#define S3C2410_GPE15_IICSDA (0x02 << 30)
533#define S3C2410_GPE15_MASK (0x03 << 30) 446#define S3C2410_GPE15_MASK (0x03 << 30)
534 447
@@ -564,39 +477,31 @@
564#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) 477#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
565#define S3C2400_GPFUP S3C2410_GPIOREG(0x40) 478#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
566 479
567#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
568#define S3C2410_GPF0_EINT0 (0x02 << 0) 480#define S3C2410_GPF0_EINT0 (0x02 << 0)
569#define S3C2400_GPF0_RXD0 (0x02 << 0) 481#define S3C2400_GPF0_RXD0 (0x02 << 0)
570 482
571#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
572#define S3C2410_GPF1_EINT1 (0x02 << 2) 483#define S3C2410_GPF1_EINT1 (0x02 << 2)
573#define S3C2400_GPF1_RXD1 (0x02 << 2) 484#define S3C2400_GPF1_RXD1 (0x02 << 2)
574#define S3C2400_GPF1_IICSDA (0x03 << 2) 485#define S3C2400_GPF1_IICSDA (0x03 << 2)
575 486
576#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
577#define S3C2410_GPF2_EINT2 (0x02 << 4) 487#define S3C2410_GPF2_EINT2 (0x02 << 4)
578#define S3C2400_GPF2_TXD0 (0x02 << 4) 488#define S3C2400_GPF2_TXD0 (0x02 << 4)
579 489
580#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
581#define S3C2410_GPF3_EINT3 (0x02 << 6) 490#define S3C2410_GPF3_EINT3 (0x02 << 6)
582#define S3C2400_GPF3_TXD1 (0x02 << 6) 491#define S3C2400_GPF3_TXD1 (0x02 << 6)
583#define S3C2400_GPF3_IICSCL (0x03 << 6) 492#define S3C2400_GPF3_IICSCL (0x03 << 6)
584 493
585#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
586#define S3C2410_GPF4_EINT4 (0x02 << 8) 494#define S3C2410_GPF4_EINT4 (0x02 << 8)
587#define S3C2400_GPF4_nRTS0 (0x02 << 8) 495#define S3C2400_GPF4_nRTS0 (0x02 << 8)
588#define S3C2400_GPF4_nXBACK (0x03 << 8) 496#define S3C2400_GPF4_nXBACK (0x03 << 8)
589 497
590#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
591#define S3C2410_GPF5_EINT5 (0x02 << 10) 498#define S3C2410_GPF5_EINT5 (0x02 << 10)
592#define S3C2400_GPF5_nCTS0 (0x02 << 10) 499#define S3C2400_GPF5_nCTS0 (0x02 << 10)
593#define S3C2400_GPF5_nXBREQ (0x03 << 10) 500#define S3C2400_GPF5_nXBREQ (0x03 << 10)
594 501
595#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
596#define S3C2410_GPF6_EINT6 (0x02 << 12) 502#define S3C2410_GPF6_EINT6 (0x02 << 12)
597#define S3C2400_GPF6_CLKOUT (0x02 << 12) 503#define S3C2400_GPF6_CLKOUT (0x02 << 12)
598 504
599#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
600#define S3C2410_GPF7_EINT7 (0x02 << 14) 505#define S3C2410_GPF7_EINT7 (0x02 << 14)
601 506
602#define S3C2410_GPF_PUPDIS(x) (1<<(x)) 507#define S3C2410_GPF_PUPDIS(x) (1<<(x))
@@ -621,85 +526,69 @@
621#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) 526#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
622#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) 527#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
623 528
624#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
625#define S3C2410_GPG0_EINT8 (0x02 << 0) 529#define S3C2410_GPG0_EINT8 (0x02 << 0)
626#define S3C2400_GPG0_I2SLRCK (0x02 << 0) 530#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
627 531
628#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
629#define S3C2410_GPG1_EINT9 (0x02 << 2) 532#define S3C2410_GPG1_EINT9 (0x02 << 2)
630#define S3C2400_GPG1_I2SSCLK (0x02 << 2) 533#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
631 534
632#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
633#define S3C2410_GPG2_EINT10 (0x02 << 4) 535#define S3C2410_GPG2_EINT10 (0x02 << 4)
634#define S3C2410_GPG2_nSS0 (0x03 << 4) 536#define S3C2410_GPG2_nSS0 (0x03 << 4)
635#define S3C2400_GPG2_CDCLK (0x02 << 4) 537#define S3C2400_GPG2_CDCLK (0x02 << 4)
636 538
637#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
638#define S3C2410_GPG3_EINT11 (0x02 << 6) 539#define S3C2410_GPG3_EINT11 (0x02 << 6)
639#define S3C2410_GPG3_nSS1 (0x03 << 6) 540#define S3C2410_GPG3_nSS1 (0x03 << 6)
640#define S3C2400_GPG3_I2SSDO (0x02 << 6) 541#define S3C2400_GPG3_I2SSDO (0x02 << 6)
641#define S3C2400_GPG3_I2SSDI (0x03 << 6) 542#define S3C2400_GPG3_I2SSDI (0x03 << 6)
642 543
643#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
644#define S3C2410_GPG4_EINT12 (0x02 << 8) 544#define S3C2410_GPG4_EINT12 (0x02 << 8)
645#define S3C2400_GPG4_MMCCLK (0x02 << 8) 545#define S3C2400_GPG4_MMCCLK (0x02 << 8)
646#define S3C2400_GPG4_I2SSDI (0x03 << 8) 546#define S3C2400_GPG4_I2SSDI (0x03 << 8)
647#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 547#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
648#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 548#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
649 549
650#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
651#define S3C2410_GPG5_EINT13 (0x02 << 10) 550#define S3C2410_GPG5_EINT13 (0x02 << 10)
652#define S3C2400_GPG5_MMCCMD (0x02 << 10) 551#define S3C2400_GPG5_MMCCMD (0x02 << 10)
653#define S3C2400_GPG5_IICSDA (0x03 << 10) 552#define S3C2400_GPG5_IICSDA (0x03 << 10)
654#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 553#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
655 554
656#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
657#define S3C2410_GPG6_EINT14 (0x02 << 12) 555#define S3C2410_GPG6_EINT14 (0x02 << 12)
658#define S3C2400_GPG6_MMCDAT (0x02 << 12) 556#define S3C2400_GPG6_MMCDAT (0x02 << 12)
659#define S3C2400_GPG6_IICSCL (0x03 << 12) 557#define S3C2400_GPG6_IICSCL (0x03 << 12)
660#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 558#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
661 559
662#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
663#define S3C2410_GPG7_EINT15 (0x02 << 14) 560#define S3C2410_GPG7_EINT15 (0x02 << 14)
664#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 561#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
665#define S3C2400_GPG7_SPIMISO (0x02 << 14) 562#define S3C2400_GPG7_SPIMISO (0x02 << 14)
666#define S3C2400_GPG7_IICSDA (0x03 << 14) 563#define S3C2400_GPG7_IICSDA (0x03 << 14)
667 564
668#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
669#define S3C2410_GPG8_EINT16 (0x02 << 16) 565#define S3C2410_GPG8_EINT16 (0x02 << 16)
670#define S3C2400_GPG8_SPIMOSI (0x02 << 16) 566#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
671#define S3C2400_GPG8_IICSCL (0x03 << 16) 567#define S3C2400_GPG8_IICSCL (0x03 << 16)
672 568
673#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
674#define S3C2410_GPG9_EINT17 (0x02 << 18) 569#define S3C2410_GPG9_EINT17 (0x02 << 18)
675#define S3C2400_GPG9_SPICLK (0x02 << 18) 570#define S3C2400_GPG9_SPICLK (0x02 << 18)
676#define S3C2400_GPG9_MMCCLK (0x03 << 18) 571#define S3C2400_GPG9_MMCCLK (0x03 << 18)
677 572
678#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
679#define S3C2410_GPG10_EINT18 (0x02 << 20) 573#define S3C2410_GPG10_EINT18 (0x02 << 20)
680 574
681#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
682#define S3C2410_GPG11_EINT19 (0x02 << 22) 575#define S3C2410_GPG11_EINT19 (0x02 << 22)
683#define S3C2410_GPG11_TCLK1 (0x03 << 22) 576#define S3C2410_GPG11_TCLK1 (0x03 << 22)
684#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) 577#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
685 578
686#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
687#define S3C2410_GPG12_EINT20 (0x02 << 24) 579#define S3C2410_GPG12_EINT20 (0x02 << 24)
688#define S3C2410_GPG12_XMON (0x03 << 24) 580#define S3C2410_GPG12_XMON (0x03 << 24)
689#define S3C2442_GPG12_nSPICS0 (0x03 << 24) 581#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
690#define S3C2443_GPG12_nINPACK (0x03 << 24) 582#define S3C2443_GPG12_nINPACK (0x03 << 24)
691 583
692#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
693#define S3C2410_GPG13_EINT21 (0x02 << 26) 584#define S3C2410_GPG13_EINT21 (0x02 << 26)
694#define S3C2410_GPG13_nXPON (0x03 << 26) 585#define S3C2410_GPG13_nXPON (0x03 << 26)
695#define S3C2443_GPG13_CF_nREG (0x03 << 26) 586#define S3C2443_GPG13_CF_nREG (0x03 << 26)
696 587
697#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
698#define S3C2410_GPG14_EINT22 (0x02 << 28) 588#define S3C2410_GPG14_EINT22 (0x02 << 28)
699#define S3C2410_GPG14_YMON (0x03 << 28) 589#define S3C2410_GPG14_YMON (0x03 << 28)
700#define S3C2443_GPG14_CF_RESET (0x03 << 28) 590#define S3C2443_GPG14_CF_RESET (0x03 << 28)
701 591
702#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
703#define S3C2410_GPG15_EINT23 (0x02 << 30) 592#define S3C2410_GPG15_EINT23 (0x02 << 30)
704#define S3C2410_GPG15_nYPON (0x03 << 30) 593#define S3C2410_GPG15_nYPON (0x03 << 30)
705#define S3C2443_GPG15_CF_PWR (0x03 << 30) 594#define S3C2443_GPG15_CF_PWR (0x03 << 30)
@@ -718,40 +607,29 @@
718#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) 607#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
719#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 608#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
720 609
721#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
722#define S3C2410_GPH0_nCTS0 (0x02 << 0) 610#define S3C2410_GPH0_nCTS0 (0x02 << 0)
723 611
724#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
725#define S3C2410_GPH1_nRTS0 (0x02 << 2) 612#define S3C2410_GPH1_nRTS0 (0x02 << 2)
726 613
727#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
728#define S3C2410_GPH2_TXD0 (0x02 << 4) 614#define S3C2410_GPH2_TXD0 (0x02 << 4)
729 615
730#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
731#define S3C2410_GPH3_RXD0 (0x02 << 6) 616#define S3C2410_GPH3_RXD0 (0x02 << 6)
732 617
733#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
734#define S3C2410_GPH4_TXD1 (0x02 << 8) 618#define S3C2410_GPH4_TXD1 (0x02 << 8)
735 619
736#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
737#define S3C2410_GPH5_RXD1 (0x02 << 10) 620#define S3C2410_GPH5_RXD1 (0x02 << 10)
738 621
739#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
740#define S3C2410_GPH6_TXD2 (0x02 << 12) 622#define S3C2410_GPH6_TXD2 (0x02 << 12)
741#define S3C2410_GPH6_nRTS1 (0x03 << 12) 623#define S3C2410_GPH6_nRTS1 (0x03 << 12)
742 624
743#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
744#define S3C2410_GPH7_RXD2 (0x02 << 14) 625#define S3C2410_GPH7_RXD2 (0x02 << 14)
745#define S3C2410_GPH7_nCTS1 (0x03 << 14) 626#define S3C2410_GPH7_nCTS1 (0x03 << 14)
746 627
747#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
748#define S3C2410_GPH8_UCLK (0x02 << 16) 628#define S3C2410_GPH8_UCLK (0x02 << 16)
749 629
750#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
751#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 630#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
752#define S3C2442_GPH9_nSPICS0 (0x03 << 18) 631#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
753 632
754#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
755#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 633#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
756 634
757/* The S3C2412 and S3C2413 move the GPJ register set to after 635/* The S3C2412 and S3C2413 move the GPJ register set to after
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 43f7536c5291..06a84adfb13f 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -225,8 +225,8 @@ static void amlm5900_init_pm(void)
225 } else { 225 } else {
226 enable_irq_wake(IRQ_EINT9); 226 enable_irq_wake(IRQ_EINT9);
227 /* configure the suspend/resume status pin */ 227 /* configure the suspend/resume status pin */
228 s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT); 228 s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT);
229 s3c2410_gpio_pullup(S3C2410_GPF2, 0); 229 s3c2410_gpio_pullup(S3C2410_GPF(2), 0);
230 } 230 }
231} 231}
232static void __init amlm5900_init(void) 232static void __init amlm5900_init(void)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 3410caefb869..496463768de7 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -213,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
213static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) 213static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
214{ 214{
215 /* ensure that an nRESET is not generated on resume. */ 215 /* ensure that an nRESET is not generated on resume. */
216 s3c2410_gpio_setpin(S3C2410_GPA21, 1); 216 s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
217 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPIO_OUTPUT); 217 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
218 218
219 return 0; 219 return 0;
220} 220}
221 221
222static int bast_pm_resume(struct sys_device *sd) 222static int bast_pm_resume(struct sys_device *sd)
223{ 223{
224 s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); 224 s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
225 return 0; 225 return 0;
226} 226}
227 227
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 7a7c4da4c256..d9cd5ddecf4a 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
127 127
128static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { 128static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = {
129 .udc_command = h1940_udc_pullup, 129 .udc_command = h1940_udc_pullup,
130 .vbus_pin = S3C2410_GPG5, 130 .vbus_pin = S3C2410_GPG(5),
131 .vbus_pin_inverted = 1, 131 .vbus_pin_inverted = 1,
132}; 132};
133 133
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 83705036ca6b..0f6ed61af415 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -86,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
86{ 86{
87 switch (cmd) { 87 switch (cmd) {
88 case S3C2410_UDC_P_ENABLE : 88 case S3C2410_UDC_P_ENABLE :
89 s3c2410_gpio_setpin(S3C2410_GPB3, 1); 89 s3c2410_gpio_setpin(S3C2410_GPB(3), 1);
90 break; 90 break;
91 case S3C2410_UDC_P_DISABLE : 91 case S3C2410_UDC_P_DISABLE :
92 s3c2410_gpio_setpin(S3C2410_GPB3, 0); 92 s3c2410_gpio_setpin(S3C2410_GPB(3), 0);
93 break; 93 break;
94 case S3C2410_UDC_P_RESET : 94 case S3C2410_UDC_P_RESET :
95 break; 95 break;
@@ -100,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
100 100
101static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { 101static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
102 .udc_command = n30_udc_pullup, 102 .udc_command = n30_udc_pullup,
103 .vbus_pin = S3C2410_GPG1, 103 .vbus_pin = S3C2410_GPG(1),
104 .vbus_pin_inverted = 0, 104 .vbus_pin_inverted = 0,
105}; 105};
106 106
107static struct gpio_keys_button n30_buttons[] = { 107static struct gpio_keys_button n30_buttons[] = {
108 { 108 {
109 .gpio = S3C2410_GPF0, 109 .gpio = S3C2410_GPF(0),
110 .code = KEY_POWER, 110 .code = KEY_POWER,
111 .desc = "Power", 111 .desc = "Power",
112 .active_low = 0, 112 .active_low = 0,
113 }, 113 },
114 { 114 {
115 .gpio = S3C2410_GPG9, 115 .gpio = S3C2410_GPG(9),
116 .code = KEY_UP, 116 .code = KEY_UP,
117 .desc = "Thumbwheel Up", 117 .desc = "Thumbwheel Up",
118 .active_low = 0, 118 .active_low = 0,
119 }, 119 },
120 { 120 {
121 .gpio = S3C2410_GPG8, 121 .gpio = S3C2410_GPG(8),
122 .code = KEY_DOWN, 122 .code = KEY_DOWN,
123 .desc = "Thumbwheel Down", 123 .desc = "Thumbwheel Down",
124 .active_low = 0, 124 .active_low = 0,
125 }, 125 },
126 { 126 {
127 .gpio = S3C2410_GPG7, 127 .gpio = S3C2410_GPG(7),
128 .code = KEY_ENTER, 128 .code = KEY_ENTER,
129 .desc = "Thumbwheel Press", 129 .desc = "Thumbwheel Press",
130 .active_low = 0, 130 .active_low = 0,
131 }, 131 },
132 { 132 {
133 .gpio = S3C2410_GPF7, 133 .gpio = S3C2410_GPF(7),
134 .code = KEY_HOMEPAGE, 134 .code = KEY_HOMEPAGE,
135 .desc = "Home", 135 .desc = "Home",
136 .active_low = 0, 136 .active_low = 0,
137 }, 137 },
138 { 138 {
139 .gpio = S3C2410_GPF6, 139 .gpio = S3C2410_GPF(6),
140 .code = KEY_CALENDAR, 140 .code = KEY_CALENDAR,
141 .desc = "Calendar", 141 .desc = "Calendar",
142 .active_low = 0, 142 .active_low = 0,
143 }, 143 },
144 { 144 {
145 .gpio = S3C2410_GPF5, 145 .gpio = S3C2410_GPF(5),
146 .code = KEY_ADDRESSBOOK, 146 .code = KEY_ADDRESSBOOK,
147 .desc = "Contacts", 147 .desc = "Contacts",
148 .active_low = 0, 148 .active_low = 0,
149 }, 149 },
150 { 150 {
151 .gpio = S3C2410_GPF4, 151 .gpio = S3C2410_GPF(4),
152 .code = KEY_MAIL, 152 .code = KEY_MAIL,
153 .desc = "Mail", 153 .desc = "Mail",
154 .active_low = 0, 154 .active_low = 0,
@@ -170,73 +170,73 @@ static struct platform_device n30_button_device = {
170 170
171static struct gpio_keys_button n35_buttons[] = { 171static struct gpio_keys_button n35_buttons[] = {
172 { 172 {
173 .gpio = S3C2410_GPF0, 173 .gpio = S3C2410_GPF(0),
174 .code = KEY_POWER, 174 .code = KEY_POWER,
175 .desc = "Power", 175 .desc = "Power",
176 .active_low = 0, 176 .active_low = 0,
177 }, 177 },
178 { 178 {
179 .gpio = S3C2410_GPG9, 179 .gpio = S3C2410_GPG(9),
180 .code = KEY_UP, 180 .code = KEY_UP,
181 .desc = "Joystick Up", 181 .desc = "Joystick Up",
182 .active_low = 0, 182 .active_low = 0,
183 }, 183 },
184 { 184 {
185 .gpio = S3C2410_GPG8, 185 .gpio = S3C2410_GPG(8),
186 .code = KEY_DOWN, 186 .code = KEY_DOWN,
187 .desc = "Joystick Down", 187 .desc = "Joystick Down",
188 .active_low = 0, 188 .active_low = 0,
189 }, 189 },
190 { 190 {
191 .gpio = S3C2410_GPG6, 191 .gpio = S3C2410_GPG(6),
192 .code = KEY_DOWN, 192 .code = KEY_DOWN,
193 .desc = "Joystick Left", 193 .desc = "Joystick Left",
194 .active_low = 0, 194 .active_low = 0,
195 }, 195 },
196 { 196 {
197 .gpio = S3C2410_GPG5, 197 .gpio = S3C2410_GPG(5),
198 .code = KEY_DOWN, 198 .code = KEY_DOWN,
199 .desc = "Joystick Right", 199 .desc = "Joystick Right",
200 .active_low = 0, 200 .active_low = 0,
201 }, 201 },
202 { 202 {
203 .gpio = S3C2410_GPG7, 203 .gpio = S3C2410_GPG(7),
204 .code = KEY_ENTER, 204 .code = KEY_ENTER,
205 .desc = "Joystick Press", 205 .desc = "Joystick Press",
206 .active_low = 0, 206 .active_low = 0,
207 }, 207 },
208 { 208 {
209 .gpio = S3C2410_GPF7, 209 .gpio = S3C2410_GPF(7),
210 .code = KEY_HOMEPAGE, 210 .code = KEY_HOMEPAGE,
211 .desc = "Home", 211 .desc = "Home",
212 .active_low = 0, 212 .active_low = 0,
213 }, 213 },
214 { 214 {
215 .gpio = S3C2410_GPF6, 215 .gpio = S3C2410_GPF(6),
216 .code = KEY_CALENDAR, 216 .code = KEY_CALENDAR,
217 .desc = "Calendar", 217 .desc = "Calendar",
218 .active_low = 0, 218 .active_low = 0,
219 }, 219 },
220 { 220 {
221 .gpio = S3C2410_GPF5, 221 .gpio = S3C2410_GPF(5),
222 .code = KEY_ADDRESSBOOK, 222 .code = KEY_ADDRESSBOOK,
223 .desc = "Contacts", 223 .desc = "Contacts",
224 .active_low = 0, 224 .active_low = 0,
225 }, 225 },
226 { 226 {
227 .gpio = S3C2410_GPF4, 227 .gpio = S3C2410_GPF(4),
228 .code = KEY_MAIL, 228 .code = KEY_MAIL,
229 .desc = "Mail", 229 .desc = "Mail",
230 .active_low = 0, 230 .active_low = 0,
231 }, 231 },
232 { 232 {
233 .gpio = S3C2410_GPF3, 233 .gpio = S3C2410_GPF(3),
234 .code = SW_RADIO, 234 .code = SW_RADIO,
235 .desc = "GPS Antenna", 235 .desc = "GPS Antenna",
236 .active_low = 0, 236 .active_low = 0,
237 }, 237 },
238 { 238 {
239 .gpio = S3C2410_GPG2, 239 .gpio = S3C2410_GPG(2),
240 .code = SW_HEADPHONE_INSERT, 240 .code = SW_HEADPHONE_INSERT,
241 .desc = "Headphone", 241 .desc = "Headphone",
242 .active_low = 0, 242 .active_low = 0,
@@ -260,7 +260,7 @@ static struct platform_device n35_button_device = {
260/* This is the bluetooth LED on the device. */ 260/* This is the bluetooth LED on the device. */
261static struct s3c24xx_led_platdata n30_blue_led_pdata = { 261static struct s3c24xx_led_platdata n30_blue_led_pdata = {
262 .name = "blue_led", 262 .name = "blue_led",
263 .gpio = S3C2410_GPG6, 263 .gpio = S3C2410_GPG(6),
264 .def_trigger = "", 264 .def_trigger = "",
265}; 265};
266 266
@@ -271,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
271static struct s3c24xx_led_platdata n30_warning_led_pdata = { 271static struct s3c24xx_led_platdata n30_warning_led_pdata = {
272 .name = "warning_led", 272 .name = "warning_led",
273 .flags = S3C24XX_LEDF_ACTLOW, 273 .flags = S3C24XX_LEDF_ACTLOW,
274 .gpio = S3C2410_GPD9, 274 .gpio = S3C2410_GPD(9),
275 .def_trigger = "", 275 .def_trigger = "",
276}; 276};
277 277
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 7520aee3c9e1..2cc9849eb448 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -199,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
199/* LED */ 199/* LED */
200 200
201static struct s3c24xx_led_platdata qt2410_pdata_led = { 201static struct s3c24xx_led_platdata qt2410_pdata_led = {
202 .gpio = S3C2410_GPB0, 202 .gpio = S3C2410_GPB(0),
203 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 203 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
204 .name = "led", 204 .name = "led",
205 .def_trigger = "timer", 205 .def_trigger = "timer",
@@ -219,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
219{ 219{
220 switch (cs) { 220 switch (cs) {
221 case BITBANG_CS_ACTIVE: 221 case BITBANG_CS_ACTIVE:
222 s3c2410_gpio_setpin(S3C2410_GPB5, 0); 222 s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
223 break; 223 break;
224 case BITBANG_CS_INACTIVE: 224 case BITBANG_CS_INACTIVE:
225 s3c2410_gpio_setpin(S3C2410_GPB5, 1); 225 s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
226 break; 226 break;
227 } 227 }
228} 228}
229 229
230static struct s3c2410_spigpio_info spi_gpio_cfg = { 230static struct s3c2410_spigpio_info spi_gpio_cfg = {
231 .pin_clk = S3C2410_GPG7, 231 .pin_clk = S3C2410_GPG(7),
232 .pin_mosi = S3C2410_GPG6, 232 .pin_mosi = S3C2410_GPG(6),
233 .pin_miso = S3C2410_GPG5, 233 .pin_miso = S3C2410_GPG(5),
234 .chip_select = &spi_gpio_cs, 234 .chip_select = &spi_gpio_cs,
235}; 235};
236 236
@@ -347,13 +347,13 @@ static void __init qt2410_machine_init(void)
347 } 347 }
348 s3c24xx_fb_set_platdata(&qt2410_fb_info); 348 s3c24xx_fb_set_platdata(&qt2410_fb_info);
349 349
350 s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); 350 s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
351 s3c2410_gpio_setpin(S3C2410_GPB0, 1); 351 s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
352 352
353 s3c24xx_udc_set_platdata(&qt2410_udc_cfg); 353 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
354 s3c_i2c0_set_platdata(NULL); 354 s3c_i2c0_set_platdata(NULL);
355 355
356 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); 356 s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
357 357
358 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); 358 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
359 s3c_pm_init(); 359 s3c_pm_init();
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 0507a7ec18ce..1628cc773a2c 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -278,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
278 278
279static struct s3c24xx_led_platdata vr1000_led1_pdata = { 279static struct s3c24xx_led_platdata vr1000_led1_pdata = {
280 .name = "led1", 280 .name = "led1",
281 .gpio = S3C2410_GPB0, 281 .gpio = S3C2410_GPB(0),
282 .def_trigger = "", 282 .def_trigger = "",
283}; 283};
284 284
285static struct s3c24xx_led_platdata vr1000_led2_pdata = { 285static struct s3c24xx_led_platdata vr1000_led2_pdata = {
286 .name = "led2", 286 .name = "led2",
287 .gpio = S3C2410_GPB1, 287 .gpio = S3C2410_GPB(1),
288 .def_trigger = "", 288 .def_trigger = "",
289}; 289};
290 290
291static struct s3c24xx_led_platdata vr1000_led3_pdata = { 291static struct s3c24xx_led_platdata vr1000_led3_pdata = {
292 .name = "led3", 292 .name = "led3",
293 .gpio = S3C2410_GPB2, 293 .gpio = S3C2410_GPB(2),
294 .def_trigger = "", 294 .def_trigger = "",
295}; 295};
296 296
@@ -356,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
356 356
357static void vr1000_power_off(void) 357static void vr1000_power_off(void)
358{ 358{
359 s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPIO_OUTPUT); 359 s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT);
360 s3c2410_gpio_setpin(S3C2410_GPB9, 1); 360 s3c2410_gpio_setpin(S3C2410_GPB(9), 1);
361} 361}
362 362
363static void __init vr1000_map_io(void) 363static void __init vr1000_map_io(void)
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 726cfc093886..143e08a599d4 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -77,7 +77,7 @@ static void s3c2410_pm_prepare(void)
77 } 77 }
78 78
79 if ( machine_is_aml_m5900() ) 79 if ( machine_is_aml_m5900() )
80 s3c2410_gpio_setpin(S3C2410_GPF2, 1); 80 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
81 81
82} 82}
83 83
@@ -92,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
92 __raw_writel(tmp, S3C2410_GSTATUS2); 92 __raw_writel(tmp, S3C2410_GSTATUS2);
93 93
94 if ( machine_is_aml_m5900() ) 94 if ( machine_is_aml_m5900() )
95 s3c2410_gpio_setpin(S3C2410_GPF2, 0); 95 s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
96 96
97 return 0; 97 return 0;
98} 98}
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 506252b33fef..dd45eb4a6f0c 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -54,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
54 power_state[port] = to; 54 power_state[port] = to;
55 55
56 if (power_state[0] && power_state[1]) 56 if (power_state[0] && power_state[1])
57 s3c2410_gpio_setpin(S3C2410_GPB4, 0); 57 s3c2410_gpio_setpin(S3C2410_GPB(4), 0);
58 else 58 else
59 s3c2410_gpio_setpin(S3C2410_GPB4, 1); 59 s3c2410_gpio_setpin(S3C2410_GPB(4), 1);
60} 60}
61 61
62static irqreturn_t 62static irqreturn_t
@@ -64,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
64{ 64{
65 struct s3c2410_hcd_info *info = pw; 65 struct s3c2410_hcd_info *info = pw;
66 66
67 if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) { 67 if (s3c2410_gpio_getpin(S3C2410_GPG(10)) == 0) {
68 pr_debug("usb_simtec: over-current irq (oc detected)\n"); 68 pr_debug("usb_simtec: over-current irq (oc detected)\n");
69 s3c2410_usb_report_oc(info, 3); 69 s3c2410_usb_report_oc(info, 3);
70 } else { 70 } else {
@@ -110,7 +110,7 @@ int usb_simtec_init(void)
110 printk("USB Power Control, (c) 2004 Simtec Electronics\n"); 110 printk("USB Power Control, (c) 2004 Simtec Electronics\n");
111 s3c_device_usb.dev.platform_data = &usb_simtec_info; 111 s3c_device_usb.dev.platform_data = &usb_simtec_info;
112 112
113 s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPIO_OUTPUT); 113 s3c2410_gpio_cfgpin(S3C2410_GPB(4), S3C2410_GPIO_OUTPUT);
114 s3c2410_gpio_setpin(S3C2410_GPB4, 1); 114 s3c2410_gpio_setpin(S3C2410_GPB(4), 1);
115 return 0; 115 return 0;
116} 116}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 17:38:34 -0500