diff options
author | James Bottomley <jejb@titanic.(none)> | 2005-11-10 09:29:07 -0500 |
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committer | James Bottomley <jejb@titanic.(none)> | 2005-11-10 09:29:07 -0500 |
commit | 8a87a0b6313109d2fea87b1271d497c954ce2ca8 (patch) | |
tree | 1b7ae51ff681e27118590e9cab4bf0ce38f5d80e /arch/arm/mach-s3c2410/mach-anubis.c | |
parent | e6a04466ba965875a6132700fabb2f2c0249c41a (diff) | |
parent | 3b44f137b9a846c5452d9e6e1271b79b1dbcc942 (diff) |
Merge by hand (whitespace conflicts in libata.h)
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'arch/arm/mach-s3c2410/mach-anubis.c')
-rw-r--r-- | arch/arm/mach-s3c2410/mach-anubis.c | 51 |
1 files changed, 42 insertions, 9 deletions
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c index 8390b685c2b6..0f81fc0c2f7f 100644 --- a/arch/arm/mach-s3c2410/mach-anubis.c +++ b/arch/arm/mach-s3c2410/mach-anubis.c | |||
@@ -56,8 +56,16 @@ | |||
56 | static struct map_desc anubis_iodesc[] __initdata = { | 56 | static struct map_desc anubis_iodesc[] __initdata = { |
57 | /* ISA IO areas */ | 57 | /* ISA IO areas */ |
58 | 58 | ||
59 | { (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE }, | 59 | { |
60 | { (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE }, | 60 | .virtual = (u32)S3C24XX_VA_ISA_BYTE, |
61 | .pfn = __phys_to_pfn(0x0), | ||
62 | .length = SZ_4M, | ||
63 | .type = MT_DEVICE | ||
64 | }, { | ||
65 | .virtual = (u32)S3C24XX_VA_ISA_WORD, | ||
66 | .pfn = __phys_to_pfn(0x0), | ||
67 | .length = SZ_4M, MT_DEVICE | ||
68 | }, | ||
61 | 69 | ||
62 | /* we could possibly compress the next set down into a set of smaller tables | 70 | /* we could possibly compress the next set down into a set of smaller tables |
63 | * pagetables, but that would mean using an L2 section, and it still means | 71 | * pagetables, but that would mean using an L2 section, and it still means |
@@ -66,16 +74,41 @@ static struct map_desc anubis_iodesc[] __initdata = { | |||
66 | 74 | ||
67 | /* CPLD control registers */ | 75 | /* CPLD control registers */ |
68 | 76 | ||
69 | { (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE }, | 77 | { |
70 | { (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE }, | 78 | .virtual = (u32)ANUBIS_VA_CTRL1, |
79 | .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1), | ||
80 | .length = SZ_4K, | ||
81 | .type = MT_DEVICE | ||
82 | }, { | ||
83 | .virtual = (u32)ANUBIS_VA_CTRL2, | ||
84 | .pfn = __phys_to_pfn(ANUBIS_PA_CTRL2), | ||
85 | .length = SZ_4K, | ||
86 | .type =MT_DEVICE | ||
87 | }, | ||
71 | 88 | ||
72 | /* IDE drives */ | 89 | /* IDE drives */ |
73 | 90 | ||
74 | { (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE }, | 91 | { |
75 | { (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE }, | 92 | .virtual = (u32)ANUBIS_IDEPRI, |
76 | 93 | .pfn = __phys_to_pfn(S3C2410_CS3), | |
77 | { (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE }, | 94 | .length = SZ_1M, |
78 | { (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE }, | 95 | .type = MT_DEVICE |
96 | }, { | ||
97 | .virtual = (u32)ANUBIS_IDEPRIAUX, | ||
98 | .pfn = __phys_to_pfn(S3C2410_CS3+(1<<26)), | ||
99 | .length = SZ_1M, | ||
100 | .type = MT_DEVICE | ||
101 | }, { | ||
102 | .virtual = (u32)ANUBIS_IDESEC, | ||
103 | .pfn = __phys_to_pfn(S3C2410_CS4), | ||
104 | .length = SZ_1M, | ||
105 | .type = MT_DEVICE | ||
106 | }, { | ||
107 | .virtual = (u32)ANUBIS_IDESECAUX, | ||
108 | .pfn = __phys_to_pfn(S3C2410_CS4+(1<<26)), | ||
109 | .length = SZ_1M, | ||
110 | .type = MT_DEVICE | ||
111 | }, | ||
79 | }; | 112 | }; |
80 | 113 | ||
81 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | 114 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK |