diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-05-17 01:53:48 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-18 06:06:34 -0400 |
commit | 1635ca4aaf835794401da33079e50ce1d6bbb5d0 (patch) | |
tree | e8b6284f10729f9d827d77ad853c83ea1796f118 /arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |
parent | 7987bd7a7051c979f7b9b572898f92dbef6aaeb1 (diff) |
ARM: S3C24XX: Remove macros mapping GPIO number to base
As part of the cleanup, remove the old macros mapping GPIO numbers
to the base of the register now we have gpiolib to manage the GPIO
mappings for us.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s3c2410/include/mach/regs-gpio.h')
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 821b966bf05a..95e29fefec34 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -17,29 +17,11 @@ | |||
17 | #include <mach/gpio-nrs.h> | 17 | #include <mach/gpio-nrs.h> |
18 | 18 | ||
19 | #ifdef CONFIG_CPU_S3C2400 | 19 | #ifdef CONFIG_CPU_S3C2400 |
20 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | 20 | #define S3C24XX_MISCCR S3C2400_MISCCR |
21 | #define S3C24XX_MISCCR S3C2400_MISCCR | ||
22 | #else | 21 | #else |
23 | #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) | 22 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) |
24 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) | ||
25 | #endif /* CONFIG_CPU_S3C2400 */ | 23 | #endif /* CONFIG_CPU_S3C2400 */ |
26 | 24 | ||
27 | |||
28 | /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ | ||
29 | |||
30 | #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) | ||
31 | #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) | ||
32 | #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ | ||
33 | (2 * (S3C2400_BANKNUM(pin)-2))) | ||
34 | |||
35 | #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ | ||
36 | S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ | ||
37 | S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) | ||
38 | |||
39 | |||
40 | #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) | ||
41 | #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) | ||
42 | |||
43 | /* general configuration options */ | 25 | /* general configuration options */ |
44 | 26 | ||
45 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) | 27 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) |