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authorHaojian Zhuang <haojian.zhuang@gmail.com>2012-08-20 01:38:15 -0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2012-08-20 01:51:45 -0400
commitd8bbb55266f48e4c227ade192244a692710b9aae (patch)
treec6ca97b33d5f014cf8f42048d0cbc1ea51f469e3 /arch/arm/mach-pxa
parent51931b37fcb17a2f48f726fd21b88e3af770ddc2 (diff)
ARM: pxa: append the definition of CKENC
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 207ecb49a61b..f4d48d20754e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,7 @@
131#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ 131#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
132#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ 132#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
133#define CKENB __REG(0x41340010) /* B Clock Enable Register */ 133#define CKENB __REG(0x41340010) /* B Clock Enable Register */
134#define CKENC __REG(0x41340024) /* C Clock Enable Register */
134#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ 135#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
135 136
136#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */ 137#define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */