Merge branch 'next/dt' into HEAD

Conflicts:
	Documentation/devicetree/bindings/usb/platform-uhci.txt
	arch/arm/mach-vt8500/bv07.c
	arch/arm/mach-vt8500/devices-vt8500.c
	arch/arm/mach-vt8500/devices-wm8505.c
	arch/arm/mach-vt8500/devices.c
	arch/arm/mach-vt8500/devices.h
	arch/arm/mach-vt8500/wm8505_7in.c

7 files changed, 215 insertions, 26 deletions

diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f80ef50..8e6288de69b9 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO
 if !ARCH_PXA_V7
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
 
+config MACH_PXA3XX_DT
+        bool "Support PXA3xx platforms from device tree"
+        select PXA3xx
+        select CPU_PXA300
+        select POWER_SUPPLY
+        select HAVE_PWM
+        select USE_OF
+        help
+          Include support for Marvell PXA3xx based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_PXA3XX_DT is enabled.
+
 config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform (aka Lubbock)"
         select PXA25x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df8685c..2bedc9ed076c 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 
 # NOTE: keep the order of boards in accordance to their order in Kconfig
 
+# Device Tree support
+obj-$(CONFIG_MACH_PXA3XX_DT)    += pxa-dt.o
+
 # Intel/Marvell Dev Platforms
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 2a37a9a8f621..d4e9499832dc 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk)
 
         if (clk->cken < 32)
                 CKENA |= mask;
-        else
+        else if (clk->cken < 64)
                 CKENB |= mask;
+        else
+                CKENC |= mask;
 }
 
 void clk_pxa3xx_cken_disable(struct clk *clk)
@@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk)
 
         if (clk->cken < 32)
                 CKENA &= ~mask;
-        else
+        else if (clk->cken < 64)
                 CKENB &= ~mask;
+        else
+                CKENC &= ~mask;
 }
 
 const struct clkops clk_pxa3xx_cken_ops = {
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 207ecb49a61b..f4d48d20754e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,7 @@
 #define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
 #define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
 #define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
+#define CKENC           __REG(0x41340024)       /* C Clock Enable Register */
 #define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
 
 #define ACCR_XPDIS              (1 << 31)       /* Core PLL Output Disable */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 5dae15ea6718..b6cc1816463e 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,6 +17,8 @@
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/exception.h>
 
@@ -25,8 +27,6 @@
 
 #include "generic.h"
 
-#define IRQ_BASE                io_p2v(0x40d00000)
-
 #define ICIP                    (0x000)
 #define ICMR                    (0x004)
 #define ICLR                    (0x008)
@@ -48,22 +48,19 @@
  * This is for peripheral IRQs internal to the PXA chip.
  */
 
+static void __iomem *pxa_irq_base;
 static int pxa_internal_irq_nr;
-
-static inline int cpu_has_ipr(void)
-{
-        return !cpu_is_pxa25x();
-}
+static bool cpu_has_ipr;
 
 static inline void __iomem *irq_base(int i)
 {
-        static unsigned long phys_base[] = {
-                0x40d00000,
-                0x40d0009c,
-                0x40d00130,
+        static unsigned long phys_base_offset[] = {
+                0x0,
+                0x9c,
+                0x130,
         };
 
-        return io_p2v(phys_base[i]);
+        return pxa_irq_base + phys_base_offset[i];
 }
 
 void pxa_mask_irq(struct irq_data *d)
@@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
         uint32_t icip, icmr, mask;
 
         do {
-                icip = __raw_readl(IRQ_BASE + ICIP);
-                icmr = __raw_readl(IRQ_BASE + ICMR);
+                icip = __raw_readl(pxa_irq_base + ICIP);
+                icmr = __raw_readl(pxa_irq_base + ICMR);
                 mask = icip & icmr;
 
                 if (mask == 0)
@@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 
         pxa_internal_irq_nr = irq_nr;
+        cpu_has_ipr = !cpu_is_pxa25x();
+        pxa_irq_base = io_p2v(0x40d00000);
 
         for (n = 0; n < irq_nr; n += 32) {
                 void __iomem *base = irq_base(n >> 5);
@@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
                 __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
                 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
                         /* initialize interrupt priority */
-                        if (cpu_has_ipr())
-                                __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+                        if (cpu_has_ipr)
+                                __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
 
                         irq = PXA_IRQ(i);
                         irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
@@ -168,9 +167,9 @@ static int pxa_irq_suspend(void)
                 __raw_writel(0, base + ICMR);
         }
 
-        if (cpu_has_ipr()) {
+        if (cpu_has_ipr) {
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
+                        saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
         }
 
         return 0;
@@ -187,11 +186,11 @@ static void pxa_irq_resume(void)
                 __raw_writel(0, base + ICLR);
         }
 
-        if (cpu_has_ipr())
+        if (cpu_has_ipr)
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+                        __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
 
-        __raw_writel(1, IRQ_BASE + ICCR);
+        __raw_writel(1, pxa_irq_base + ICCR);
 }
 #else
 #define pxa_irq_suspend         NULL
@@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = {
         .suspend        = pxa_irq_suspend,
         .resume         = pxa_irq_resume,
 };
+
+#ifdef CONFIG_OF
+static struct irq_domain *pxa_irq_domain;
+
+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
+                       irq_hw_number_t hw)
+{
+        void __iomem *base = irq_base(hw / 32);
+
+        /* initialize interrupt priority */
+        if (cpu_has_ipr)
+                __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
+
+        irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
+                                 handle_level_irq);
+        irq_set_chip_data(hw, base);
+        set_irq_flags(hw, IRQF_VALID);
+
+        return 0;
+}
+
+static struct irq_domain_ops pxa_irq_ops = {
+        .map    = pxa_irq_map,
+        .xlate  = irq_domain_xlate_onecell,
+};
+
+static const struct of_device_id intc_ids[] __initconst = {
+        { .compatible = "marvell,pxa-intc", },
+        {}
+};
+
+void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct pxa_intc_conf *conf;
+        struct resource res;
+        int n, ret;
+
+        node = of_find_matching_node(NULL, intc_ids);
+        if (!node) {
+                pr_err("Failed to find interrupt controller in arch-pxa\n");
+                return;
+        }
+        of_id = of_match_node(intc_ids, node);
+        conf = of_id->data;
+
+        ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
+                                   &pxa_internal_irq_nr);
+        if (ret) {
+                pr_err("Not found marvell,intc-nr-irqs property\n");
+                return;
+        }
+
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret < 0) {
+                pr_err("No registers defined for node\n");
+                return;
+        }
+        pxa_irq_base = io_p2v(res.start);
+
+        if (of_find_property(node, "marvell,intc-priority", NULL))
+                cpu_has_ipr = 1;
+
+        ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
+        if (ret < 0) {
+                pr_err("Failed to allocate IRQ numbers\n");
+                return;
+        }
+
+        pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
+                                               &pxa_irq_ops, NULL);
+        if (!pxa_irq_domain)
+                panic("Unable to add PXA IRQ domain\n");
+
+        irq_set_default_host(pxa_irq_domain);
+
+        for (n = 0; n < pxa_internal_irq_nr; n += 32) {
+                void __iomem *base = irq_base(n >> 5);
+
+                __raw_writel(0, base + ICMR);   /* disable all IRQs */
+                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
+        }
+
+        /* only unmasked interrupts kick us out of idle */
+        __raw_writel(1, irq_base(0) + ICCR);
+
+        pxa_internal_irq_chip.irq_set_wake = fn;
+}
+#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
new file mode 100644
index 000000000000..c9192cea0033
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -0,0 +1,63 @@
+/*
+ *  linux/arch/arm/mach-pxa/pxa-dt.c
+ *
+ *  Copyright (C) 2012 Daniel Mack
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/pxa3xx.h>
+
+#include "generic.h"
+
+#ifdef CONFIG_PXA3xx
+extern void __init pxa3xx_dt_init_irq(void);
+
+static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40100000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40200000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40700000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x41600000, "pxa2xx-uart.3", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-mmc",       0x41100000, "pxa2xx-mci.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-gpio",         0x40e00000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-ohci",      0x4c000000, "pxa27x-ohci", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-i2c",          0x40301680, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pwri2c",           0x40f500c0, "pxa3xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("marvell,pxa3xx-nand",   0x43100000, "pxa3xx-nand", NULL),
+        {}
+};
+
+static void __init pxa3xx_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             pxa3xx_auxdata_lookup, NULL);
+}
+
+static const char *pxa3xx_dt_board_compat[] __initdata = {
+        "marvell,pxa300",
+        "marvell,pxa310",
+        "marvell,pxa320",
+        NULL,
+};
+#endif
+
+#ifdef CONFIG_PXA3xx
+DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
+        .map_io         = pxa3xx_map_io,
+        .init_irq       = pxa3xx_dt_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
+        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
+        .init_machine   = pxa3xx_dt_init,
+        .dt_compat      = pxa3xx_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index dffb7e813d98..ff9c9574ec3e 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/syscore_ops.h>
 #include <linux/i2c/pxa-i2c.h>
 
@@ -40,6 +41,8 @@
 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
 
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
+
 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
         pxa_ext_wakeup_chip.irq_set_wake = fn;
 }
 
-void __init pxa3xx_init_irq(void)
+static void __init __pxa3xx_init_irq(void)
 {
         /* enable CP6 access */
         u32 value;
@@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void)
         value |= (1 << 6);
         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
-        pxa_init_irq(56, pxa3xx_set_wake);
         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 }
 
+void __init pxa3xx_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_init_irq(56, pxa3xx_set_wake);
+}
+
+#ifdef CONFIG_OF
+void __init pxa3xx_dt_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_dt_irq_init(pxa3xx_set_wake);
+}
+#endif  /* CONFIG_OF */
+
 static struct map_desc pxa3xx_io_desc[] __initdata = {
         {       /* Mem Ctl */
                 .virtual        = (unsigned long)SMEMC_VIRT,
@@ -466,7 +482,8 @@ static int __init pxa3xx_init(void)
                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 
-                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (!of_have_populated_dt())
+                        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
         return ret;