aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-pxa
diff options
context:
space:
mode:
authorDmitry Torokhov <dmitry.torokhov@gmail.com>2013-06-28 02:00:25 -0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2013-06-28 02:00:25 -0400
commit31881d74b6dd1a6c530cff61248def4f2da38bee (patch)
treebe62420cf39192074e13b25553d172b9d5e58a33 /arch/arm/mach-pxa
parent8855f30cd2b68012571932c7b01290c20be4508c (diff)
parent257867dc8d893690c175c1f717f91c3b6d44a63d (diff)
Merge branch 'for-next' of git://github.com/rydberg/linux into next
Pull in changes from Henrik: "a trivial MT documentation fix".
Diffstat (limited to 'arch/arm/mach-pxa')
-rw-r--r--arch/arm/mach-pxa/Kconfig3
-rw-r--r--arch/arm/mach-pxa/Makefile6
-rw-r--r--arch/arm/mach-pxa/cpufreq-pxa2xx.c494
-rw-r--r--arch/arm/mach-pxa/cpufreq-pxa3xx.c258
-rw-r--r--arch/arm/mach-pxa/devices.c29
-rw-r--r--arch/arm/mach-pxa/devices.h6
-rw-r--r--arch/arm/mach-pxa/include/mach/debug-macro.S23
-rw-r--r--arch/arm/mach-pxa/include/mach/generic.h1
-rw-r--r--arch/arm/mach-pxa/pxa25x.c11
-rw-r--r--arch/arm/mach-pxa/pxa27x.c7
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c23
-rw-r--r--arch/arm/mach-pxa/pxa930.c17
12 files changed, 81 insertions, 797 deletions
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 86eec4159cbc..96100dbf5a2e 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -51,11 +51,13 @@ config MACH_LITTLETON
51config MACH_TAVOREVB 51config MACH_TAVOREVB
52 bool "PXA930 Evaluation Board (aka TavorEVB)" 52 bool "PXA930 Evaluation Board (aka TavorEVB)"
53 select CPU_PXA930 53 select CPU_PXA930
54 select CPU_PXA935
54 select PXA3xx 55 select PXA3xx
55 56
56config MACH_SAAR 57config MACH_SAAR
57 bool "PXA930 Handheld Platform (aka SAAR)" 58 bool "PXA930 Handheld Platform (aka SAAR)"
58 select CPU_PXA930 59 select CPU_PXA930
60 select CPU_PXA935
59 select PXA3xx 61 select PXA3xx
60 62
61comment "Third Party Dev Platforms (sorted by vendor name)" 63comment "Third Party Dev Platforms (sorted by vendor name)"
@@ -160,7 +162,6 @@ config MACH_XCEP
160 select MTD 162 select MTD
161 select MTD_CFI 163 select MTD_CFI
162 select MTD_CFI_INTELEXT 164 select MTD_CFI_INTELEXT
163 select MTD_CHAR
164 select MTD_PHYSMAP 165 select MTD_PHYSMAP
165 select PXA25x 166 select PXA25x
166 select SMC91X 167 select SMC91X
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 12c500558387..648867a8caa8 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -7,12 +7,6 @@ obj-y += clock.o devices.o generic.o irq.o \
7 time.o reset.o 7 time.o reset.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o 8obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9 9
10ifeq ($(CONFIG_CPU_FREQ),y)
11obj-$(CONFIG_PXA25x) += cpufreq-pxa2xx.o
12obj-$(CONFIG_PXA27x) += cpufreq-pxa2xx.o
13obj-$(CONFIG_PXA3xx) += cpufreq-pxa3xx.o
14endif
15
16# Generic drivers that other drivers may depend upon 10# Generic drivers that other drivers may depend upon
17 11
18# SoC-specific code 12# SoC-specific code
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
deleted file mode 100644
index 6a7aeab42f6c..000000000000
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ /dev/null
@@ -1,494 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
3 *
4 * Copyright (C) 2002,2003 Intrinsyc Software
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * History:
21 * 31-Jul-2002 : Initial version [FB]
22 * 29-Jan-2003 : added PXA255 support [FB]
23 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
24 *
25 * Note:
26 * This driver may change the memory bus clock rate, but will not do any
27 * platform specific access timing changes... for example if you have flash
28 * memory connected to CS0, you will need to register a platform specific
29 * notifier which will adjust the memory access strobes to maintain a
30 * minimum strobe width.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/sched.h>
37#include <linux/init.h>
38#include <linux/cpufreq.h>
39#include <linux/err.h>
40#include <linux/regulator/consumer.h>
41#include <linux/io.h>
42
43#include <mach/pxa2xx-regs.h>
44#include <mach/smemc.h>
45
46#ifdef DEBUG
47static unsigned int freq_debug;
48module_param(freq_debug, uint, 0);
49MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
50#else
51#define freq_debug 0
52#endif
53
54static struct regulator *vcc_core;
55
56static unsigned int pxa27x_maxfreq;
57module_param(pxa27x_maxfreq, uint, 0);
58MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
59 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
60
61typedef struct {
62 unsigned int khz;
63 unsigned int membus;
64 unsigned int cccr;
65 unsigned int div2;
66 unsigned int cclkcfg;
67 int vmin;
68 int vmax;
69} pxa_freqs_t;
70
71/* Define the refresh period in mSec for the SDRAM and the number of rows */
72#define SDRAM_TREF 64 /* standard 64ms SDRAM */
73static unsigned int sdram_rows;
74
75#define CCLKCFG_TURBO 0x1
76#define CCLKCFG_FCS 0x2
77#define CCLKCFG_HALFTURBO 0x4
78#define CCLKCFG_FASTBUS 0x8
79#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
80#define MDREFR_DRI_MASK 0xFFF
81
82#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
83#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
84
85/*
86 * PXA255 definitions
87 */
88/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
89#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
90
91static pxa_freqs_t pxa255_run_freqs[] =
92{
93 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
94 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
95 {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
96 {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
97 {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
98 {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
99 {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
100};
101
102/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
103static pxa_freqs_t pxa255_turbo_freqs[] =
104{
105 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
106 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
107 {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
108 {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
109 {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
110 {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
111};
112
113#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
114#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
115
116static struct cpufreq_frequency_table
117 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
118static struct cpufreq_frequency_table
119 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
120
121static unsigned int pxa255_turbo_table;
122module_param(pxa255_turbo_table, uint, 0);
123MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
124
125/*
126 * PXA270 definitions
127 *
128 * For the PXA27x:
129 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
130 *
131 * A = 0 => memory controller clock from table 3-7,
132 * A = 1 => memory controller clock = system bus clock
133 * Run mode frequency = 13 MHz * L
134 * Turbo mode frequency = 13 MHz * L * N
135 * System bus frequency = 13 MHz * L / (B + 1)
136 *
137 * In CCCR:
138 * A = 1
139 * L = 16 oscillator to run mode ratio
140 * 2N = 6 2 * (turbo mode to run mode ratio)
141 *
142 * In CCLKCFG:
143 * B = 1 Fast bus mode
144 * HT = 0 Half-Turbo mode
145 * T = 1 Turbo mode
146 *
147 * For now, just support some of the combinations in table 3-7 of
148 * PXA27x Processor Family Developer's Manual to simplify frequency
149 * change sequences.
150 */
151#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
152#define CCLKCFG2(B, HT, T) \
153 (CCLKCFG_FCS | \
154 ((B) ? CCLKCFG_FASTBUS : 0) | \
155 ((HT) ? CCLKCFG_HALFTURBO : 0) | \
156 ((T) ? CCLKCFG_TURBO : 0))
157
158static pxa_freqs_t pxa27x_freqs[] = {
159 {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
160 {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
161 {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
162 {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
163 {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
164 {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
165 {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
166};
167
168#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
169static struct cpufreq_frequency_table
170 pxa27x_freq_table[NUM_PXA27x_FREQS+1];
171
172extern unsigned get_clk_frequency_khz(int info);
173
174#ifdef CONFIG_REGULATOR
175
176static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
177{
178 int ret = 0;
179 int vmin, vmax;
180
181 if (!cpu_is_pxa27x())
182 return 0;
183
184 vmin = pxa_freq->vmin;
185 vmax = pxa_freq->vmax;
186 if ((vmin == -1) || (vmax == -1))
187 return 0;
188
189 ret = regulator_set_voltage(vcc_core, vmin, vmax);
190 if (ret)
191 pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
192 vmin, vmax);
193 return ret;
194}
195
196static __init void pxa_cpufreq_init_voltages(void)
197{
198 vcc_core = regulator_get(NULL, "vcc_core");
199 if (IS_ERR(vcc_core)) {
200 pr_info("cpufreq: Didn't find vcc_core regulator\n");
201 vcc_core = NULL;
202 } else {
203 pr_info("cpufreq: Found vcc_core regulator\n");
204 }
205}
206#else
207static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
208{
209 return 0;
210}
211
212static __init void pxa_cpufreq_init_voltages(void) { }
213#endif
214
215static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
216 pxa_freqs_t **pxa_freqs)
217{
218 if (cpu_is_pxa25x()) {
219 if (!pxa255_turbo_table) {
220 *pxa_freqs = pxa255_run_freqs;
221 *freq_table = pxa255_run_freq_table;
222 } else {
223 *pxa_freqs = pxa255_turbo_freqs;
224 *freq_table = pxa255_turbo_freq_table;
225 }
226 }
227 if (cpu_is_pxa27x()) {
228 *pxa_freqs = pxa27x_freqs;
229 *freq_table = pxa27x_freq_table;
230 }
231}
232
233static void pxa27x_guess_max_freq(void)
234{
235 if (!pxa27x_maxfreq) {
236 pxa27x_maxfreq = 416000;
237 printk(KERN_INFO "PXA CPU 27x max frequency not defined "
238 "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
239 pxa27x_maxfreq);
240 } else {
241 pxa27x_maxfreq *= 1000;
242 }
243}
244
245static void init_sdram_rows(void)
246{
247 uint32_t mdcnfg = __raw_readl(MDCNFG);
248 unsigned int drac2 = 0, drac0 = 0;
249
250 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
251 drac2 = MDCNFG_DRAC2(mdcnfg);
252
253 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
254 drac0 = MDCNFG_DRAC0(mdcnfg);
255
256 sdram_rows = 1 << (11 + max(drac0, drac2));
257}
258
259static u32 mdrefr_dri(unsigned int freq)
260{
261 u32 interval = freq * SDRAM_TREF / sdram_rows;
262
263 return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
264}
265
266/* find a valid frequency point */
267static int pxa_verify_policy(struct cpufreq_policy *policy)
268{
269 struct cpufreq_frequency_table *pxa_freqs_table;
270 pxa_freqs_t *pxa_freqs;
271 int ret;
272
273 find_freq_tables(&pxa_freqs_table, &pxa_freqs);
274 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
275
276 if (freq_debug)
277 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
278 policy->min, policy->max);
279
280 return ret;
281}
282
283static unsigned int pxa_cpufreq_get(unsigned int cpu)
284{
285 return get_clk_frequency_khz(0);
286}
287
288static int pxa_set_target(struct cpufreq_policy *policy,
289 unsigned int target_freq,
290 unsigned int relation)
291{
292 struct cpufreq_frequency_table *pxa_freqs_table;
293 pxa_freqs_t *pxa_freq_settings;
294 struct cpufreq_freqs freqs;
295 unsigned int idx;
296 unsigned long flags;
297 unsigned int new_freq_cpu, new_freq_mem;
298 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
299 int ret = 0;
300
301 /* Get the current policy */
302 find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
303
304 /* Lookup the next frequency */
305 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
306 target_freq, relation, &idx)) {
307 return -EINVAL;
308 }
309
310 new_freq_cpu = pxa_freq_settings[idx].khz;
311 new_freq_mem = pxa_freq_settings[idx].membus;
312 freqs.old = policy->cur;
313 freqs.new = new_freq_cpu;
314 freqs.cpu = policy->cpu;
315
316 if (freq_debug)
317 pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
318 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
319 (new_freq_mem / 2000) : (new_freq_mem / 1000));
320
321 if (vcc_core && freqs.new > freqs.old)
322 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
323 if (ret)
324 return ret;
325 /*
326 * Tell everyone what we're about to do...
327 * you should add a notify client with any platform specific
328 * Vcc changing capability
329 */
330 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
331
332 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
333 * we need to preset the smaller DRI before the change. If we're
334 * speeding up we need to set the larger DRI value after the change.
335 */
336 preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
337 if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
338 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
339 preset_mdrefr |= mdrefr_dri(new_freq_mem);
340 }
341 postset_mdrefr =
342 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
343
344 /* If we're dividing the memory clock by two for the SDRAM clock, this
345 * must be set prior to the change. Clearing the divide must be done
346 * after the change.
347 */
348 if (pxa_freq_settings[idx].div2) {
349 preset_mdrefr |= MDREFR_DB2_MASK;
350 postset_mdrefr |= MDREFR_DB2_MASK;
351 } else {
352 postset_mdrefr &= ~MDREFR_DB2_MASK;
353 }
354
355 local_irq_save(flags);
356
357 /* Set new the CCCR and prepare CCLKCFG */
358 CCCR = pxa_freq_settings[idx].cccr;
359 cclkcfg = pxa_freq_settings[idx].cclkcfg;
360
361 asm volatile(" \n\
362 ldr r4, [%1] /* load MDREFR */ \n\
363 b 2f \n\
364 .align 5 \n\
3651: \n\
366 str %3, [%1] /* preset the MDREFR */ \n\
367 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
368 str %4, [%1] /* postset the MDREFR */ \n\
369 \n\
370 b 3f \n\
3712: b 1b \n\
3723: nop \n\
373 "
374 : "=&r" (unused)
375 : "r" (MDREFR), "r" (cclkcfg),
376 "r" (preset_mdrefr), "r" (postset_mdrefr)
377 : "r4", "r5");
378 local_irq_restore(flags);
379
380 /*
381 * Tell everyone what we've just done...
382 * you should add a notify client with any platform specific
383 * SDRAM refresh timer adjustments
384 */
385 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
386
387 /*
388 * Even if voltage setting fails, we don't report it, as the frequency
389 * change succeeded. The voltage reduction is not a critical failure,
390 * only power savings will suffer from this.
391 *
392 * Note: if the voltage change fails, and a return value is returned, a
393 * bug is triggered (seems a deadlock). Should anybody find out where,
394 * the "return 0" should become a "return ret".
395 */
396 if (vcc_core && freqs.new < freqs.old)
397 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
398
399 return 0;
400}
401
402static int pxa_cpufreq_init(struct cpufreq_policy *policy)
403{
404 int i;
405 unsigned int freq;
406 struct cpufreq_frequency_table *pxa255_freq_table;
407 pxa_freqs_t *pxa255_freqs;
408
409 /* try to guess pxa27x cpu */
410 if (cpu_is_pxa27x())
411 pxa27x_guess_max_freq();
412
413 pxa_cpufreq_init_voltages();
414
415 init_sdram_rows();
416
417 /* set default policy and cpuinfo */
418 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
419 policy->cur = get_clk_frequency_khz(0); /* current freq */
420 policy->min = policy->max = policy->cur;
421
422 /* Generate pxa25x the run cpufreq_frequency_table struct */
423 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
424 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
425 pxa255_run_freq_table[i].index = i;
426 }
427 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
428
429 /* Generate pxa25x the turbo cpufreq_frequency_table struct */
430 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
431 pxa255_turbo_freq_table[i].frequency =
432 pxa255_turbo_freqs[i].khz;
433 pxa255_turbo_freq_table[i].index = i;
434 }
435 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
436
437 pxa255_turbo_table = !!pxa255_turbo_table;
438
439 /* Generate the pxa27x cpufreq_frequency_table struct */
440 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
441 freq = pxa27x_freqs[i].khz;
442 if (freq > pxa27x_maxfreq)
443 break;
444 pxa27x_freq_table[i].frequency = freq;
445 pxa27x_freq_table[i].index = i;
446 }
447 pxa27x_freq_table[i].index = i;
448 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
449
450 /*
451 * Set the policy's minimum and maximum frequencies from the tables
452 * just constructed. This sets cpuinfo.mxx_freq, min and max.
453 */
454 if (cpu_is_pxa25x()) {
455 find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
456 pr_info("PXA255 cpufreq using %s frequency table\n",
457 pxa255_turbo_table ? "turbo" : "run");
458 cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
459 }
460 else if (cpu_is_pxa27x())
461 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
462
463 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
464
465 return 0;
466}
467
468static struct cpufreq_driver pxa_cpufreq_driver = {
469 .verify = pxa_verify_policy,
470 .target = pxa_set_target,
471 .init = pxa_cpufreq_init,
472 .get = pxa_cpufreq_get,
473 .name = "PXA2xx",
474};
475
476static int __init pxa_cpu_init(void)
477{
478 int ret = -ENODEV;
479 if (cpu_is_pxa25x() || cpu_is_pxa27x())
480 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
481 return ret;
482}
483
484static void __exit pxa_cpu_exit(void)
485{
486 cpufreq_unregister_driver(&pxa_cpufreq_driver);
487}
488
489
490MODULE_AUTHOR("Intrinsyc Software Inc.");
491MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
492MODULE_LICENSE("GPL");
493module_init(pxa_cpu_init);
494module_exit(pxa_cpu_exit);
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
deleted file mode 100644
index b85b4ab7aac6..000000000000
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ /dev/null
@@ -1,258 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/cpufreq-pxa3xx.c
3 *
4 * Copyright (C) 2008 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/sched.h>
15#include <linux/init.h>
16#include <linux/cpufreq.h>
17#include <linux/slab.h>
18#include <linux/io.h>
19
20#include <mach/pxa3xx-regs.h>
21
22#include "generic.h"
23
24#define HSS_104M (0)
25#define HSS_156M (1)
26#define HSS_208M (2)
27#define HSS_312M (3)
28
29#define SMCFS_78M (0)
30#define SMCFS_104M (2)
31#define SMCFS_208M (5)
32
33#define SFLFS_104M (0)
34#define SFLFS_156M (1)
35#define SFLFS_208M (2)
36#define SFLFS_312M (3)
37
38#define XSPCLK_156M (0)
39#define XSPCLK_NONE (3)
40
41#define DMCFS_26M (0)
42#define DMCFS_260M (3)
43
44struct pxa3xx_freq_info {
45 unsigned int cpufreq_mhz;
46 unsigned int core_xl : 5;
47 unsigned int core_xn : 3;
48 unsigned int hss : 2;
49 unsigned int dmcfs : 2;
50 unsigned int smcfs : 3;
51 unsigned int sflfs : 2;
52 unsigned int df_clkdiv : 3;
53
54 int vcc_core; /* in mV */
55 int vcc_sram; /* in mV */
56};
57
58#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
59{ \
60 .cpufreq_mhz = cpufreq, \
61 .core_xl = _xl, \
62 .core_xn = _xn, \
63 .hss = HSS_##_hss##M, \
64 .dmcfs = DMCFS_##_dmc##M, \
65 .smcfs = SMCFS_##_smc##M, \
66 .sflfs = SFLFS_##_sfl##M, \
67 .df_clkdiv = _dfi, \
68 .vcc_core = vcore, \
69 .vcc_sram = vsram, \
70}
71
72static struct pxa3xx_freq_info pxa300_freqs[] = {
73 /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
74 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
75 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
76 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
77 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
78};
79
80static struct pxa3xx_freq_info pxa320_freqs[] = {
81 /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
82 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
83 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
84 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
85 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
86 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
87};
88
89static unsigned int pxa3xx_freqs_num;
90static struct pxa3xx_freq_info *pxa3xx_freqs;
91static struct cpufreq_frequency_table *pxa3xx_freqs_table;
92
93static int setup_freqs_table(struct cpufreq_policy *policy,
94 struct pxa3xx_freq_info *freqs, int num)
95{
96 struct cpufreq_frequency_table *table;
97 int i;
98
99 table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
100 if (table == NULL)
101 return -ENOMEM;
102
103 for (i = 0; i < num; i++) {
104 table[i].index = i;
105 table[i].frequency = freqs[i].cpufreq_mhz * 1000;
106 }
107 table[num].index = i;
108 table[num].frequency = CPUFREQ_TABLE_END;
109
110 pxa3xx_freqs = freqs;
111 pxa3xx_freqs_num = num;
112 pxa3xx_freqs_table = table;
113
114 return cpufreq_frequency_table_cpuinfo(policy, table);
115}
116
117static void __update_core_freq(struct pxa3xx_freq_info *info)
118{
119 uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
120 uint32_t accr = ACCR;
121 uint32_t xclkcfg;
122
123 accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
124 accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
125
126 /* No clock until core PLL is re-locked */
127 accr |= ACCR_XSPCLK(XSPCLK_NONE);
128
129 xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
130
131 ACCR = accr;
132 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
133
134 while ((ACSR & mask) != (accr & mask))
135 cpu_relax();
136}
137
138static void __update_bus_freq(struct pxa3xx_freq_info *info)
139{
140 uint32_t mask;
141 uint32_t accr = ACCR;
142
143 mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
144 ACCR_DMCFS_MASK;
145
146 accr &= ~mask;
147 accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
148 ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
149
150 ACCR = accr;
151
152 while ((ACSR & mask) != (accr & mask))
153 cpu_relax();
154}
155
156static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
157{
158 return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
159}
160
161static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
162{
163 return pxa3xx_get_clk_frequency_khz(0);
164}
165
166static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
167 unsigned int target_freq,
168 unsigned int relation)
169{
170 struct pxa3xx_freq_info *next;
171 struct cpufreq_freqs freqs;
172 unsigned long flags;
173 int idx;
174
175 if (policy->cpu != 0)
176 return -EINVAL;
177
178 /* Lookup the next frequency */
179 if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
180 target_freq, relation, &idx))
181 return -EINVAL;
182
183 next = &pxa3xx_freqs[idx];
184
185 freqs.old = policy->cur;
186 freqs.new = next->cpufreq_mhz * 1000;
187 freqs.cpu = policy->cpu;
188
189 pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
190 freqs.old / 1000, freqs.new / 1000,
191 (freqs.old == freqs.new) ? " (skipped)" : "");
192
193 if (freqs.old == target_freq)
194 return 0;
195
196 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
197
198 local_irq_save(flags);
199 __update_core_freq(next);
200 __update_bus_freq(next);
201 local_irq_restore(flags);
202
203 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
204
205 return 0;
206}
207
208static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
209{
210 int ret = -EINVAL;
211
212 /* set default policy and cpuinfo */
213 policy->cpuinfo.min_freq = 104000;
214 policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
215 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
216 policy->max = pxa3xx_get_clk_frequency_khz(0);
217 policy->cur = policy->min = policy->max;
218
219 if (cpu_is_pxa300() || cpu_is_pxa310())
220 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
221
222 if (cpu_is_pxa320())
223 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
224
225 if (ret) {
226 pr_err("failed to setup frequency table\n");
227 return ret;
228 }
229
230 pr_info("CPUFREQ support for PXA3xx initialized\n");
231 return 0;
232}
233
234static struct cpufreq_driver pxa3xx_cpufreq_driver = {
235 .verify = pxa3xx_cpufreq_verify,
236 .target = pxa3xx_cpufreq_set,
237 .init = pxa3xx_cpufreq_init,
238 .get = pxa3xx_cpufreq_get,
239 .name = "pxa3xx-cpufreq",
240};
241
242static int __init cpufreq_init(void)
243{
244 if (cpu_is_pxa3xx())
245 return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
246
247 return 0;
248}
249module_init(cpufreq_init);
250
251static void __exit cpufreq_exit(void)
252{
253 cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
254}
255module_exit(cpufreq_exit);
256
257MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
258MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index daa86d39ed9e..666094315ab1 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1107,8 +1107,33 @@ struct resource pxa_resource_gpio[] = {
1107 }, 1107 },
1108}; 1108};
1109 1109
1110struct platform_device pxa_device_gpio = { 1110struct platform_device pxa25x_device_gpio = {
1111 .name = "pxa-gpio", 1111#ifdef CONFIG_CPU_PXA26x
1112 .name = "pxa26x-gpio",
1113#else
1114 .name = "pxa25x-gpio",
1115#endif
1116 .id = -1,
1117 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1118 .resource = pxa_resource_gpio,
1119};
1120
1121struct platform_device pxa27x_device_gpio = {
1122 .name = "pxa27x-gpio",
1123 .id = -1,
1124 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1125 .resource = pxa_resource_gpio,
1126};
1127
1128struct platform_device pxa3xx_device_gpio = {
1129 .name = "pxa3xx-gpio",
1130 .id = -1,
1131 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1132 .resource = pxa_resource_gpio,
1133};
1134
1135struct platform_device pxa93x_device_gpio = {
1136 .name = "pxa93x-gpio",
1112 .id = -1, 1137 .id = -1,
1113 .num_resources = ARRAY_SIZE(pxa_resource_gpio), 1138 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1114 .resource = pxa_resource_gpio, 1139 .resource = pxa_resource_gpio,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 1475db107254..0f3fd0d65b12 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -16,7 +16,6 @@ extern struct platform_device pxa_device_ficp;
16extern struct platform_device sa1100_device_rtc; 16extern struct platform_device sa1100_device_rtc;
17extern struct platform_device pxa_device_rtc; 17extern struct platform_device pxa_device_rtc;
18extern struct platform_device pxa_device_ac97; 18extern struct platform_device pxa_device_ac97;
19extern struct platform_device pxa_device_gpio;
20 19
21extern struct platform_device pxa27x_device_i2c_power; 20extern struct platform_device pxa27x_device_i2c_power;
22extern struct platform_device pxa27x_device_ohci; 21extern struct platform_device pxa27x_device_ohci;
@@ -46,4 +45,9 @@ extern struct platform_device pxa_device_asoc_ssp2;
46extern struct platform_device pxa_device_asoc_ssp3; 45extern struct platform_device pxa_device_asoc_ssp3;
47extern struct platform_device pxa_device_asoc_ssp4; 46extern struct platform_device pxa_device_asoc_ssp4;
48 47
48extern struct platform_device pxa25x_device_gpio;
49extern struct platform_device pxa27x_device_gpio;
50extern struct platform_device pxa3xx_device_gpio;
51extern struct platform_device pxa93x_device_gpio;
52
49void __init pxa_register_device(struct platform_device *dev, void *data); 53void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
deleted file mode 100644
index 70b112e8ef68..000000000000
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ /dev/null
@@ -1,23 +0,0 @@
1/* arch/arm/mach-pxa/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include "hardware.h"
15
16 .macro addruart, rp, rv, tmp
17 mov \rp, #0x00100000
18 orr \rv, \rp, #io_p2v(0x40000000) @ virtual
19 orr \rp, \rp, #0x40000000 @ physical
20 .endm
21
22#define UART_SHIFT 2
23#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pxa/include/mach/generic.h b/arch/arm/mach-pxa/include/mach/generic.h
new file mode 100644
index 000000000000..665542e0c9e2
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/generic.h
@@ -0,0 +1 @@
#include "../../generic.h"
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3f5171eaf67b..f2c28972084d 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -208,7 +208,11 @@ static struct clk_lookup pxa25x_clkregs[] = {
208 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), 208 INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
209 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), 209 INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
210 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), 210 INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
211 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), 211#ifdef CONFIG_CPU_PXA26x
212 INIT_CLKREG(&clk_dummy, "pxa26x-gpio", NULL),
213#else
214 INIT_CLKREG(&clk_dummy, "pxa25x-gpio", NULL),
215#endif
212 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), 216 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
213}; 217};
214 218
@@ -340,7 +344,8 @@ void __init pxa25x_map_io(void)
340} 344}
341 345
342static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = { 346static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
343 .gpio_set_wake = gpio_set_wake, 347 .irq_base = PXA_GPIO_TO_IRQ(0),
348 .gpio_set_wake = gpio_set_wake,
344}; 349};
345 350
346static struct platform_device *pxa25x_devices[] __initdata = { 351static struct platform_device *pxa25x_devices[] __initdata = {
@@ -375,7 +380,7 @@ static int __init pxa25x_init(void)
375 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 380 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
376 register_syscore_ops(&pxa2xx_clock_syscore_ops); 381 register_syscore_ops(&pxa2xx_clock_syscore_ops);
377 382
378 pxa_register_device(&pxa_device_gpio, &pxa25x_gpio_info); 383 pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
379 ret = platform_add_devices(pxa25x_devices, 384 ret = platform_add_devices(pxa25x_devices,
380 ARRAY_SIZE(pxa25x_devices)); 385 ARRAY_SIZE(pxa25x_devices));
381 if (ret) 386 if (ret)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 3203a9f5b4a2..301471a07a10 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -237,7 +237,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
237 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), 237 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
238 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), 238 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
239 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), 239 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
240 INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL), 240 INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
241 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), 241 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
242}; 242};
243 243
@@ -431,7 +431,8 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
431} 431}
432 432
433static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { 433static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
434 .gpio_set_wake = gpio_set_wake, 434 .irq_base = PXA_GPIO_TO_IRQ(0),
435 .gpio_set_wake = gpio_set_wake,
435}; 436};
436 437
437static struct platform_device *devices[] __initdata = { 438static struct platform_device *devices[] __initdata = {
@@ -470,7 +471,7 @@ static int __init pxa27x_init(void)
470 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 471 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
471 register_syscore_ops(&pxa2xx_clock_syscore_ops); 472 register_syscore_ops(&pxa2xx_clock_syscore_ops);
472 473
473 pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info); 474 pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
474 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 475 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
475 } 476 }
476 477
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 656a1bb16d14..87011f3de69d 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -15,6 +15,7 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/gpio-pxa.h>
18#include <linux/pm.h> 19#include <linux/pm.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
20#include <linux/irq.h> 21#include <linux/irq.h>
@@ -92,7 +93,8 @@ static struct clk_lookup pxa3xx_clkregs[] = {
92 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), 93 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
93 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), 94 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
94 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), 95 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
95 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL), 96 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
97 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
96 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), 98 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
97}; 99};
98 100
@@ -435,8 +437,11 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
435 pxa_register_device(&pxa3xx_device_i2c_power, info); 437 pxa_register_device(&pxa3xx_device_i2c_power, info);
436} 438}
437 439
440static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
441 .irq_base = PXA_GPIO_TO_IRQ(0),
442};
443
438static struct platform_device *devices[] __initdata = { 444static struct platform_device *devices[] __initdata = {
439 &pxa_device_gpio,
440 &pxa27x_device_udc, 445 &pxa27x_device_udc,
441 &pxa_device_pmu, 446 &pxa_device_pmu,
442 &pxa_device_i2s, 447 &pxa_device_i2s,
@@ -482,8 +487,18 @@ static int __init pxa3xx_init(void)
482 register_syscore_ops(&pxa3xx_mfp_syscore_ops); 487 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
483 register_syscore_ops(&pxa3xx_clock_syscore_ops); 488 register_syscore_ops(&pxa3xx_clock_syscore_ops);
484 489
485 if (!of_have_populated_dt()) 490 if (of_have_populated_dt())
486 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 491 return 0;
492
493 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
494 if (ret)
495 return ret;
496 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
497 platform_device_add_data(&pxa3xx_device_gpio,
498 &pxa3xx_gpio_pdata,
499 sizeof(pxa3xx_gpio_pdata));
500 ret = platform_device_register(&pxa3xx_device_gpio);
501 }
487 } 502 }
488 503
489 return ret; 504 return ret;
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 8aeacf908784..ab624487cf39 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -12,12 +12,15 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/irq.h>
17#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
16#include <linux/irq.h>
17#include <linux/gpio-pxa.h>
18#include <linux/platform_device.h>
18 19
19#include <mach/pxa930.h> 20#include <mach/pxa930.h>
20 21
22#include "devices.h"
23
21static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = { 24static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
22 25
23 MFP_ADDR(GPIO0, 0x02e0), 26 MFP_ADDR(GPIO0, 0x02e0),
@@ -190,11 +193,21 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
190 MFP_ADDR_END, 193 MFP_ADDR_END,
191}; 194};
192 195
196static struct pxa_gpio_platform_data pxa93x_gpio_pdata = {
197 .irq_base = PXA_GPIO_TO_IRQ(0),
198};
199
193static int __init pxa930_init(void) 200static int __init pxa930_init(void)
194{ 201{
202 int ret = 0;
203
195 if (cpu_is_pxa93x()) { 204 if (cpu_is_pxa93x()) {
196 mfp_init_base(io_p2v(MFPR_BASE)); 205 mfp_init_base(io_p2v(MFPR_BASE));
197 mfp_init_addr(pxa930_mfp_addr_map); 206 mfp_init_addr(pxa930_mfp_addr_map);
207 platform_device_add_data(&pxa93x_device_gpio,
208 &pxa93x_gpio_pdata,
209 sizeof(pxa93x_gpio_pdata));
210 ret = platform_device_register(&pxa93x_device_gpio);
198 } 211 }
199 212
200 if (cpu_is_pxa935()) 213 if (cpu_is_pxa935())
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 23:06:55 -0500