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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-05-18 09:57:59 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-06-02 08:49:17 -0400
commitffdf786291636137ef2d51c3a5d340793032aa28 (patch)
tree0377c58d46ca76c3e1c2415a713d4ac0b9226fc8 /arch/arm/mach-pxa/standby.S
parent4e5e8de0dbdeb08df2b4c15fa2b0ba2216091793 (diff)
[ARM] pxa: Add PXA3_ prefix to PXA3 specific constants
standby.S contains both PXA2 and PXA3 specific code. The PXA3 specific constants clash with the PXA2 ones, so give them a prefix. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/standby.S')
-rw-r--r--arch/arm/mach-pxa/standby.S82
1 files changed, 41 insertions, 41 deletions
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S
index 167412e6bec8..a37ef1c4b9e9 100644
--- a/arch/arm/mach-pxa/standby.S
+++ b/arch/arm/mach-pxa/standby.S
@@ -35,20 +35,20 @@ ENTRY(pxa_cpu_standby)
35 35
36#ifdef CONFIG_PXA3xx 36#ifdef CONFIG_PXA3xx
37 37
38#define MDCNFG 0x0000 38#define PXA3_MDCNFG 0x0000
39#define MDCNFG_DMCEN (1 << 30) 39#define PXA3_MDCNFG_DMCEN (1 << 30)
40#define DDR_HCAL 0x0060 40#define PXA3_DDR_HCAL 0x0060
41#define DDR_HCAL_HCRNG 0x1f 41#define PXA3_DDR_HCAL_HCRNG 0x1f
42#define DDR_HCAL_HCPROG (1 << 28) 42#define PXA3_DDR_HCAL_HCPROG (1 << 28)
43#define DDR_HCAL_HCEN (1 << 31) 43#define PXA3_DDR_HCAL_HCEN (1 << 31)
44#define DMCIER 0x0070 44#define PXA3_DMCIER 0x0070
45#define DMCIER_EDLP (1 << 29) 45#define PXA3_DMCIER_EDLP (1 << 29)
46#define DMCISR 0x0078 46#define PXA3_DMCISR 0x0078
47#define RCOMP 0x0100 47#define PXA3_RCOMP 0x0100
48#define RCOMP_SWEVAL (1 << 31) 48#define PXA3_RCOMP_SWEVAL (1 << 31)
49 49
50ENTRY(pm_enter_standby_start) 50ENTRY(pm_enter_standby_start)
51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG) 51 mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
52 add r1, r1, #0x00100000 52 add r1, r1, #0x00100000
53 53
54 /* 54 /*
@@ -59,54 +59,54 @@ ENTRY(pm_enter_standby_start)
59 * This also means that only the dynamic memory controller 59 * This also means that only the dynamic memory controller
60 * can be reliably accessed in the code following standby. 60 * can be reliably accessed in the code following standby.
61 */ 61 */
62 ldr r2, [r1] @ Dummy read MDCNFG 62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
63 63
64 mcr p14, 0, r0, c7, c0, 0 64 mcr p14, 0, r0, c7, c0, 0
65 .rept 8 65 .rept 8
66 nop 66 nop
67 .endr 67 .endr
68 68
69 ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN 69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #DDR_HCAL_HCEN 70 bic r0, r0, #PXA3_DDR_HCAL_HCEN
71 str r0, [r1, #DDR_HCAL] 71 str r0, [r1, #PXA3_DDR_HCAL]
721: ldr r0, [r1, #DDR_HCAL] 721: ldr r0, [r1, #PXA3_DDR_HCAL]
73 tst r0, #DDR_HCAL_HCEN 73 tst r0, #PXA3_DDR_HCAL_HCEN
74 bne 1b 74 bne 1b
75 75
76 ldr r0, [r1, #RCOMP] @ Initiate RCOMP 76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
77 orr r0, r0, #RCOMP_SWEVAL 77 orr r0, r0, #PXA3_RCOMP_SWEVAL
78 str r0, [r1, #RCOMP] 78 str r0, [r1, #PXA3_RCOMP]
79 79
80 mov r0, #~0 @ Clear interrupts 80 mov r0, #~0 @ Clear interrupts
81 str r0, [r1, #DMCISR] 81 str r0, [r1, #PXA3_DMCISR]
82 82
83 ldr r0, [r1, #DMCIER] @ set DMIER[EDLP] 83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
84 orr r0, r0, #DMCIER_EDLP 84 orr r0, r0, #PXA3_DMCIER_EDLP
85 str r0, [r1, #DMCIER] 85 str r0, [r1, #PXA3_DMCIER]
86 86
87 ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN 87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
88 bic r0, r0, #DDR_HCAL_HCRNG 88 bic r0, r0, #PXA3_DDR_HCAL_HCRNG
89 orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG 89 orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
90 str r0, [r1, #DDR_HCAL] 90 str r0, [r1, #PXA3_DDR_HCAL]
91 91
921: ldr r0, [r1, #DMCISR] 921: ldr r0, [r1, #PXA3_DMCISR]
93 tst r0, #DMCIER_EDLP 93 tst r0, #PXA3_DMCIER_EDLP
94 beq 1b 94 beq 1b
95 95
96 ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN] 96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
97 orr r0, r0, #MDCNFG_DMCEN 97 orr r0, r0, #PXA3_MDCNFG_DMCEN
98 str r0, [r1, #MDCNFG] 98 str r0, [r1, #PXA3_MDCNFG]
991: ldr r0, [r1, #MDCNFG] 991: ldr r0, [r1, #PXA3_MDCNFG]
100 tst r0, #MDCNFG_DMCEN 100 tst r0, #PXA3_MDCNFG_DMCEN
101 beq 1b 101 beq 1b
102 102
103 ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG] 103 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
104 orr r0, r0, #2 @ HCRNG 104 orr r0, r0, #2 @ HCRNG
105 str r0, [r1, #DDR_HCAL] 105 str r0, [r1, #PXA3_DDR_HCAL]
106 106
107 ldr r0, [r1, #DMCIER] @ Clear the interrupt 107 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
108 bic r0, r0, #0x20000000 108 bic r0, r0, #0x20000000
109 str r0, [r1, #DMCIER] 109 str r0, [r1, #PXA3_DMCIER]
110 110
111 mov pc, lr 111 mov pc, lr
112ENTRY(pm_enter_standby_end) 112ENTRY(pm_enter_standby_end)