diff options
author | Eric Miao <eric.miao@marvell.com> | 2008-09-03 06:06:34 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-09-26 18:43:20 -0400 |
commit | 5a3d96519040f9736b9f8089e2a1e33a81a6eafe (patch) | |
tree | be92df6b14ba6c9e420bc45d13a76b812991bb0c /arch/arm/mach-pxa/pxa27x.c | |
parent | 4fa7c24e94b3f5bfb367bb847af3c3abd8cca3c0 (diff) |
[ARM] pxa: better MFP low power state support for pxa25x/pxa27x
When configured as a specific low power state: MFP_LPM_DRIVE_LOW,
MFP_LPM_DRIVE_HIGH, the corresponding GPDR register bit during
low power mode shall be re-configured as output (if they are not
configured so), thus the PGSRx bits can output.
Create an additional low power values GPDR registers, and properly
save/restore the GAFR + GPDR registers when doing suspend/resume.
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/pxa27x.c')
-rw-r--r-- | arch/arm/mach-pxa/pxa27x.c | 37 |
1 files changed, 6 insertions, 31 deletions
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index f9f6a9c31f4b..0288665ad035 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -183,36 +183,18 @@ static struct clk pxa27x_clks[] = { | |||
183 | * More ones like CP and general purpose register values are preserved | 183 | * More ones like CP and general purpose register values are preserved |
184 | * with the stack pointer in sleep.S. | 184 | * with the stack pointer in sleep.S. |
185 | */ | 185 | */ |
186 | enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, | 186 | enum { |
187 | |||
188 | SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, | ||
189 | SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, | ||
190 | SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, | ||
191 | SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U, | ||
192 | |||
193 | SLEEP_SAVE_PSTR, | 187 | SLEEP_SAVE_PSTR, |
194 | |||
195 | SLEEP_SAVE_CKEN, | 188 | SLEEP_SAVE_CKEN, |
196 | |||
197 | SLEEP_SAVE_MDREFR, | 189 | SLEEP_SAVE_MDREFR, |
198 | SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, | 190 | SLEEP_SAVE_PCFR, |
199 | SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, | ||
200 | |||
201 | SLEEP_SAVE_COUNT | 191 | SLEEP_SAVE_COUNT |
202 | }; | 192 | }; |
203 | 193 | ||
204 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | 194 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) |
205 | { | 195 | { |
206 | SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); | ||
207 | |||
208 | SAVE(GAFR0_L); SAVE(GAFR0_U); | ||
209 | SAVE(GAFR1_L); SAVE(GAFR1_U); | ||
210 | SAVE(GAFR2_L); SAVE(GAFR2_U); | ||
211 | SAVE(GAFR3_L); SAVE(GAFR3_U); | ||
212 | |||
213 | SAVE(MDREFR); | 196 | SAVE(MDREFR); |
214 | SAVE(PWER); SAVE(PCFR); SAVE(PRER); | 197 | SAVE(PCFR); |
215 | SAVE(PFER); SAVE(PKWR); | ||
216 | 198 | ||
217 | SAVE(CKEN); | 199 | SAVE(CKEN); |
218 | SAVE(PSTR); | 200 | SAVE(PSTR); |
@@ -223,21 +205,12 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | |||
223 | /* ensure not to come back here if it wasn't intended */ | 205 | /* ensure not to come back here if it wasn't intended */ |
224 | PSPR = 0; | 206 | PSPR = 0; |
225 | 207 | ||
226 | /* restore registers */ | ||
227 | RESTORE(GAFR0_L); RESTORE(GAFR0_U); | ||
228 | RESTORE(GAFR1_L); RESTORE(GAFR1_U); | ||
229 | RESTORE(GAFR2_L); RESTORE(GAFR2_U); | ||
230 | RESTORE(GAFR3_L); RESTORE(GAFR3_U); | ||
231 | RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); | ||
232 | |||
233 | RESTORE(MDREFR); | 208 | RESTORE(MDREFR); |
234 | RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER); | 209 | RESTORE(PCFR); |
235 | RESTORE(PFER); RESTORE(PKWR); | ||
236 | 210 | ||
237 | PSSR = PSSR_RDH | PSSR_PH; | 211 | PSSR = PSSR_RDH | PSSR_PH; |
238 | 212 | ||
239 | RESTORE(CKEN); | 213 | RESTORE(CKEN); |
240 | |||
241 | RESTORE(PSTR); | 214 | RESTORE(PSTR); |
242 | } | 215 | } |
243 | 216 | ||
@@ -376,6 +349,8 @@ static struct sys_device pxa27x_sysdev[] = { | |||
376 | { | 349 | { |
377 | .cls = &pxa_irq_sysclass, | 350 | .cls = &pxa_irq_sysclass, |
378 | }, { | 351 | }, { |
352 | .cls = &pxa2xx_mfp_sysclass, | ||
353 | }, { | ||
379 | .cls = &pxa_gpio_sysclass, | 354 | .cls = &pxa_gpio_sysclass, |
380 | }, | 355 | }, |
381 | }; | 356 | }; |