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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2007-08-20 05:18:02 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-10-12 16:14:55 -0400
commita6dba20c5c7b3a18d69bcbd60a1d2ebc0536f0ce (patch)
tree954e4f3aa86f730fc4b8834126e7886022c0dccf /arch/arm/mach-pxa/pxa25x.c
parent00dc4f949e7423769de1a160c590840534ea3a70 (diff)
[ARM] pxa: introduce clk support for PXA SoC clocks
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/pxa25x.c')
-rw-r--r--arch/arm/mach-pxa/pxa25x.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index bcf3f0a78463..62a770121bfa 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -30,6 +30,7 @@
30 30
31#include "generic.h" 31#include "generic.h"
32#include "devices.h" 32#include "devices.h"
33#include "clock.h"
33 34
34/* 35/*
35 * Various clock factors driven by the CCCR register. 36 * Various clock factors driven by the CCCR register.
@@ -94,6 +95,41 @@ unsigned int pxa25x_get_memclk_frequency_10khz(void)
94 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 95 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
95} 96}
96 97
98static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
99{
100 return pxa25x_get_memclk_frequency_10khz() * 10000;
101}
102
103static const struct clkops clk_pxa25x_lcd_ops = {
104 .enable = clk_cken_enable,
105 .disable = clk_cken_disable,
106 .getrate = clk_pxa25x_lcd_getrate,
107};
108
109/*
110 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
111 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
112 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
113 */
114static struct clk pxa25x_clks[] = {
115 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
116 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
117 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
118 INIT_CKEN("UARTCLK", STUART, 14745600, 1, &pxa_device_stuart.dev),
119 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
120 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
121 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
122 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
123 /*
124 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
125 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
126 INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
127 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
128 INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
129 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
130 */
131};
132
97#ifdef CONFIG_PM 133#ifdef CONFIG_PM
98 134
99#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 135#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
@@ -215,6 +251,8 @@ static int __init pxa25x_init(void)
215 int ret = 0; 251 int ret = 0;
216 252
217 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 253 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
254 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
255
218 if ((ret = pxa_init_dma(16))) 256 if ((ret = pxa_init_dma(16)))
219 return ret; 257 return ret;
220#ifdef CONFIG_PM 258#ifdef CONFIG_PM