[ARM] pxa/balloon3: Add NAND driver

The NAND support is implemented through the gen_nand driver.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

1 files changed, 25 insertions, 3 deletions

diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 238f887ebaea..eec92e6fd7cf 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -31,12 +31,15 @@ enum balloon3_features {
 #define BALLOON3_CF_CONTROL_REG         (BALLOON3_FPGA_VIRT + 0x00e00008)
 /* FPGA / CPLD version register */
 #define BALLOON3_FPGA_VER               (BALLOON3_FPGA_VIRT + 0x00e0001c)
+/* FPGA / CPLD registers for NAND flash */
+#define BALLOON3_NAND_BASE              (PXA_CS4_PHYS + 0x00e00000)
+#define BALLOON3_NAND_IO_REG            (BALLOON3_FPGA_VIRT + 0x00e00000)
+#define BALLOON3_NAND_CONTROL2_REG      (BALLOON3_FPGA_VIRT + 0x00e00010)
+#define BALLOON3_NAND_STAT_REG          (BALLOON3_FPGA_VIRT + 0x00e00010)
+#define BALLOON3_NAND_CONTROL_REG       (BALLOON3_FPGA_VIRT + 0x00e00014)
 
-#define BALLOON3_NANDIO_IO_REG          (BALLOON3_FPGA_VIRT + 0x00e00000)
 /* fpga/cpld interrupt control register */
 #define BALLOON3_INT_CONTROL_REG        (BALLOON3_FPGA_VIRT + 0x00e0000C)
-#define BALLOON3_NANDIO_CTL2_REG        (BALLOON3_FPGA_VIRT + 0x00e00010)
-#define BALLOON3_NANDIO_CTL_REG         (BALLOON3_FPGA_VIRT + 0x00e00014)
 #define BALLOON3_VERSION_REG            (BALLOON3_FPGA_VIRT + 0x00e0001c)
 
 #define BALLOON3_SAMOSA_ADDR_REG        (BALLOON3_FPGA_VIRT + 0x00c00000)
@@ -56,6 +59,22 @@ enum balloon3_features {
 #define BALLOON3_BP_CF_NRDY_IRQ         BALLOON3_IRQ(0)
 #define BALLOON3_BP_NSTSCHG_IRQ         BALLOON3_IRQ(1)
 
+/* NAND Control register */
+#define BALLOON3_NAND_CONTROL_FLWP      (1 << 7)
+#define BALLOON3_NAND_CONTROL_FLSE      (1 << 6)
+#define BALLOON3_NAND_CONTROL_FLCE3     (1 << 5)
+#define BALLOON3_NAND_CONTROL_FLCE2     (1 << 4)
+#define BALLOON3_NAND_CONTROL_FLCE1     (1 << 3)
+#define BALLOON3_NAND_CONTROL_FLCE0     (1 << 2)
+#define BALLOON3_NAND_CONTROL_FLALE     (1 << 1)
+#define BALLOON3_NAND_CONTROL_FLCLE     (1 << 0)
+
+/* NAND Status register */
+#define BALLOON3_NAND_STAT_RNB          (1 << 0)
+
+/* NAND Control2 register */
+#define BALLOON3_NAND_CONTROL2_16BIT    (1 << 0)
+
 /* GPIOs for irqs */
 #define BALLOON3_GPIO_AUX_NIRQ          (94)
 #define BALLOON3_GPIO_CODEC_IRQ         (95)
@@ -69,6 +88,9 @@ enum balloon3_features {
 
 #define BALLOON3_GPIO_S0_CD             (105)
 
+/* NAND */
+#define BALLOON3_GPIO_RUN_NAND          (102)
+
 /* PCF8574A Leds */
 #define BALLOON3_PCF_GPIO_BASE          160
 #define BALLOON3_PCF_GPIO_LED0          (BALLOON3_PCF_GPIO_BASE + 0)