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authorEric Miao <eric.miao@marvell.com>2009-01-19 23:09:06 -0500
committerEric Miao <eric.miao@marvell.com>2009-03-22 22:11:33 -0400
commit38f539a608c9a3b40b30f1892bd5f9a38f4e5ffe (patch)
treefeb9c3ee23fe75151f73e8916c1afeb7c562e0dd /arch/arm/mach-pxa/include/mach
parentbd5ce4332328c1fe473690a86b2e6a4157be038f (diff)
[ARM] pxa: move common GPIO handling code into plat-pxa
1. add common GPIO handling code into [arch/arm/plat-pxa] 2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors should implement its own <mach/gpio.h>, provide the following required definitions and '#include <plat/gpio.h>' in the end: - GPIO_REGS_VIRT for mapped virtual address of the GPIO registers' physical I/O memory - macros of GPLR(), GPSR(), GPDR() for constant optimization for functions gpio_{set,get}_value() (so that bit-bang code can still have tolerable performance) - NR_BUILTIN_GPIO for the number of onchip GPIO - definitions of __gpio_is_inverted() and __gpio_is_occupied(), they can be either macros or inlined functions Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm/mach-pxa/include/mach')
-rw-r--r--arch/arm/mach-pxa/include/mach/gpio.h32
1 files changed, 1 insertions, 31 deletions
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index c72c89a2285e..b024a8b37439 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -99,40 +99,12 @@
99#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) 99#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
100 100
101 101
102/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85).
103 * Those cases currently cause holes in the GPIO number space, the
104 * actual number of the last GPIO is recorded by 'pxa_last_gpio'.
105 */
106extern int pxa_last_gpio;
107
108#define NR_BUILTIN_GPIO 128 102#define NR_BUILTIN_GPIO 128
109 103
110static inline int gpio_get_value(unsigned gpio)
111{
112 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO))
113 return GPLR(gpio) & GPIO_bit(gpio);
114 else
115 return __gpio_get_value(gpio);
116}
117
118static inline void gpio_set_value(unsigned gpio, int value)
119{
120 if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) {
121 if (value)
122 GPSR(gpio) = GPIO_bit(gpio);
123 else
124 GPCR(gpio) = GPIO_bit(gpio);
125 } else {
126 __gpio_set_value(gpio, value);
127 }
128}
129
130#define gpio_cansleep __gpio_cansleep
131#define gpio_to_bank(gpio) ((gpio) >> 5) 104#define gpio_to_bank(gpio) ((gpio) >> 5)
132#define gpio_to_irq(gpio) IRQ_GPIO(gpio) 105#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
133#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) 106#define irq_to_gpio(irq) IRQ_TO_GPIO(irq)
134 107
135
136#ifdef CONFIG_CPU_PXA26x 108#ifdef CONFIG_CPU_PXA26x
137/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, 109/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
138 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 110 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
@@ -165,7 +137,5 @@ static inline int __gpio_is_occupied(unsigned gpio)
165 return GPDR(gpio) & GPIO_bit(gpio); 137 return GPDR(gpio) & GPIO_bit(gpio);
166} 138}
167 139
168typedef int (*set_wake_t)(unsigned int irq, unsigned int on); 140#include <plat/gpio.h>
169
170extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn);
171#endif 141#endif